1 #include <linux/errno.h> 2 #include <linux/signal.h> 3 #include <linux/tty.h> 4 #include <linux/tty_flip.h> 5 #include <linux/serial.h> 6 #include <linux/serial_reg.h> 7 #include <linux/ioport.h> 8 #include <linux/mm.h> 9 #include <linux/sched.h> 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/slab.h> 14 #include <linux/wait.h> 15 #include <linux/tty_driver.h> 16 #include <linux/pci.h> 17 #include <linux/circ_buf.h> 18 19 #include <asm/uaccess.h> 20 #include <asm/io.h> 21 #include <asm/irq.h> 22 #include <asm/segment.h> 23 #include <asm/serial.h> 24 #include <linux/interrupt.h> 25 26 27 #include <linux/parport.h> 28 #include <linux/ctype.h> 29 #include <linux/poll.h> 30 31 32 #define MP_TERMIOS ktermios 33 34 #include "sb_mp_register.h" 35 #include "sb_ser_core.h" 36 37 #define DRIVER_VERSION "1.1" 38 #define DRIVER_DATE "2012/01/05" 39 #define DRIVER_AUTHOR "SYSTEMBASE<tech@sysbas.com>" 40 #define DRIVER_DESC "SystemBase PCI/PCIe Multiport Core" 41 42 #define SB_TTY_MP_MAJOR 54 43 #define PCI_VENDOR_ID_MULTIPORT 0x14A1 44 45 #define PCI_DEVICE_ID_MP1 0x4d01 46 #define PCI_DEVICE_ID_MP2 0x4d02 47 #define PCI_DEVICE_ID_MP4 0x4d04 48 #define PCI_DEVICE_ID_MP4A 0x4d54 49 #define PCI_DEVICE_ID_MP6 0x4d06 50 #define PCI_DEVICE_ID_MP6A 0x4d56 51 #define PCI_DEVICE_ID_MP8 0x4d08 52 #define PCI_DEVICE_ID_MP32 0x4d32 53 /* Parallel port */ 54 #define PCI_DEVICE_ID_MP1P 0x4301 55 #define PCI_DEVICE_ID_MP2S1P 0x4303 56 57 #define PCIE_DEVICE_ID_MP1 0x4501 58 #define PCIE_DEVICE_ID_MP2 0x4502 59 #define PCIE_DEVICE_ID_MP4 0x4504 60 #define PCIE_DEVICE_ID_MP8 0x4508 61 #define PCIE_DEVICE_ID_MP32 0x4532 62 63 #define PCIE_DEVICE_ID_MP1E 0x4e01 64 #define PCIE_DEVICE_ID_MP2E 0x4e02 65 #define PCIE_DEVICE_ID_MP2B 0x4b02 66 #define PCIE_DEVICE_ID_MP4B 0x4b04 67 #define PCIE_DEVICE_ID_MP8B 0x4b08 68 69 #define PCI_DEVICE_ID_GT_MP4 0x0004 70 #define PCI_DEVICE_ID_GT_MP4A 0x0054 71 #define PCI_DEVICE_ID_GT_MP6 0x0006 72 #define PCI_DEVICE_ID_GT_MP6A 0x0056 73 #define PCI_DEVICE_ID_GT_MP8 0x0008 74 #define PCI_DEVICE_ID_GT_MP32 0x0032 75 76 #define PCIE_DEVICE_ID_GT_MP1 0x1501 77 #define PCIE_DEVICE_ID_GT_MP2 0x1502 78 #define PCIE_DEVICE_ID_GT_MP4 0x1504 79 #define PCIE_DEVICE_ID_GT_MP8 0x1508 80 #define PCIE_DEVICE_ID_GT_MP32 0x1532 81 82 #define PCI_DEVICE_ID_MP4M 0x4604 //modem 83 84 #define MAX_MP_DEV 8 85 #define BD_MAX_PORT 32 /* Max serial port in one board */ 86 #define MAX_MP_PORT 256 /* Max serial port in one PC */ 87 88 #define PORT_16C105XA 3 89 #define PORT_16C105X 2 90 #define PORT_16C55X 1 91 92 #define ENABLE 1 93 #define DISABLE 0 94 95 /* ioctls */ 96 #define TIOCGNUMOFPORT 0x545F 97 #define TIOCSMULTIECHO 0x5440 98 #define TIOCSPTPNOECHO 0x5441 99 100 #define TIOCGOPTIONREG 0x5461 101 #define TIOCGDISABLEIRQ 0x5462 102 #define TIOCGENABLEIRQ 0x5463 103 #define TIOCGSOFTRESET 0x5464 104 #define TIOCGSOFTRESETR 0x5465 105 #define TIOCGREGINFO 0x5466 106 #define TIOCGGETLSR 0x5467 107 #define TIOCGGETDEVID 0x5468 108 #define TIOCGGETBDNO 0x5469 109 #define TIOCGGETINTERFACE 0x546A 110 #define TIOCGGETREV 0x546B 111 #define TIOCGGETNRPORTS 0x546C 112 #define TIOCGGETPORTTYPE 0x546D 113 #define GETDEEPFIFO 0x54AA 114 #define SETDEEPFIFO 0x54AB 115 #define SETFCR 0x54BA 116 #define SETTTR 0x54B1 117 #define SETRTR 0x54B2 118 #define GETTTR 0x54B3 119 #define GETRTR 0x54B4 120 121 /* multi-drop mode related ioctl commands */ 122 #define TIOCSMULTIDROP 0x5470 123 #define TIOCSMDADDR 0x5471 124 #define TIOCGMDADDR 0x5472 125 #define TIOCSENDADDR 0x5473 126 127 128 /* serial interface */ 129 #define RS232 1 130 #define RS422PTP 2 131 #define RS422MD 3 132 #define RS485NE 4 133 #define RS485ECHO 5 134 135 #define serial_inp(up, offset) serial_in(up, offset) 136 #define serial_outp(up, offset, value) serial_out(up, offset, value) 137 138 #define PASS_LIMIT 256 139 #define is_real_interrupt(irq) ((irq) != 0) 140 141 #define PROBE_ANY (~0) 142 143 static DEFINE_MUTEX(mp_mutex); 144 #define MP_MUTEX_LOCK(x) mutex_lock(&(x)) 145 #define MP_MUTEX_UNLOCK(x) mutex_unlock(&(x)) 146 #define MP_STATE_LOCK(x) mutex_lock(&((x)->mutex)) 147 #define MP_STATE_UNLOCK(x) mutex_unlock(&((x)->mutex)) 148 149 150 #define UART_LSR_SPECIAL 0x1E 151 152 #define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8) 153 #define uart_users(state) ((state)->count + ((state)->info ? (state)->info->blocked_open : 0)) 154 155 156 //#define MP_DEBUG 1 157 #undef MP_DEBUG 158 159 #ifdef MP_DEBUG 160 #define DPRINTK(x...) printk(x) 161 #else 162 #define DPRINTK(x...) do { } while (0) 163 #endif 164 165 #ifdef MP_DEBUG 166 #define DEBUG_AUTOCONF(fmt...) printk(fmt) 167 #else 168 #define DEBUG_AUTOCONF(fmt...) do { } while (0) 169 #endif 170 171 #ifdef MP_DEBUG 172 #define DEBUG_INTR(fmt...) printk(fmt) 173 #else 174 #define DEBUG_INTR(fmt...) do { } while (0) 175 #endif 176 177 #if defined(__i386__) && defined(CONFIG_M486) 178 #define SERIAL_INLINE 179 #endif 180 #ifdef SERIAL_INLINE 181 #define _INLINE_ inline 182 #else 183 #define _INLINE_ 184 #endif 185 186 #define TYPE_POLL 1 187 #define TYPE_INTERRUPT 2 188 189 190 struct mp_device_t { 191 unsigned short device_id; 192 unsigned char revision; 193 char *name; 194 unsigned long uart_access_addr; 195 unsigned long option_reg_addr; 196 unsigned long reserved_addr[4]; 197 int irq; 198 int nr_ports; 199 int poll_type; 200 }; 201 202 typedef struct mppcibrd { 203 char *name; 204 unsigned short vendor_id; 205 unsigned short device_id; 206 } mppcibrd_t; 207 208 static mppcibrd_t mp_pciboards[] = { 209 210 { "Multi-1 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1} , 211 { "Multi-2 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2} , 212 { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4} , 213 { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4A} , 214 { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6} , 215 { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6A} , 216 { "Multi-8 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP8} , 217 { "Multi-32 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP32} , 218 219 { "Multi-1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1P} , 220 { "Multi-2S1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2S1P} , 221 222 { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4} , 223 { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4A} , 224 { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6} , 225 { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6A} , 226 { "Multi-8(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP8} , 227 { "Multi-32(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP32} , 228 229 { "Multi-1 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1} , 230 { "Multi-2 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2} , 231 { "Multi-4 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4} , 232 { "Multi-8 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8} , 233 { "Multi-32 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP32} , 234 235 { "Multi-1 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1E} , 236 { "Multi-2 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2E} , 237 { "Multi-2 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2B} , 238 { "Multi-4 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4B} , 239 { "Multi-8 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8B} , 240 241 { "Multi-1(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP1} , 242 { "Multi-2(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP2} , 243 { "Multi-4(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP4} , 244 { "Multi-8(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP8} , 245 { "Multi-32(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP32} , 246 247 { "Multi-4M PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4M} , 248 }; 249 250 struct mp_port { 251 struct sb_uart_port port; 252 253 struct timer_list timer; /* "no irq" timer */ 254 struct list_head list; /* ports on this IRQ */ 255 unsigned int capabilities; /* port capabilities */ 256 unsigned short rev; 257 unsigned char acr; 258 unsigned char ier; 259 unsigned char lcr; 260 unsigned char mcr; 261 unsigned char mcr_mask; /* mask of user bits */ 262 unsigned char mcr_force; /* mask of forced bits */ 263 unsigned char lsr_break_flag; 264 265 void (*pm)(struct sb_uart_port *port, 266 unsigned int state, unsigned int old); 267 struct mp_device_t *device; 268 unsigned long interface_config_addr; 269 unsigned long option_base_addr; 270 unsigned char interface; 271 unsigned char poll_type; 272 }; 273 274 struct irq_info { 275 spinlock_t lock; 276 struct list_head *head; 277 }; 278 279 struct sb105x_uart_config { 280 char *name; 281 int dfl_xmit_fifo_size; 282 int flags; 283 }; 284 285 static const struct sb105x_uart_config uart_config[] = { 286 { "unknown", 1, 0 }, 287 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO }, 288 { "SB16C1050", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 289 { "SB16C1050A", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH }, 290 }; 291 292 293 294