1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <inki.dae@samsung.com> 6 * Joonyoung Shim <jy0922.shim@samsung.com> 7 * Seung-Woo Kim <sw0312.kim@samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 #ifndef _EXYNOS_DRM_H_ 15 #define _EXYNOS_DRM_H_ 16 17 #include <uapi/drm/exynos_drm.h> 18 19 /** 20 * A structure for lcd panel information. 21 * 22 * @timing: default video mode for initializing 23 * @width_mm: physical size of lcd width. 24 * @height_mm: physical size of lcd height. 25 */ 26 struct exynos_drm_panel_info { 27 struct fb_videomode timing; 28 u32 width_mm; 29 u32 height_mm; 30 }; 31 32 /** 33 * Platform Specific Structure for DRM based FIMD. 34 * 35 * @panel: default panel info for initializing 36 * @default_win: default window layer number to be used for UI. 37 * @bpp: default bit per pixel. 38 */ 39 struct exynos_drm_fimd_pdata { 40 struct exynos_drm_panel_info panel; 41 u32 vidcon0; 42 u32 vidcon1; 43 unsigned int default_win; 44 unsigned int bpp; 45 }; 46 47 /** 48 * Platform Specific Structure for DRM based HDMI. 49 * 50 * @hdmi_dev: device point to specific hdmi driver. 51 * @mixer_dev: device point to specific mixer driver. 52 * 53 * this structure is used for common hdmi driver and each device object 54 * would be used to access specific device driver(hdmi or mixer driver) 55 */ 56 struct exynos_drm_common_hdmi_pd { 57 struct device *hdmi_dev; 58 struct device *mixer_dev; 59 }; 60 61 /** 62 * Platform Specific Structure for DRM based HDMI core. 63 * 64 * @is_v13: set if hdmi version 13 is. 65 * @cfg_hpd: function pointer to configure hdmi hotplug detection pin 66 * @get_hpd: function pointer to get value of hdmi hotplug detection pin 67 */ 68 struct exynos_drm_hdmi_pdata { 69 bool is_v13; 70 void (*cfg_hpd)(bool external); 71 int (*get_hpd)(void); 72 }; 73 74 /** 75 * Platform Specific Structure for DRM based IPP. 76 * 77 * @inv_pclk: if set 1. invert pixel clock 78 * @inv_vsync: if set 1. invert vsync signal for wb 79 * @inv_href: if set 1. invert href signal 80 * @inv_hsync: if set 1. invert hsync signal for wb 81 */ 82 struct exynos_drm_ipp_pol { 83 unsigned int inv_pclk; 84 unsigned int inv_vsync; 85 unsigned int inv_href; 86 unsigned int inv_hsync; 87 }; 88 89 /** 90 * Platform Specific Structure for DRM based FIMC. 91 * 92 * @pol: current hardware block polarity settings. 93 * @clk_rate: current hardware clock rate. 94 */ 95 struct exynos_drm_fimc_pdata { 96 struct exynos_drm_ipp_pol pol; 97 int clk_rate; 98 }; 99 100 #endif /* _EXYNOS_DRM_H_ */ 101