1 /*
2 * linux/include/video/vga.h -- standard VGA chipset interaction
3 *
4 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
5 *
6 * Copyright history from vga16fb.c:
7 * Copyright 1999 Ben Pfaff and Petr Vandrovec
8 * Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
9 * Based on VESA framebuffer (c) 1998 Gerd Knorr
10 *
11 * This file is subject to the terms and conditions of the GNU General
12 * Public License. See the file COPYING in the main directory of this
13 * archive for more details.
14 *
15 */
16
17 #ifndef __linux_video_vga_h__
18 #define __linux_video_vga_h__
19
20 #include <linux/types.h>
21 #include <asm/io.h>
22 #include <asm/vga.h>
23 #include <asm/byteorder.h>
24
25
26 /* Some of the code below is taken from SVGAlib. The original,
27 unmodified copyright notice for that code is below. */
28 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */
29 /* */
30 /* This library is free software; you can redistribute it and/or */
31 /* modify it without any restrictions. This library is distributed */
32 /* in the hope that it will be useful, but without any warranty. */
33
34 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
35 /* partially copyrighted (C) 1993 by Hartmut Schirmer */
36
37 /* VGA data register ports */
38 #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */
39 #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */
40 #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */
41 #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */
42 #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */
43 #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */
44 #define VGA_MIS_R 0x3CC /* Misc Output Read Register */
45 #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */
46 #define VGA_FTC_R 0x3CA /* Feature Control Read Register */
47 #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */
48 #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */
49 #define VGA_PEL_D 0x3C9 /* PEL Data Register */
50 #define VGA_PEL_MSK 0x3C6 /* PEL mask register */
51
52 /* EGA-specific registers */
53 #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */
54 #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */
55
56 /* VGA index register ports */
57 #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */
58 #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */
59 #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */
60 #define VGA_GFX_I 0x3CE /* Graphics Controller Index */
61 #define VGA_SEQ_I 0x3C4 /* Sequencer Index */
62 #define VGA_PEL_IW 0x3C8 /* PEL Write Index */
63 #define VGA_PEL_IR 0x3C7 /* PEL Read Index */
64
65 /* standard VGA indexes max counts */
66 #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */
67 #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */
68 #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */
69 #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */
70 #define VGA_MIS_C 0x01 /* Number of Misc Output Register */
71
72 /* VGA misc register bit masks */
73 #define VGA_MIS_COLOR 0x01
74 #define VGA_MIS_ENB_MEM_ACCESS 0x02
75 #define VGA_MIS_DCLK_28322_720 0x04
76 #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08)
77 #define VGA_MIS_SEL_HIGH_PAGE 0x20
78
79 /* VGA CRT controller register indices */
80 #define VGA_CRTC_H_TOTAL 0
81 #define VGA_CRTC_H_DISP 1
82 #define VGA_CRTC_H_BLANK_START 2
83 #define VGA_CRTC_H_BLANK_END 3
84 #define VGA_CRTC_H_SYNC_START 4
85 #define VGA_CRTC_H_SYNC_END 5
86 #define VGA_CRTC_V_TOTAL 6
87 #define VGA_CRTC_OVERFLOW 7
88 #define VGA_CRTC_PRESET_ROW 8
89 #define VGA_CRTC_MAX_SCAN 9
90 #define VGA_CRTC_CURSOR_START 0x0A
91 #define VGA_CRTC_CURSOR_END 0x0B
92 #define VGA_CRTC_START_HI 0x0C
93 #define VGA_CRTC_START_LO 0x0D
94 #define VGA_CRTC_CURSOR_HI 0x0E
95 #define VGA_CRTC_CURSOR_LO 0x0F
96 #define VGA_CRTC_V_SYNC_START 0x10
97 #define VGA_CRTC_V_SYNC_END 0x11
98 #define VGA_CRTC_V_DISP_END 0x12
99 #define VGA_CRTC_OFFSET 0x13
100 #define VGA_CRTC_UNDERLINE 0x14
101 #define VGA_CRTC_V_BLANK_START 0x15
102 #define VGA_CRTC_V_BLANK_END 0x16
103 #define VGA_CRTC_MODE 0x17
104 #define VGA_CRTC_LINE_COMPARE 0x18
105 #define VGA_CRTC_REGS VGA_CRT_C
106
107 /* VGA CRT controller bit masks */
108 #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */
109 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
110
111 /* VGA attribute controller register indices */
112 #define VGA_ATC_PALETTE0 0x00
113 #define VGA_ATC_PALETTE1 0x01
114 #define VGA_ATC_PALETTE2 0x02
115 #define VGA_ATC_PALETTE3 0x03
116 #define VGA_ATC_PALETTE4 0x04
117 #define VGA_ATC_PALETTE5 0x05
118 #define VGA_ATC_PALETTE6 0x06
119 #define VGA_ATC_PALETTE7 0x07
120 #define VGA_ATC_PALETTE8 0x08
121 #define VGA_ATC_PALETTE9 0x09
122 #define VGA_ATC_PALETTEA 0x0A
123 #define VGA_ATC_PALETTEB 0x0B
124 #define VGA_ATC_PALETTEC 0x0C
125 #define VGA_ATC_PALETTED 0x0D
126 #define VGA_ATC_PALETTEE 0x0E
127 #define VGA_ATC_PALETTEF 0x0F
128 #define VGA_ATC_MODE 0x10
129 #define VGA_ATC_OVERSCAN 0x11
130 #define VGA_ATC_PLANE_ENABLE 0x12
131 #define VGA_ATC_PEL 0x13
132 #define VGA_ATC_COLOR_PAGE 0x14
133
134 #define VGA_AR_ENABLE_DISPLAY 0x20
135
136 /* VGA sequencer register indices */
137 #define VGA_SEQ_RESET 0x00
138 #define VGA_SEQ_CLOCK_MODE 0x01
139 #define VGA_SEQ_PLANE_WRITE 0x02
140 #define VGA_SEQ_CHARACTER_MAP 0x03
141 #define VGA_SEQ_MEMORY_MODE 0x04
142
143 /* VGA sequencer register bit masks */
144 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
145 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
146 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
147 #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */
148 #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */
149 #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
150
151 /* VGA graphics controller register indices */
152 #define VGA_GFX_SR_VALUE 0x00
153 #define VGA_GFX_SR_ENABLE 0x01
154 #define VGA_GFX_COMPARE_VALUE 0x02
155 #define VGA_GFX_DATA_ROTATE 0x03
156 #define VGA_GFX_PLANE_READ 0x04
157 #define VGA_GFX_MODE 0x05
158 #define VGA_GFX_MISC 0x06
159 #define VGA_GFX_COMPARE_MASK 0x07
160 #define VGA_GFX_BIT_MASK 0x08
161
162 /* VGA graphics controller bit masks */
163 #define VGA_GR06_GRAPHICS_MODE 0x01
164
165 /* macro for composing an 8-bit VGA register index and value
166 * into a single 16-bit quantity */
167 #define VGA_OUT16VAL(v, r) (((v) << 8) | (r))
168
169 /* decide whether we should enable the faster 16-bit VGA register writes */
170 #ifdef __LITTLE_ENDIAN
171 #define VGA_OUTW_WRITE
172 #endif
173
174 /* VGA State Save and Restore */
175 #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */
176 #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */
177 #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */
178 #define VGA_SAVE_FONTS 7 /* save/restore all fonts */
179 #define VGA_SAVE_MODE 8 /* save/restore video mode */
180 #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */
181
182 struct vgastate {
183 void __iomem *vgabase; /* mmio base, if supported */
184 unsigned long membase; /* VGA window base, 0 for default - 0xA000 */
185 __u32 memsize; /* VGA window size, 0 for default 64K */
186 __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */
187 __u32 depth; /* current fb depth, not important */
188 __u32 num_attr; /* number of att registers, 0 for default */
189 __u32 num_crtc; /* number of crt registers, 0 for default */
190 __u32 num_gfx; /* number of gfx registers, 0 for default */
191 __u32 num_seq; /* number of seq registers, 0 for default */
192 void *vidstate;
193 };
194
195 extern int save_vga(struct vgastate *state);
196 extern int restore_vga(struct vgastate *state);
197
198 /*
199 * generic VGA port read/write
200 */
201
vga_io_r(unsigned short port)202 static inline unsigned char vga_io_r (unsigned short port)
203 {
204 return inb_p(port);
205 }
206
vga_io_w(unsigned short port,unsigned char val)207 static inline void vga_io_w (unsigned short port, unsigned char val)
208 {
209 outb_p(val, port);
210 }
211
vga_io_w_fast(unsigned short port,unsigned char reg,unsigned char val)212 static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
213 unsigned char val)
214 {
215 outw(VGA_OUT16VAL (val, reg), port);
216 }
217
vga_mm_r(void __iomem * regbase,unsigned short port)218 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port)
219 {
220 return readb (regbase + port);
221 }
222
vga_mm_w(void __iomem * regbase,unsigned short port,unsigned char val)223 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val)
224 {
225 writeb (val, regbase + port);
226 }
227
vga_mm_w_fast(void __iomem * regbase,unsigned short port,unsigned char reg,unsigned char val)228 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port,
229 unsigned char reg, unsigned char val)
230 {
231 writew (VGA_OUT16VAL (val, reg), regbase + port);
232 }
233
vga_r(void __iomem * regbase,unsigned short port)234 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port)
235 {
236 if (regbase)
237 return vga_mm_r (regbase, port);
238 else
239 return vga_io_r (port);
240 }
241
vga_w(void __iomem * regbase,unsigned short port,unsigned char val)242 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val)
243 {
244 if (regbase)
245 vga_mm_w (regbase, port, val);
246 else
247 vga_io_w (port, val);
248 }
249
250
vga_w_fast(void __iomem * regbase,unsigned short port,unsigned char reg,unsigned char val)251 static inline void vga_w_fast (void __iomem *regbase, unsigned short port,
252 unsigned char reg, unsigned char val)
253 {
254 if (regbase)
255 vga_mm_w_fast (regbase, port, reg, val);
256 else
257 vga_io_w_fast (port, reg, val);
258 }
259
260
261 /*
262 * VGA CRTC register read/write
263 */
264
vga_rcrt(void __iomem * regbase,unsigned char reg)265 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg)
266 {
267 vga_w (regbase, VGA_CRT_IC, reg);
268 return vga_r (regbase, VGA_CRT_DC);
269 }
270
vga_wcrt(void __iomem * regbase,unsigned char reg,unsigned char val)271 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
272 {
273 #ifdef VGA_OUTW_WRITE
274 vga_w_fast (regbase, VGA_CRT_IC, reg, val);
275 #else
276 vga_w (regbase, VGA_CRT_IC, reg);
277 vga_w (regbase, VGA_CRT_DC, val);
278 #endif /* VGA_OUTW_WRITE */
279 }
280
vga_io_rcrt(unsigned char reg)281 static inline unsigned char vga_io_rcrt (unsigned char reg)
282 {
283 vga_io_w (VGA_CRT_IC, reg);
284 return vga_io_r (VGA_CRT_DC);
285 }
286
vga_io_wcrt(unsigned char reg,unsigned char val)287 static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
288 {
289 #ifdef VGA_OUTW_WRITE
290 vga_io_w_fast (VGA_CRT_IC, reg, val);
291 #else
292 vga_io_w (VGA_CRT_IC, reg);
293 vga_io_w (VGA_CRT_DC, val);
294 #endif /* VGA_OUTW_WRITE */
295 }
296
vga_mm_rcrt(void __iomem * regbase,unsigned char reg)297 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg)
298 {
299 vga_mm_w (regbase, VGA_CRT_IC, reg);
300 return vga_mm_r (regbase, VGA_CRT_DC);
301 }
302
vga_mm_wcrt(void __iomem * regbase,unsigned char reg,unsigned char val)303 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
304 {
305 #ifdef VGA_OUTW_WRITE
306 vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
307 #else
308 vga_mm_w (regbase, VGA_CRT_IC, reg);
309 vga_mm_w (regbase, VGA_CRT_DC, val);
310 #endif /* VGA_OUTW_WRITE */
311 }
312
313
314 /*
315 * VGA sequencer register read/write
316 */
317
vga_rseq(void __iomem * regbase,unsigned char reg)318 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg)
319 {
320 vga_w (regbase, VGA_SEQ_I, reg);
321 return vga_r (regbase, VGA_SEQ_D);
322 }
323
vga_wseq(void __iomem * regbase,unsigned char reg,unsigned char val)324 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
325 {
326 #ifdef VGA_OUTW_WRITE
327 vga_w_fast (regbase, VGA_SEQ_I, reg, val);
328 #else
329 vga_w (regbase, VGA_SEQ_I, reg);
330 vga_w (regbase, VGA_SEQ_D, val);
331 #endif /* VGA_OUTW_WRITE */
332 }
333
vga_io_rseq(unsigned char reg)334 static inline unsigned char vga_io_rseq (unsigned char reg)
335 {
336 vga_io_w (VGA_SEQ_I, reg);
337 return vga_io_r (VGA_SEQ_D);
338 }
339
vga_io_wseq(unsigned char reg,unsigned char val)340 static inline void vga_io_wseq (unsigned char reg, unsigned char val)
341 {
342 #ifdef VGA_OUTW_WRITE
343 vga_io_w_fast (VGA_SEQ_I, reg, val);
344 #else
345 vga_io_w (VGA_SEQ_I, reg);
346 vga_io_w (VGA_SEQ_D, val);
347 #endif /* VGA_OUTW_WRITE */
348 }
349
vga_mm_rseq(void __iomem * regbase,unsigned char reg)350 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg)
351 {
352 vga_mm_w (regbase, VGA_SEQ_I, reg);
353 return vga_mm_r (regbase, VGA_SEQ_D);
354 }
355
vga_mm_wseq(void __iomem * regbase,unsigned char reg,unsigned char val)356 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
357 {
358 #ifdef VGA_OUTW_WRITE
359 vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
360 #else
361 vga_mm_w (regbase, VGA_SEQ_I, reg);
362 vga_mm_w (regbase, VGA_SEQ_D, val);
363 #endif /* VGA_OUTW_WRITE */
364 }
365
366 /*
367 * VGA graphics controller register read/write
368 */
369
vga_rgfx(void __iomem * regbase,unsigned char reg)370 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg)
371 {
372 vga_w (regbase, VGA_GFX_I, reg);
373 return vga_r (regbase, VGA_GFX_D);
374 }
375
vga_wgfx(void __iomem * regbase,unsigned char reg,unsigned char val)376 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
377 {
378 #ifdef VGA_OUTW_WRITE
379 vga_w_fast (regbase, VGA_GFX_I, reg, val);
380 #else
381 vga_w (regbase, VGA_GFX_I, reg);
382 vga_w (regbase, VGA_GFX_D, val);
383 #endif /* VGA_OUTW_WRITE */
384 }
385
vga_io_rgfx(unsigned char reg)386 static inline unsigned char vga_io_rgfx (unsigned char reg)
387 {
388 vga_io_w (VGA_GFX_I, reg);
389 return vga_io_r (VGA_GFX_D);
390 }
391
vga_io_wgfx(unsigned char reg,unsigned char val)392 static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
393 {
394 #ifdef VGA_OUTW_WRITE
395 vga_io_w_fast (VGA_GFX_I, reg, val);
396 #else
397 vga_io_w (VGA_GFX_I, reg);
398 vga_io_w (VGA_GFX_D, val);
399 #endif /* VGA_OUTW_WRITE */
400 }
401
vga_mm_rgfx(void __iomem * regbase,unsigned char reg)402 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg)
403 {
404 vga_mm_w (regbase, VGA_GFX_I, reg);
405 return vga_mm_r (regbase, VGA_GFX_D);
406 }
407
vga_mm_wgfx(void __iomem * regbase,unsigned char reg,unsigned char val)408 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
409 {
410 #ifdef VGA_OUTW_WRITE
411 vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
412 #else
413 vga_mm_w (regbase, VGA_GFX_I, reg);
414 vga_mm_w (regbase, VGA_GFX_D, val);
415 #endif /* VGA_OUTW_WRITE */
416 }
417
418
419 /*
420 * VGA attribute controller register read/write
421 */
422
vga_rattr(void __iomem * regbase,unsigned char reg)423 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg)
424 {
425 vga_w (regbase, VGA_ATT_IW, reg);
426 return vga_r (regbase, VGA_ATT_R);
427 }
428
vga_wattr(void __iomem * regbase,unsigned char reg,unsigned char val)429 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
430 {
431 vga_w (regbase, VGA_ATT_IW, reg);
432 vga_w (regbase, VGA_ATT_W, val);
433 }
434
vga_io_rattr(unsigned char reg)435 static inline unsigned char vga_io_rattr (unsigned char reg)
436 {
437 vga_io_w (VGA_ATT_IW, reg);
438 return vga_io_r (VGA_ATT_R);
439 }
440
vga_io_wattr(unsigned char reg,unsigned char val)441 static inline void vga_io_wattr (unsigned char reg, unsigned char val)
442 {
443 vga_io_w (VGA_ATT_IW, reg);
444 vga_io_w (VGA_ATT_W, val);
445 }
446
vga_mm_rattr(void __iomem * regbase,unsigned char reg)447 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg)
448 {
449 vga_mm_w (regbase, VGA_ATT_IW, reg);
450 return vga_mm_r (regbase, VGA_ATT_R);
451 }
452
vga_mm_wattr(void __iomem * regbase,unsigned char reg,unsigned char val)453 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
454 {
455 vga_mm_w (regbase, VGA_ATT_IW, reg);
456 vga_mm_w (regbase, VGA_ATT_W, val);
457 }
458
459 #endif /* __linux_video_vga_h__ */
460