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1 /*
2  * atmel_ssc_dai.c  --  ALSA SoC ATMEL SSC Audio Layer Platform driver
3  *
4  * Copyright (C) 2005 SAN People
5  * Copyright (C) 2008 Atmel
6  *
7  * Author: Sedji Gaouaou <sedji.gaouaou@atmel.com>
8  *         ATMEL CORP.
9  *
10  * Based on at91-ssc.c by
11  * Frank Mandarino <fmandarino@endrelia.com>
12  * Based on pxa2xx Platform drivers by
13  * Liam Girdwood <lrg@slimlogic.co.uk>
14  *
15  * This program is free software; you can redistribute it and/or modify
16  * it under the terms of the GNU General Public License as published by
17  * the Free Software Foundation; either version 2 of the License, or
18  * (at your option) any later version.
19  *
20  * This program is distributed in the hope that it will be useful,
21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
23  * GNU General Public License for more details.
24  *
25  * You should have received a copy of the GNU General Public License
26  * along with this program; if not, write to the Free Software
27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
28  */
29 
30 #include <linux/init.h>
31 #include <linux/module.h>
32 #include <linux/interrupt.h>
33 #include <linux/device.h>
34 #include <linux/delay.h>
35 #include <linux/clk.h>
36 #include <linux/atmel_pdc.h>
37 
38 #include <linux/atmel-ssc.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
44 
45 #include "atmel-pcm.h"
46 #include "atmel_ssc_dai.h"
47 
48 
49 #define NUM_SSC_DEVICES		3
50 
51 /*
52  * SSC PDC registers required by the PCM DMA engine.
53  */
54 static struct atmel_pdc_regs pdc_tx_reg = {
55 	.xpr		= ATMEL_PDC_TPR,
56 	.xcr		= ATMEL_PDC_TCR,
57 	.xnpr		= ATMEL_PDC_TNPR,
58 	.xncr		= ATMEL_PDC_TNCR,
59 };
60 
61 static struct atmel_pdc_regs pdc_rx_reg = {
62 	.xpr		= ATMEL_PDC_RPR,
63 	.xcr		= ATMEL_PDC_RCR,
64 	.xnpr		= ATMEL_PDC_RNPR,
65 	.xncr		= ATMEL_PDC_RNCR,
66 };
67 
68 /*
69  * SSC & PDC status bits for transmit and receive.
70  */
71 static struct atmel_ssc_mask ssc_tx_mask = {
72 	.ssc_enable	= SSC_BIT(CR_TXEN),
73 	.ssc_disable	= SSC_BIT(CR_TXDIS),
74 	.ssc_endx	= SSC_BIT(SR_ENDTX),
75 	.ssc_endbuf	= SSC_BIT(SR_TXBUFE),
76 	.pdc_enable	= ATMEL_PDC_TXTEN,
77 	.pdc_disable	= ATMEL_PDC_TXTDIS,
78 };
79 
80 static struct atmel_ssc_mask ssc_rx_mask = {
81 	.ssc_enable	= SSC_BIT(CR_RXEN),
82 	.ssc_disable	= SSC_BIT(CR_RXDIS),
83 	.ssc_endx	= SSC_BIT(SR_ENDRX),
84 	.ssc_endbuf	= SSC_BIT(SR_RXBUFF),
85 	.pdc_enable	= ATMEL_PDC_RXTEN,
86 	.pdc_disable	= ATMEL_PDC_RXTDIS,
87 };
88 
89 
90 /*
91  * DMA parameters.
92  */
93 static struct atmel_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
94 	{{
95 	.name		= "SSC0 PCM out",
96 	.pdc		= &pdc_tx_reg,
97 	.mask		= &ssc_tx_mask,
98 	},
99 	{
100 	.name		= "SSC0 PCM in",
101 	.pdc		= &pdc_rx_reg,
102 	.mask		= &ssc_rx_mask,
103 	} },
104 	{{
105 	.name		= "SSC1 PCM out",
106 	.pdc		= &pdc_tx_reg,
107 	.mask		= &ssc_tx_mask,
108 	},
109 	{
110 	.name		= "SSC1 PCM in",
111 	.pdc		= &pdc_rx_reg,
112 	.mask		= &ssc_rx_mask,
113 	} },
114 	{{
115 	.name		= "SSC2 PCM out",
116 	.pdc		= &pdc_tx_reg,
117 	.mask		= &ssc_tx_mask,
118 	},
119 	{
120 	.name		= "SSC2 PCM in",
121 	.pdc		= &pdc_rx_reg,
122 	.mask		= &ssc_rx_mask,
123 	} },
124 };
125 
126 
127 static struct atmel_ssc_info ssc_info[NUM_SSC_DEVICES] = {
128 	{
129 	.name		= "ssc0",
130 	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[0].lock),
131 	.dir_mask	= SSC_DIR_MASK_UNUSED,
132 	.initialized	= 0,
133 	},
134 	{
135 	.name		= "ssc1",
136 	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[1].lock),
137 	.dir_mask	= SSC_DIR_MASK_UNUSED,
138 	.initialized	= 0,
139 	},
140 	{
141 	.name		= "ssc2",
142 	.lock		= __SPIN_LOCK_UNLOCKED(ssc_info[2].lock),
143 	.dir_mask	= SSC_DIR_MASK_UNUSED,
144 	.initialized	= 0,
145 	},
146 };
147 
148 
149 /*
150  * SSC interrupt handler.  Passes PDC interrupts to the DMA
151  * interrupt handler in the PCM driver.
152  */
atmel_ssc_interrupt(int irq,void * dev_id)153 static irqreturn_t atmel_ssc_interrupt(int irq, void *dev_id)
154 {
155 	struct atmel_ssc_info *ssc_p = dev_id;
156 	struct atmel_pcm_dma_params *dma_params;
157 	u32 ssc_sr;
158 	u32 ssc_substream_mask;
159 	int i;
160 
161 	ssc_sr = (unsigned long)ssc_readl(ssc_p->ssc->regs, SR)
162 			& (unsigned long)ssc_readl(ssc_p->ssc->regs, IMR);
163 
164 	/*
165 	 * Loop through the substreams attached to this SSC.  If
166 	 * a DMA-related interrupt occurred on that substream, call
167 	 * the DMA interrupt handler function, if one has been
168 	 * registered in the dma_params structure by the PCM driver.
169 	 */
170 	for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
171 		dma_params = ssc_p->dma_params[i];
172 
173 		if ((dma_params != NULL) &&
174 			(dma_params->dma_intr_handler != NULL)) {
175 			ssc_substream_mask = (dma_params->mask->ssc_endx |
176 					dma_params->mask->ssc_endbuf);
177 			if (ssc_sr & ssc_substream_mask) {
178 				dma_params->dma_intr_handler(ssc_sr,
179 						dma_params->
180 						substream);
181 			}
182 		}
183 	}
184 
185 	return IRQ_HANDLED;
186 }
187 
188 
189 /*-------------------------------------------------------------------------*\
190  * DAI functions
191 \*-------------------------------------------------------------------------*/
192 /*
193  * Startup.  Only that one substream allowed in each direction.
194  */
atmel_ssc_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)195 static int atmel_ssc_startup(struct snd_pcm_substream *substream,
196 			     struct snd_soc_dai *dai)
197 {
198 	struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
199 	int dir_mask;
200 
201 	pr_debug("atmel_ssc_startup: SSC_SR=0x%u\n",
202 		ssc_readl(ssc_p->ssc->regs, SR));
203 
204 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
205 		dir_mask = SSC_DIR_MASK_PLAYBACK;
206 	else
207 		dir_mask = SSC_DIR_MASK_CAPTURE;
208 
209 	spin_lock_irq(&ssc_p->lock);
210 	if (ssc_p->dir_mask & dir_mask) {
211 		spin_unlock_irq(&ssc_p->lock);
212 		return -EBUSY;
213 	}
214 	ssc_p->dir_mask |= dir_mask;
215 	spin_unlock_irq(&ssc_p->lock);
216 
217 	return 0;
218 }
219 
220 /*
221  * Shutdown.  Clear DMA parameters and shutdown the SSC if there
222  * are no other substreams open.
223  */
atmel_ssc_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)224 static void atmel_ssc_shutdown(struct snd_pcm_substream *substream,
225 			       struct snd_soc_dai *dai)
226 {
227 	struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
228 	struct atmel_pcm_dma_params *dma_params;
229 	int dir, dir_mask;
230 
231 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
232 		dir = 0;
233 	else
234 		dir = 1;
235 
236 	dma_params = ssc_p->dma_params[dir];
237 
238 	if (dma_params != NULL) {
239 		ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_disable);
240 		pr_debug("atmel_ssc_shutdown: %s disabled SSC_SR=0x%08x\n",
241 			(dir ? "receive" : "transmit"),
242 			ssc_readl(ssc_p->ssc->regs, SR));
243 
244 		dma_params->ssc = NULL;
245 		dma_params->substream = NULL;
246 		ssc_p->dma_params[dir] = NULL;
247 	}
248 
249 	dir_mask = 1 << dir;
250 
251 	spin_lock_irq(&ssc_p->lock);
252 	ssc_p->dir_mask &= ~dir_mask;
253 	if (!ssc_p->dir_mask) {
254 		if (ssc_p->initialized) {
255 			/* Shutdown the SSC clock. */
256 			pr_debug("atmel_ssc_dau: Stopping clock\n");
257 			clk_disable(ssc_p->ssc->clk);
258 
259 			free_irq(ssc_p->ssc->irq, ssc_p);
260 			ssc_p->initialized = 0;
261 		}
262 
263 		/* Reset the SSC */
264 		ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
265 		/* Clear the SSC dividers */
266 		ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
267 	}
268 	spin_unlock_irq(&ssc_p->lock);
269 }
270 
271 
272 /*
273  * Record the DAI format for use in hw_params().
274  */
atmel_ssc_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)275 static int atmel_ssc_set_dai_fmt(struct snd_soc_dai *cpu_dai,
276 		unsigned int fmt)
277 {
278 	struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
279 
280 	ssc_p->daifmt = fmt;
281 	return 0;
282 }
283 
284 /*
285  * Record SSC clock dividers for use in hw_params().
286  */
atmel_ssc_set_dai_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)287 static int atmel_ssc_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
288 	int div_id, int div)
289 {
290 	struct atmel_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
291 
292 	switch (div_id) {
293 	case ATMEL_SSC_CMR_DIV:
294 		/*
295 		 * The same master clock divider is used for both
296 		 * transmit and receive, so if a value has already
297 		 * been set, it must match this value.
298 		 */
299 		if (ssc_p->cmr_div == 0)
300 			ssc_p->cmr_div = div;
301 		else
302 			if (div != ssc_p->cmr_div)
303 				return -EBUSY;
304 		break;
305 
306 	case ATMEL_SSC_TCMR_PERIOD:
307 		ssc_p->tcmr_period = div;
308 		break;
309 
310 	case ATMEL_SSC_RCMR_PERIOD:
311 		ssc_p->rcmr_period = div;
312 		break;
313 
314 	default:
315 		return -EINVAL;
316 	}
317 
318 	return 0;
319 }
320 
321 /*
322  * Configure the SSC.
323  */
atmel_ssc_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)324 static int atmel_ssc_hw_params(struct snd_pcm_substream *substream,
325 	struct snd_pcm_hw_params *params,
326 	struct snd_soc_dai *dai)
327 {
328 	struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
329 	int id = dai->id;
330 	struct atmel_ssc_info *ssc_p = &ssc_info[id];
331 	struct atmel_pcm_dma_params *dma_params;
332 	int dir, channels, bits;
333 	u32 tfmr, rfmr, tcmr, rcmr;
334 	int start_event;
335 	int ret;
336 
337 	/*
338 	 * Currently, there is only one set of dma params for
339 	 * each direction.  If more are added, this code will
340 	 * have to be changed to select the proper set.
341 	 */
342 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
343 		dir = 0;
344 	else
345 		dir = 1;
346 
347 	dma_params = &ssc_dma_params[id][dir];
348 	dma_params->ssc = ssc_p->ssc;
349 	dma_params->substream = substream;
350 
351 	ssc_p->dma_params[dir] = dma_params;
352 
353 	/*
354 	 * The snd_soc_pcm_stream->dma_data field is only used to communicate
355 	 * the appropriate DMA parameters to the pcm driver hw_params()
356 	 * function.  It should not be used for other purposes
357 	 * as it is common to all substreams.
358 	 */
359 	snd_soc_dai_set_dma_data(rtd->cpu_dai, substream, dma_params);
360 
361 	channels = params_channels(params);
362 
363 	/*
364 	 * Determine sample size in bits and the PDC increment.
365 	 */
366 	switch (params_format(params)) {
367 	case SNDRV_PCM_FORMAT_S8:
368 		bits = 8;
369 		dma_params->pdc_xfer_size = 1;
370 		break;
371 	case SNDRV_PCM_FORMAT_S16_LE:
372 		bits = 16;
373 		dma_params->pdc_xfer_size = 2;
374 		break;
375 	case SNDRV_PCM_FORMAT_S24_LE:
376 		bits = 24;
377 		dma_params->pdc_xfer_size = 4;
378 		break;
379 	case SNDRV_PCM_FORMAT_S32_LE:
380 		bits = 32;
381 		dma_params->pdc_xfer_size = 4;
382 		break;
383 	default:
384 		printk(KERN_WARNING "atmel_ssc_dai: unsupported PCM format");
385 		return -EINVAL;
386 	}
387 
388 	/*
389 	 * The SSC only supports up to 16-bit samples in I2S format, due
390 	 * to the size of the Frame Mode Register FSLEN field.
391 	 */
392 	if ((ssc_p->daifmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S
393 		&& bits > 16) {
394 		printk(KERN_WARNING
395 				"atmel_ssc_dai: sample size %d "
396 				"is too large for I2S\n", bits);
397 		return -EINVAL;
398 	}
399 
400 	/*
401 	 * Compute SSC register settings.
402 	 */
403 	switch (ssc_p->daifmt
404 		& (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_MASTER_MASK)) {
405 
406 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBS_CFS:
407 		/*
408 		 * I2S format, SSC provides BCLK and LRC clocks.
409 		 *
410 		 * The SSC transmit and receive clocks are generated
411 		 * from the MCK divider, and the BCLK signal
412 		 * is output on the SSC TK line.
413 		 */
414 		rcmr =	  SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
415 			| SSC_BF(RCMR_STTDLY, START_DELAY)
416 			| SSC_BF(RCMR_START, SSC_START_FALLING_RF)
417 			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
418 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
419 			| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
420 
421 		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
422 			| SSC_BF(RFMR_FSOS, SSC_FSOS_NEGATIVE)
423 			| SSC_BF(RFMR_FSLEN, (bits - 1))
424 			| SSC_BF(RFMR_DATNB, (channels - 1))
425 			| SSC_BIT(RFMR_MSBF)
426 			| SSC_BF(RFMR_LOOP, 0)
427 			| SSC_BF(RFMR_DATLEN, (bits - 1));
428 
429 		tcmr =	  SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
430 			| SSC_BF(TCMR_STTDLY, START_DELAY)
431 			| SSC_BF(TCMR_START, SSC_START_FALLING_RF)
432 			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
433 			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
434 			| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
435 
436 		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
437 			| SSC_BF(TFMR_FSDEN, 0)
438 			| SSC_BF(TFMR_FSOS, SSC_FSOS_NEGATIVE)
439 			| SSC_BF(TFMR_FSLEN, (bits - 1))
440 			| SSC_BF(TFMR_DATNB, (channels - 1))
441 			| SSC_BIT(TFMR_MSBF)
442 			| SSC_BF(TFMR_DATDEF, 0)
443 			| SSC_BF(TFMR_DATLEN, (bits - 1));
444 		break;
445 
446 	case SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_CBM_CFM:
447 		/*
448 		 * I2S format, CODEC supplies BCLK and LRC clocks.
449 		 *
450 		 * The SSC transmit clock is obtained from the BCLK signal on
451 		 * on the TK line, and the SSC receive clock is
452 		 * generated from the transmit clock.
453 		 *
454 		 *  For single channel data, one sample is transferred
455 		 * on the falling edge of the LRC clock.
456 		 * For two channel data, one sample is
457 		 * transferred on both edges of the LRC clock.
458 		 */
459 		start_event = ((channels == 1)
460 				? SSC_START_FALLING_RF
461 				: SSC_START_EDGE_RF);
462 
463 		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
464 			| SSC_BF(RCMR_STTDLY, START_DELAY)
465 			| SSC_BF(RCMR_START, start_event)
466 			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
467 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
468 			| SSC_BF(RCMR_CKS, SSC_CKS_CLOCK);
469 
470 		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
471 			| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
472 			| SSC_BF(RFMR_FSLEN, 0)
473 			| SSC_BF(RFMR_DATNB, 0)
474 			| SSC_BIT(RFMR_MSBF)
475 			| SSC_BF(RFMR_LOOP, 0)
476 			| SSC_BF(RFMR_DATLEN, (bits - 1));
477 
478 		tcmr =	  SSC_BF(TCMR_PERIOD, 0)
479 			| SSC_BF(TCMR_STTDLY, START_DELAY)
480 			| SSC_BF(TCMR_START, start_event)
481 			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
482 			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
483 			| SSC_BF(TCMR_CKS, SSC_CKS_PIN);
484 
485 		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
486 			| SSC_BF(TFMR_FSDEN, 0)
487 			| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
488 			| SSC_BF(TFMR_FSLEN, 0)
489 			| SSC_BF(TFMR_DATNB, 0)
490 			| SSC_BIT(TFMR_MSBF)
491 			| SSC_BF(TFMR_DATDEF, 0)
492 			| SSC_BF(TFMR_DATLEN, (bits - 1));
493 		break;
494 
495 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBS_CFS:
496 		/*
497 		 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks.
498 		 *
499 		 * The SSC transmit and receive clocks are generated from the
500 		 * MCK divider, and the BCLK signal is output
501 		 * on the SSC TK line.
502 		 */
503 		rcmr =	  SSC_BF(RCMR_PERIOD, ssc_p->rcmr_period)
504 			| SSC_BF(RCMR_STTDLY, 1)
505 			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
506 			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
507 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
508 			| SSC_BF(RCMR_CKS, SSC_CKS_DIV);
509 
510 		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
511 			| SSC_BF(RFMR_FSOS, SSC_FSOS_POSITIVE)
512 			| SSC_BF(RFMR_FSLEN, 0)
513 			| SSC_BF(RFMR_DATNB, (channels - 1))
514 			| SSC_BIT(RFMR_MSBF)
515 			| SSC_BF(RFMR_LOOP, 0)
516 			| SSC_BF(RFMR_DATLEN, (bits - 1));
517 
518 		tcmr =	  SSC_BF(TCMR_PERIOD, ssc_p->tcmr_period)
519 			| SSC_BF(TCMR_STTDLY, 1)
520 			| SSC_BF(TCMR_START, SSC_START_RISING_RF)
521 			| SSC_BF(TCMR_CKI, SSC_CKI_RISING)
522 			| SSC_BF(TCMR_CKO, SSC_CKO_CONTINUOUS)
523 			| SSC_BF(TCMR_CKS, SSC_CKS_DIV);
524 
525 		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
526 			| SSC_BF(TFMR_FSDEN, 0)
527 			| SSC_BF(TFMR_FSOS, SSC_FSOS_POSITIVE)
528 			| SSC_BF(TFMR_FSLEN, 0)
529 			| SSC_BF(TFMR_DATNB, (channels - 1))
530 			| SSC_BIT(TFMR_MSBF)
531 			| SSC_BF(TFMR_DATDEF, 0)
532 			| SSC_BF(TFMR_DATLEN, (bits - 1));
533 		break;
534 
535 	case SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_CBM_CFM:
536 		/*
537 		 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks.
538 		 *
539 		 * The SSC transmit clock is obtained from the BCLK signal on
540 		 * on the TK line, and the SSC receive clock is
541 		 * generated from the transmit clock.
542 		 *
543 		 * Data is transferred on first BCLK after LRC pulse rising
544 		 * edge.If stereo, the right channel data is contiguous with
545 		 * the left channel data.
546 		 */
547 		rcmr =	  SSC_BF(RCMR_PERIOD, 0)
548 			| SSC_BF(RCMR_STTDLY, START_DELAY)
549 			| SSC_BF(RCMR_START, SSC_START_RISING_RF)
550 			| SSC_BF(RCMR_CKI, SSC_CKI_RISING)
551 			| SSC_BF(RCMR_CKO, SSC_CKO_NONE)
552 			| SSC_BF(RCMR_CKS, SSC_CKS_PIN);
553 
554 		rfmr =	  SSC_BF(RFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
555 			| SSC_BF(RFMR_FSOS, SSC_FSOS_NONE)
556 			| SSC_BF(RFMR_FSLEN, 0)
557 			| SSC_BF(RFMR_DATNB, (channels - 1))
558 			| SSC_BIT(RFMR_MSBF)
559 			| SSC_BF(RFMR_LOOP, 0)
560 			| SSC_BF(RFMR_DATLEN, (bits - 1));
561 
562 		tcmr =	  SSC_BF(TCMR_PERIOD, 0)
563 			| SSC_BF(TCMR_STTDLY, START_DELAY)
564 			| SSC_BF(TCMR_START, SSC_START_RISING_RF)
565 			| SSC_BF(TCMR_CKI, SSC_CKI_FALLING)
566 			| SSC_BF(TCMR_CKO, SSC_CKO_NONE)
567 			| SSC_BF(TCMR_CKS, SSC_CKS_PIN);
568 
569 		tfmr =	  SSC_BF(TFMR_FSEDGE, SSC_FSEDGE_POSITIVE)
570 			| SSC_BF(TFMR_FSDEN, 0)
571 			| SSC_BF(TFMR_FSOS, SSC_FSOS_NONE)
572 			| SSC_BF(TFMR_FSLEN, 0)
573 			| SSC_BF(TFMR_DATNB, (channels - 1))
574 			| SSC_BIT(TFMR_MSBF)
575 			| SSC_BF(TFMR_DATDEF, 0)
576 			| SSC_BF(TFMR_DATLEN, (bits - 1));
577 		break;
578 
579 	default:
580 		printk(KERN_WARNING "atmel_ssc_dai: unsupported DAI format 0x%x\n",
581 			ssc_p->daifmt);
582 		return -EINVAL;
583 	}
584 	pr_debug("atmel_ssc_hw_params: "
585 			"RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n",
586 			rcmr, rfmr, tcmr, tfmr);
587 
588 	if (!ssc_p->initialized) {
589 
590 		/* Enable PMC peripheral clock for this SSC */
591 		pr_debug("atmel_ssc_dai: Starting clock\n");
592 		clk_enable(ssc_p->ssc->clk);
593 
594 		/* Reset the SSC and its PDC registers */
595 		ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_SWRST));
596 
597 		ssc_writel(ssc_p->ssc->regs, PDC_RPR, 0);
598 		ssc_writel(ssc_p->ssc->regs, PDC_RCR, 0);
599 		ssc_writel(ssc_p->ssc->regs, PDC_RNPR, 0);
600 		ssc_writel(ssc_p->ssc->regs, PDC_RNCR, 0);
601 
602 		ssc_writel(ssc_p->ssc->regs, PDC_TPR, 0);
603 		ssc_writel(ssc_p->ssc->regs, PDC_TCR, 0);
604 		ssc_writel(ssc_p->ssc->regs, PDC_TNPR, 0);
605 		ssc_writel(ssc_p->ssc->regs, PDC_TNCR, 0);
606 
607 		ret = request_irq(ssc_p->ssc->irq, atmel_ssc_interrupt, 0,
608 				ssc_p->name, ssc_p);
609 		if (ret < 0) {
610 			printk(KERN_WARNING
611 					"atmel_ssc_dai: request_irq failure\n");
612 			pr_debug("Atmel_ssc_dai: Stoping clock\n");
613 			clk_disable(ssc_p->ssc->clk);
614 			return ret;
615 		}
616 
617 		ssc_p->initialized = 1;
618 	}
619 
620 	/* set SSC clock mode register */
621 	ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->cmr_div);
622 
623 	/* set receive clock mode and format */
624 	ssc_writel(ssc_p->ssc->regs, RCMR, rcmr);
625 	ssc_writel(ssc_p->ssc->regs, RFMR, rfmr);
626 
627 	/* set transmit clock mode and format */
628 	ssc_writel(ssc_p->ssc->regs, TCMR, tcmr);
629 	ssc_writel(ssc_p->ssc->regs, TFMR, tfmr);
630 
631 	pr_debug("atmel_ssc_dai,hw_params: SSC initialized\n");
632 	return 0;
633 }
634 
635 
atmel_ssc_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)636 static int atmel_ssc_prepare(struct snd_pcm_substream *substream,
637 			     struct snd_soc_dai *dai)
638 {
639 	struct atmel_ssc_info *ssc_p = &ssc_info[dai->id];
640 	struct atmel_pcm_dma_params *dma_params;
641 	int dir;
642 
643 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
644 		dir = 0;
645 	else
646 		dir = 1;
647 
648 	dma_params = ssc_p->dma_params[dir];
649 
650 	ssc_writel(ssc_p->ssc->regs, CR, dma_params->mask->ssc_enable);
651 
652 	pr_debug("%s enabled SSC_SR=0x%08x\n",
653 			dir ? "receive" : "transmit",
654 			ssc_readl(ssc_p->ssc->regs, SR));
655 	return 0;
656 }
657 
658 
659 #ifdef CONFIG_PM
atmel_ssc_suspend(struct snd_soc_dai * cpu_dai)660 static int atmel_ssc_suspend(struct snd_soc_dai *cpu_dai)
661 {
662 	struct atmel_ssc_info *ssc_p;
663 
664 	if (!cpu_dai->active)
665 		return 0;
666 
667 	ssc_p = &ssc_info[cpu_dai->id];
668 
669 	/* Save the status register before disabling transmit and receive */
670 	ssc_p->ssc_state.ssc_sr = ssc_readl(ssc_p->ssc->regs, SR);
671 	ssc_writel(ssc_p->ssc->regs, CR, SSC_BIT(CR_TXDIS) | SSC_BIT(CR_RXDIS));
672 
673 	/* Save the current interrupt mask, then disable unmasked interrupts */
674 	ssc_p->ssc_state.ssc_imr = ssc_readl(ssc_p->ssc->regs, IMR);
675 	ssc_writel(ssc_p->ssc->regs, IDR, ssc_p->ssc_state.ssc_imr);
676 
677 	ssc_p->ssc_state.ssc_cmr = ssc_readl(ssc_p->ssc->regs, CMR);
678 	ssc_p->ssc_state.ssc_rcmr = ssc_readl(ssc_p->ssc->regs, RCMR);
679 	ssc_p->ssc_state.ssc_rfmr = ssc_readl(ssc_p->ssc->regs, RFMR);
680 	ssc_p->ssc_state.ssc_tcmr = ssc_readl(ssc_p->ssc->regs, TCMR);
681 	ssc_p->ssc_state.ssc_tfmr = ssc_readl(ssc_p->ssc->regs, TFMR);
682 
683 	return 0;
684 }
685 
686 
687 
atmel_ssc_resume(struct snd_soc_dai * cpu_dai)688 static int atmel_ssc_resume(struct snd_soc_dai *cpu_dai)
689 {
690 	struct atmel_ssc_info *ssc_p;
691 	u32 cr;
692 
693 	if (!cpu_dai->active)
694 		return 0;
695 
696 	ssc_p = &ssc_info[cpu_dai->id];
697 
698 	/* restore SSC register settings */
699 	ssc_writel(ssc_p->ssc->regs, TFMR, ssc_p->ssc_state.ssc_tfmr);
700 	ssc_writel(ssc_p->ssc->regs, TCMR, ssc_p->ssc_state.ssc_tcmr);
701 	ssc_writel(ssc_p->ssc->regs, RFMR, ssc_p->ssc_state.ssc_rfmr);
702 	ssc_writel(ssc_p->ssc->regs, RCMR, ssc_p->ssc_state.ssc_rcmr);
703 	ssc_writel(ssc_p->ssc->regs, CMR, ssc_p->ssc_state.ssc_cmr);
704 
705 	/* re-enable interrupts */
706 	ssc_writel(ssc_p->ssc->regs, IER, ssc_p->ssc_state.ssc_imr);
707 
708 	/* Re-enable receive and transmit as appropriate */
709 	cr = 0;
710 	cr |=
711 	    (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_RXEN)) ? SSC_BIT(CR_RXEN) : 0;
712 	cr |=
713 	    (ssc_p->ssc_state.ssc_sr & SSC_BIT(SR_TXEN)) ? SSC_BIT(CR_TXEN) : 0;
714 	ssc_writel(ssc_p->ssc->regs, CR, cr);
715 
716 	return 0;
717 }
718 #else /* CONFIG_PM */
719 #  define atmel_ssc_suspend	NULL
720 #  define atmel_ssc_resume	NULL
721 #endif /* CONFIG_PM */
722 
723 #define ATMEL_SSC_RATES (SNDRV_PCM_RATE_8000_96000)
724 
725 #define ATMEL_SSC_FORMATS (SNDRV_PCM_FMTBIT_S8     | SNDRV_PCM_FMTBIT_S16_LE |\
726 			  SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
727 
728 static const struct snd_soc_dai_ops atmel_ssc_dai_ops = {
729 	.startup	= atmel_ssc_startup,
730 	.shutdown	= atmel_ssc_shutdown,
731 	.prepare	= atmel_ssc_prepare,
732 	.hw_params	= atmel_ssc_hw_params,
733 	.set_fmt	= atmel_ssc_set_dai_fmt,
734 	.set_clkdiv	= atmel_ssc_set_dai_clkdiv,
735 };
736 
737 static struct snd_soc_dai_driver atmel_ssc_dai = {
738 		.suspend = atmel_ssc_suspend,
739 		.resume = atmel_ssc_resume,
740 		.playback = {
741 			.channels_min = 1,
742 			.channels_max = 2,
743 			.rates = ATMEL_SSC_RATES,
744 			.formats = ATMEL_SSC_FORMATS,},
745 		.capture = {
746 			.channels_min = 1,
747 			.channels_max = 2,
748 			.rates = ATMEL_SSC_RATES,
749 			.formats = ATMEL_SSC_FORMATS,},
750 		.ops = &atmel_ssc_dai_ops,
751 };
752 
753 static const struct snd_soc_component_driver atmel_ssc_component = {
754 	.name		= "atmel-ssc",
755 };
756 
asoc_ssc_init(struct device * dev)757 static int asoc_ssc_init(struct device *dev)
758 {
759 	struct platform_device *pdev = to_platform_device(dev);
760 	struct ssc_device *ssc = platform_get_drvdata(pdev);
761 	int ret;
762 
763 	ret = snd_soc_register_component(dev, &atmel_ssc_component,
764 					 &atmel_ssc_dai, 1);
765 	if (ret) {
766 		dev_err(dev, "Could not register DAI: %d\n", ret);
767 		goto err;
768 	}
769 
770 	if (ssc->pdata->use_dma)
771 		ret = atmel_pcm_dma_platform_register(dev);
772 	else
773 		ret = atmel_pcm_pdc_platform_register(dev);
774 
775 	if (ret) {
776 		dev_err(dev, "Could not register PCM: %d\n", ret);
777 		goto err_unregister_dai;
778 	};
779 
780 	return 0;
781 
782 err_unregister_dai:
783 	snd_soc_unregister_component(dev);
784 err:
785 	return ret;
786 }
787 
asoc_ssc_exit(struct device * dev)788 static void asoc_ssc_exit(struct device *dev)
789 {
790 	struct platform_device *pdev = to_platform_device(dev);
791 	struct ssc_device *ssc = platform_get_drvdata(pdev);
792 
793 	if (ssc->pdata->use_dma)
794 		atmel_pcm_dma_platform_unregister(dev);
795 	else
796 		atmel_pcm_pdc_platform_unregister(dev);
797 
798 	snd_soc_unregister_component(dev);
799 }
800 
801 /**
802  * atmel_ssc_set_audio - Allocate the specified SSC for audio use.
803  */
atmel_ssc_set_audio(int ssc_id)804 int atmel_ssc_set_audio(int ssc_id)
805 {
806 	struct ssc_device *ssc;
807 	int ret;
808 
809 	/* If we can grab the SSC briefly to parent the DAI device off it */
810 	ssc = ssc_request(ssc_id);
811 	if (IS_ERR(ssc)) {
812 		pr_err("Unable to parent ASoC SSC DAI on SSC: %ld\n",
813 			PTR_ERR(ssc));
814 		return PTR_ERR(ssc);
815 	} else {
816 		ssc_info[ssc_id].ssc = ssc;
817 	}
818 
819 	ret = asoc_ssc_init(&ssc->pdev->dev);
820 
821 	return ret;
822 }
823 EXPORT_SYMBOL_GPL(atmel_ssc_set_audio);
824 
atmel_ssc_put_audio(int ssc_id)825 void atmel_ssc_put_audio(int ssc_id)
826 {
827 	struct ssc_device *ssc = ssc_info[ssc_id].ssc;
828 
829 	asoc_ssc_exit(&ssc->pdev->dev);
830 	ssc_free(ssc);
831 }
832 EXPORT_SYMBOL_GPL(atmel_ssc_put_audio);
833 
834 /* Module information */
835 MODULE_AUTHOR("Sedji Gaouaou, sedji.gaouaou@atmel.com, www.atmel.com");
836 MODULE_DESCRIPTION("ATMEL SSC ASoC Interface");
837 MODULE_LICENSE("GPL");
838