1 /*
2 * ASoC driver for Cirrus Logic EP93xx AC97 controller.
3 *
4 * Copyright (c) 2010 Mika Westerberg
5 *
6 * Based on s3c-ac97 ASoC driver by Jaswinder Singh.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20
21 #include <sound/core.h>
22 #include <sound/ac97_codec.h>
23 #include <sound/soc.h>
24
25 #include <linux/platform_data/dma-ep93xx.h>
26
27 /*
28 * Per channel (1-4) registers.
29 */
30 #define AC97CH(n) (((n) - 1) * 0x20)
31
32 #define AC97DR(n) (AC97CH(n) + 0x0000)
33
34 #define AC97RXCR(n) (AC97CH(n) + 0x0004)
35 #define AC97RXCR_REN BIT(0)
36 #define AC97RXCR_RX3 BIT(3)
37 #define AC97RXCR_RX4 BIT(4)
38 #define AC97RXCR_CM BIT(15)
39
40 #define AC97TXCR(n) (AC97CH(n) + 0x0008)
41 #define AC97TXCR_TEN BIT(0)
42 #define AC97TXCR_TX3 BIT(3)
43 #define AC97TXCR_TX4 BIT(4)
44 #define AC97TXCR_CM BIT(15)
45
46 #define AC97SR(n) (AC97CH(n) + 0x000c)
47 #define AC97SR_TXFE BIT(1)
48 #define AC97SR_TXUE BIT(6)
49
50 #define AC97RISR(n) (AC97CH(n) + 0x0010)
51 #define AC97ISR(n) (AC97CH(n) + 0x0014)
52 #define AC97IE(n) (AC97CH(n) + 0x0018)
53
54 /*
55 * Global AC97 controller registers.
56 */
57 #define AC97S1DATA 0x0080
58 #define AC97S2DATA 0x0084
59 #define AC97S12DATA 0x0088
60
61 #define AC97RGIS 0x008c
62 #define AC97GIS 0x0090
63 #define AC97IM 0x0094
64 /*
65 * Common bits for RGIS, GIS and IM registers.
66 */
67 #define AC97_SLOT2RXVALID BIT(1)
68 #define AC97_CODECREADY BIT(5)
69 #define AC97_SLOT2TXCOMPLETE BIT(6)
70
71 #define AC97EOI 0x0098
72 #define AC97EOI_WINT BIT(0)
73 #define AC97EOI_CODECREADY BIT(1)
74
75 #define AC97GCR 0x009c
76 #define AC97GCR_AC97IFE BIT(0)
77
78 #define AC97RESET 0x00a0
79 #define AC97RESET_TIMEDRESET BIT(0)
80
81 #define AC97SYNC 0x00a4
82 #define AC97SYNC_TIMEDSYNC BIT(0)
83
84 #define AC97_TIMEOUT msecs_to_jiffies(5)
85
86 /**
87 * struct ep93xx_ac97_info - EP93xx AC97 controller info structure
88 * @lock: mutex serializing access to the bus (slot 1 & 2 ops)
89 * @dev: pointer to the platform device dev structure
90 * @regs: mapped AC97 controller registers
91 * @done: bus ops wait here for an interrupt
92 */
93 struct ep93xx_ac97_info {
94 struct mutex lock;
95 struct device *dev;
96 void __iomem *regs;
97 struct completion done;
98 };
99
100 /* currently ALSA only supports a single AC97 device */
101 static struct ep93xx_ac97_info *ep93xx_ac97_info;
102
103 static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
104 .name = "ac97-pcm-out",
105 .dma_port = EP93XX_DMA_AAC1,
106 .direction = DMA_MEM_TO_DEV,
107 };
108
109 static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
110 .name = "ac97-pcm-in",
111 .dma_port = EP93XX_DMA_AAC1,
112 .direction = DMA_DEV_TO_MEM,
113 };
114
ep93xx_ac97_read_reg(struct ep93xx_ac97_info * info,unsigned reg)115 static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
116 unsigned reg)
117 {
118 return __raw_readl(info->regs + reg);
119 }
120
ep93xx_ac97_write_reg(struct ep93xx_ac97_info * info,unsigned reg,unsigned val)121 static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
122 unsigned reg, unsigned val)
123 {
124 __raw_writel(val, info->regs + reg);
125 }
126
ep93xx_ac97_read(struct snd_ac97 * ac97,unsigned short reg)127 static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
128 unsigned short reg)
129 {
130 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
131 unsigned short val;
132
133 mutex_lock(&info->lock);
134
135 ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
136 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
137 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
138 dev_warn(info->dev, "timeout reading register %x\n", reg);
139 mutex_unlock(&info->lock);
140 return -ETIMEDOUT;
141 }
142 val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
143
144 mutex_unlock(&info->lock);
145 return val;
146 }
147
ep93xx_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)148 static void ep93xx_ac97_write(struct snd_ac97 *ac97,
149 unsigned short reg,
150 unsigned short val)
151 {
152 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
153
154 mutex_lock(&info->lock);
155
156 /*
157 * Writes to the codec need to be done so that slot 2 is filled in
158 * before slot 1.
159 */
160 ep93xx_ac97_write_reg(info, AC97S2DATA, val);
161 ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
162
163 ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
164 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
165 dev_warn(info->dev, "timeout writing register %x\n", reg);
166
167 mutex_unlock(&info->lock);
168 }
169
ep93xx_ac97_warm_reset(struct snd_ac97 * ac97)170 static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
171 {
172 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
173
174 mutex_lock(&info->lock);
175
176 /*
177 * We are assuming that before this functions gets called, the codec
178 * BIT_CLK is stopped by forcing the codec into powerdown mode. We can
179 * control the SYNC signal directly via AC97SYNC register. Using
180 * TIMEDSYNC the controller will keep the SYNC high > 1us.
181 */
182 ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
183 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
184 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
185 dev_warn(info->dev, "codec warm reset timeout\n");
186
187 mutex_unlock(&info->lock);
188 }
189
ep93xx_ac97_cold_reset(struct snd_ac97 * ac97)190 static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
191 {
192 struct ep93xx_ac97_info *info = ep93xx_ac97_info;
193
194 mutex_lock(&info->lock);
195
196 /*
197 * For doing cold reset, we disable the AC97 controller interface, clear
198 * WINT and CODECREADY bits, and finally enable the interface again.
199 */
200 ep93xx_ac97_write_reg(info, AC97GCR, 0);
201 ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
202 ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
203
204 /*
205 * Now, assert the reset and wait for the codec to become ready.
206 */
207 ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
208 ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
209 if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
210 dev_warn(info->dev, "codec cold reset timeout\n");
211
212 /*
213 * Give the codec some time to come fully out from the reset. This way
214 * we ensure that the subsequent reads/writes will work.
215 */
216 usleep_range(15000, 20000);
217
218 mutex_unlock(&info->lock);
219 }
220
ep93xx_ac97_interrupt(int irq,void * dev_id)221 static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
222 {
223 struct ep93xx_ac97_info *info = dev_id;
224 unsigned status, mask;
225
226 /*
227 * Just mask out the interrupt and wake up the waiting thread.
228 * Interrupts are cleared via reading/writing to slot 1 & 2 registers by
229 * the waiting thread.
230 */
231 status = ep93xx_ac97_read_reg(info, AC97GIS);
232 mask = ep93xx_ac97_read_reg(info, AC97IM);
233 mask &= ~status;
234 ep93xx_ac97_write_reg(info, AC97IM, mask);
235
236 complete(&info->done);
237 return IRQ_HANDLED;
238 }
239
240 struct snd_ac97_bus_ops soc_ac97_ops = {
241 .read = ep93xx_ac97_read,
242 .write = ep93xx_ac97_write,
243 .reset = ep93xx_ac97_cold_reset,
244 .warm_reset = ep93xx_ac97_warm_reset,
245 };
246 EXPORT_SYMBOL_GPL(soc_ac97_ops);
247
ep93xx_ac97_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)248 static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
249 int cmd, struct snd_soc_dai *dai)
250 {
251 struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
252 unsigned v = 0;
253
254 switch (cmd) {
255 case SNDRV_PCM_TRIGGER_START:
256 case SNDRV_PCM_TRIGGER_RESUME:
257 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
258 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
259 /*
260 * Enable compact mode, TX slots 3 & 4, and the TX FIFO
261 * itself.
262 */
263 v |= AC97TXCR_CM;
264 v |= AC97TXCR_TX3 | AC97TXCR_TX4;
265 v |= AC97TXCR_TEN;
266 ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
267 } else {
268 /*
269 * Enable compact mode, RX slots 3 & 4, and the RX FIFO
270 * itself.
271 */
272 v |= AC97RXCR_CM;
273 v |= AC97RXCR_RX3 | AC97RXCR_RX4;
274 v |= AC97RXCR_REN;
275 ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
276 }
277 break;
278
279 case SNDRV_PCM_TRIGGER_STOP:
280 case SNDRV_PCM_TRIGGER_SUSPEND:
281 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
282 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
283 /*
284 * As per Cirrus EP93xx errata described below:
285 *
286 * http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
287 *
288 * we will wait for the TX FIFO to be empty before
289 * clearing the TEN bit.
290 */
291 unsigned long timeout = jiffies + AC97_TIMEOUT;
292
293 do {
294 v = ep93xx_ac97_read_reg(info, AC97SR(1));
295 if (time_after(jiffies, timeout)) {
296 dev_warn(info->dev, "TX timeout\n");
297 break;
298 }
299 } while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
300
301 /* disable the TX FIFO */
302 ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
303 } else {
304 /* disable the RX FIFO */
305 ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
306 }
307 break;
308
309 default:
310 dev_warn(info->dev, "unknown command %d\n", cmd);
311 return -EINVAL;
312 }
313
314 return 0;
315 }
316
ep93xx_ac97_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)317 static int ep93xx_ac97_startup(struct snd_pcm_substream *substream,
318 struct snd_soc_dai *dai)
319 {
320 struct ep93xx_dma_data *dma_data;
321
322 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
323 dma_data = &ep93xx_ac97_pcm_out;
324 else
325 dma_data = &ep93xx_ac97_pcm_in;
326
327 snd_soc_dai_set_dma_data(dai, substream, dma_data);
328 return 0;
329 }
330
331 static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
332 .startup = ep93xx_ac97_startup,
333 .trigger = ep93xx_ac97_trigger,
334 };
335
336 static struct snd_soc_dai_driver ep93xx_ac97_dai = {
337 .name = "ep93xx-ac97",
338 .id = 0,
339 .ac97_control = 1,
340 .playback = {
341 .stream_name = "AC97 Playback",
342 .channels_min = 2,
343 .channels_max = 2,
344 .rates = SNDRV_PCM_RATE_8000_48000,
345 .formats = SNDRV_PCM_FMTBIT_S16_LE,
346 },
347 .capture = {
348 .stream_name = "AC97 Capture",
349 .channels_min = 2,
350 .channels_max = 2,
351 .rates = SNDRV_PCM_RATE_8000_48000,
352 .formats = SNDRV_PCM_FMTBIT_S16_LE,
353 },
354 .ops = &ep93xx_ac97_dai_ops,
355 };
356
357 static const struct snd_soc_component_driver ep93xx_ac97_component = {
358 .name = "ep93xx-ac97",
359 };
360
ep93xx_ac97_probe(struct platform_device * pdev)361 static int ep93xx_ac97_probe(struct platform_device *pdev)
362 {
363 struct ep93xx_ac97_info *info;
364 struct resource *res;
365 unsigned int irq;
366 int ret;
367
368 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
369 if (!info)
370 return -ENOMEM;
371
372 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 if (!res)
374 return -ENODEV;
375
376 info->regs = devm_ioremap_resource(&pdev->dev, res);
377 if (IS_ERR(info->regs))
378 return PTR_ERR(info->regs);
379
380 irq = platform_get_irq(pdev, 0);
381 if (!irq)
382 return -ENODEV;
383
384 ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
385 IRQF_TRIGGER_HIGH, pdev->name, info);
386 if (ret)
387 goto fail;
388
389 dev_set_drvdata(&pdev->dev, info);
390
391 mutex_init(&info->lock);
392 init_completion(&info->done);
393 info->dev = &pdev->dev;
394
395 ep93xx_ac97_info = info;
396 platform_set_drvdata(pdev, info);
397
398 ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
399 &ep93xx_ac97_dai, 1);
400 if (ret)
401 goto fail;
402
403 return 0;
404
405 fail:
406 platform_set_drvdata(pdev, NULL);
407 ep93xx_ac97_info = NULL;
408 dev_set_drvdata(&pdev->dev, NULL);
409 return ret;
410 }
411
ep93xx_ac97_remove(struct platform_device * pdev)412 static int ep93xx_ac97_remove(struct platform_device *pdev)
413 {
414 struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
415
416 snd_soc_unregister_component(&pdev->dev);
417
418 /* disable the AC97 controller */
419 ep93xx_ac97_write_reg(info, AC97GCR, 0);
420
421 platform_set_drvdata(pdev, NULL);
422 ep93xx_ac97_info = NULL;
423 dev_set_drvdata(&pdev->dev, NULL);
424
425 return 0;
426 }
427
428 static struct platform_driver ep93xx_ac97_driver = {
429 .probe = ep93xx_ac97_probe,
430 .remove = ep93xx_ac97_remove,
431 .driver = {
432 .name = "ep93xx-ac97",
433 .owner = THIS_MODULE,
434 },
435 };
436
437 module_platform_driver(ep93xx_ac97_driver);
438
439 MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
440 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
441 MODULE_LICENSE("GPL");
442 MODULE_ALIAS("platform:ep93xx-ac97");
443