1 /*
2 * omap-mcpdm.c -- OMAP ALSA SoC DAI driver using McPDM port
3 *
4 * Copyright (C) 2009 - 2011 Texas Instruments
5 *
6 * Author: Misael Lopez Cruz <misael.lopez@ti.com>
7 * Contact: Jorge Eduardo Candelaria <x0107209@ti.com>
8 * Margarita Olaya <magi.olaya@ti.com>
9 * Peter Ujfalusi <peter.ujfalusi@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18 * General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
23 * 02110-1301 USA
24 *
25 */
26
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/interrupt.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/slab.h>
35 #include <linux/pm_runtime.h>
36 #include <linux/of_device.h>
37
38 #include <sound/core.h>
39 #include <sound/pcm.h>
40 #include <sound/pcm_params.h>
41 #include <sound/soc.h>
42 #include <sound/dmaengine_pcm.h>
43
44 #include "omap-mcpdm.h"
45
46 struct mcpdm_link_config {
47 u32 link_mask; /* channel mask for the direction */
48 u32 threshold; /* FIFO threshold */
49 };
50
51 struct omap_mcpdm {
52 struct device *dev;
53 unsigned long phys_base;
54 void __iomem *io_base;
55 int irq;
56
57 struct mutex mutex;
58
59 /* Playback/Capture configuration */
60 struct mcpdm_link_config config[2];
61
62 /* McPDM dn offsets for rx1, and 2 channels */
63 u32 dn_rx_offset;
64
65 /* McPDM needs to be restarted due to runtime reconfiguration */
66 bool restart;
67
68 struct snd_dmaengine_dai_dma_data dma_data[2];
69 unsigned int dma_req[2];
70 };
71
72 /*
73 * Stream DMA parameters
74 */
75
omap_mcpdm_write(struct omap_mcpdm * mcpdm,u16 reg,u32 val)76 static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
77 {
78 __raw_writel(val, mcpdm->io_base + reg);
79 }
80
omap_mcpdm_read(struct omap_mcpdm * mcpdm,u16 reg)81 static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
82 {
83 return __raw_readl(mcpdm->io_base + reg);
84 }
85
86 #ifdef DEBUG
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)87 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
88 {
89 dev_dbg(mcpdm->dev, "***********************\n");
90 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
91 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
92 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
93 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
94 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
95 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
96 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
97 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
98 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
99 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
100 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
101 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
102 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
103 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
104 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
105 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
106 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
107 omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
108 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
109 omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
110 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
111 omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
112 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
113 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
114 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
115 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
116 dev_dbg(mcpdm->dev, "***********************\n");
117 }
118 #else
omap_mcpdm_reg_dump(struct omap_mcpdm * mcpdm)119 static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
120 #endif
121
122 /*
123 * Enables the transfer through the PDM interface to/from the Phoenix
124 * codec by enabling the corresponding UP or DN channels.
125 */
omap_mcpdm_start(struct omap_mcpdm * mcpdm)126 static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
127 {
128 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
129 u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
130
131 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
132 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
133
134 ctrl |= link_mask;
135 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
136
137 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
138 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
139 }
140
141 /*
142 * Disables the transfer through the PDM interface to/from the Phoenix
143 * codec by disabling the corresponding UP or DN channels.
144 */
omap_mcpdm_stop(struct omap_mcpdm * mcpdm)145 static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
146 {
147 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
148 u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
149
150 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
151 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
152
153 ctrl &= ~(link_mask);
154 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
155
156 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
157 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
158
159 }
160
161 /*
162 * Is the physical McPDM interface active.
163 */
omap_mcpdm_active(struct omap_mcpdm * mcpdm)164 static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
165 {
166 return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
167 (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
168 }
169
170 /*
171 * Configures McPDM uplink, and downlink for audio.
172 * This function should be called before omap_mcpdm_start.
173 */
omap_mcpdm_open_streams(struct omap_mcpdm * mcpdm)174 static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
175 {
176 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
177 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
178 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
179
180 /* Enable DN RX1/2 offset cancellation feature, if configured */
181 if (mcpdm->dn_rx_offset) {
182 u32 dn_offset = mcpdm->dn_rx_offset;
183
184 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
185 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
186 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
187 }
188
189 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
190 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
191 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
192 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
193
194 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
195 MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
196 }
197
198 /*
199 * Cleans McPDM uplink, and downlink configuration.
200 * This function should be called when the stream is closed.
201 */
omap_mcpdm_close_streams(struct omap_mcpdm * mcpdm)202 static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
203 {
204 /* Disable irq request generation for downlink */
205 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
206 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
207
208 /* Disable DMA request generation for downlink */
209 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
210
211 /* Disable irq request generation for uplink */
212 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
213 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
214
215 /* Disable DMA request generation for uplink */
216 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
217
218 /* Disable RX1/2 offset cancellation */
219 if (mcpdm->dn_rx_offset)
220 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
221 }
222
omap_mcpdm_irq_handler(int irq,void * dev_id)223 static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
224 {
225 struct omap_mcpdm *mcpdm = dev_id;
226 int irq_status;
227
228 irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
229
230 /* Acknowledge irq event */
231 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
232
233 if (irq_status & MCPDM_DN_IRQ_FULL)
234 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
235
236 if (irq_status & MCPDM_DN_IRQ_EMPTY)
237 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
238
239 if (irq_status & MCPDM_DN_IRQ)
240 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
241
242 if (irq_status & MCPDM_UP_IRQ_FULL)
243 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
244
245 if (irq_status & MCPDM_UP_IRQ_EMPTY)
246 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
247
248 if (irq_status & MCPDM_UP_IRQ)
249 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
250
251 return IRQ_HANDLED;
252 }
253
omap_mcpdm_dai_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)254 static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
255 struct snd_soc_dai *dai)
256 {
257 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
258
259 mutex_lock(&mcpdm->mutex);
260
261 if (!dai->active) {
262 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
263
264 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
265 omap_mcpdm_open_streams(mcpdm);
266 }
267 mutex_unlock(&mcpdm->mutex);
268
269 snd_soc_dai_set_dma_data(dai, substream,
270 &mcpdm->dma_data[substream->stream]);
271
272 return 0;
273 }
274
omap_mcpdm_dai_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)275 static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
276 struct snd_soc_dai *dai)
277 {
278 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
279
280 mutex_lock(&mcpdm->mutex);
281
282 if (!dai->active) {
283 if (omap_mcpdm_active(mcpdm)) {
284 omap_mcpdm_stop(mcpdm);
285 omap_mcpdm_close_streams(mcpdm);
286 mcpdm->config[0].link_mask = 0;
287 mcpdm->config[1].link_mask = 0;
288 }
289 }
290
291 mutex_unlock(&mcpdm->mutex);
292 }
293
omap_mcpdm_dai_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)294 static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
295 struct snd_pcm_hw_params *params,
296 struct snd_soc_dai *dai)
297 {
298 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
299 int stream = substream->stream;
300 struct snd_dmaengine_dai_dma_data *dma_data;
301 u32 threshold;
302 int channels;
303 int link_mask = 0;
304
305 channels = params_channels(params);
306 switch (channels) {
307 case 5:
308 if (stream == SNDRV_PCM_STREAM_CAPTURE)
309 /* up to 3 channels for capture */
310 return -EINVAL;
311 link_mask |= 1 << 4;
312 case 4:
313 if (stream == SNDRV_PCM_STREAM_CAPTURE)
314 /* up to 3 channels for capture */
315 return -EINVAL;
316 link_mask |= 1 << 3;
317 case 3:
318 link_mask |= 1 << 2;
319 case 2:
320 link_mask |= 1 << 1;
321 case 1:
322 link_mask |= 1 << 0;
323 break;
324 default:
325 /* unsupported number of channels */
326 return -EINVAL;
327 }
328
329 dma_data = snd_soc_dai_get_dma_data(dai, substream);
330
331 threshold = mcpdm->config[stream].threshold;
332 /* Configure McPDM channels, and DMA packet size */
333 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
334 link_mask <<= 3;
335
336 /* If capture is not running assume a stereo stream to come */
337 if (!mcpdm->config[!stream].link_mask)
338 mcpdm->config[!stream].link_mask = 0x3;
339
340 dma_data->maxburst =
341 (MCPDM_DN_THRES_MAX - threshold) * channels;
342 } else {
343 /* If playback is not running assume a stereo stream to come */
344 if (!mcpdm->config[!stream].link_mask)
345 mcpdm->config[!stream].link_mask = (0x3 << 3);
346
347 dma_data->maxburst = threshold * channels;
348 }
349
350 /* Check if we need to restart McPDM with this stream */
351 if (mcpdm->config[stream].link_mask &&
352 mcpdm->config[stream].link_mask != link_mask)
353 mcpdm->restart = true;
354
355 mcpdm->config[stream].link_mask = link_mask;
356
357 return 0;
358 }
359
omap_mcpdm_prepare(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)360 static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
361 struct snd_soc_dai *dai)
362 {
363 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
364
365 if (!omap_mcpdm_active(mcpdm)) {
366 omap_mcpdm_start(mcpdm);
367 omap_mcpdm_reg_dump(mcpdm);
368 } else if (mcpdm->restart) {
369 omap_mcpdm_stop(mcpdm);
370 omap_mcpdm_start(mcpdm);
371 mcpdm->restart = false;
372 omap_mcpdm_reg_dump(mcpdm);
373 }
374
375 return 0;
376 }
377
378 static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
379 .startup = omap_mcpdm_dai_startup,
380 .shutdown = omap_mcpdm_dai_shutdown,
381 .hw_params = omap_mcpdm_dai_hw_params,
382 .prepare = omap_mcpdm_prepare,
383 };
384
omap_mcpdm_probe(struct snd_soc_dai * dai)385 static int omap_mcpdm_probe(struct snd_soc_dai *dai)
386 {
387 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
388 int ret;
389
390 pm_runtime_enable(mcpdm->dev);
391
392 /* Disable lines while request is ongoing */
393 pm_runtime_get_sync(mcpdm->dev);
394 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
395
396 ret = devm_request_irq(mcpdm->dev, mcpdm->irq, omap_mcpdm_irq_handler,
397 0, "McPDM", (void *)mcpdm);
398
399 pm_runtime_put_sync(mcpdm->dev);
400
401 if (ret) {
402 dev_err(mcpdm->dev, "Request for IRQ failed\n");
403 pm_runtime_disable(mcpdm->dev);
404 }
405
406 /* Configure McPDM threshold values */
407 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
408 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
409 MCPDM_UP_THRES_MAX - 3;
410 return ret;
411 }
412
omap_mcpdm_remove(struct snd_soc_dai * dai)413 static int omap_mcpdm_remove(struct snd_soc_dai *dai)
414 {
415 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
416
417 pm_runtime_disable(mcpdm->dev);
418
419 return 0;
420 }
421
422 #define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
423 #define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
424
425 static struct snd_soc_dai_driver omap_mcpdm_dai = {
426 .probe = omap_mcpdm_probe,
427 .remove = omap_mcpdm_remove,
428 .probe_order = SND_SOC_COMP_ORDER_LATE,
429 .remove_order = SND_SOC_COMP_ORDER_EARLY,
430 .playback = {
431 .channels_min = 1,
432 .channels_max = 5,
433 .rates = OMAP_MCPDM_RATES,
434 .formats = OMAP_MCPDM_FORMATS,
435 .sig_bits = 24,
436 },
437 .capture = {
438 .channels_min = 1,
439 .channels_max = 3,
440 .rates = OMAP_MCPDM_RATES,
441 .formats = OMAP_MCPDM_FORMATS,
442 .sig_bits = 24,
443 },
444 .ops = &omap_mcpdm_dai_ops,
445 };
446
447 static const struct snd_soc_component_driver omap_mcpdm_component = {
448 .name = "omap-mcpdm",
449 };
450
omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime * rtd,u8 rx1,u8 rx2)451 void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
452 u8 rx1, u8 rx2)
453 {
454 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
455
456 mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
457 }
458 EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
459
asoc_mcpdm_probe(struct platform_device * pdev)460 static int asoc_mcpdm_probe(struct platform_device *pdev)
461 {
462 struct omap_mcpdm *mcpdm;
463 struct resource *res;
464
465 mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
466 if (!mcpdm)
467 return -ENOMEM;
468
469 platform_set_drvdata(pdev, mcpdm);
470
471 mutex_init(&mcpdm->mutex);
472
473 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
474 if (res == NULL)
475 return -ENOMEM;
476
477 mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
478 mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
479
480 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "dn_link");
481 if (!res)
482 return -ENODEV;
483
484 mcpdm->dma_req[0] = res->start;
485 mcpdm->dma_data[0].filter_data = &mcpdm->dma_req[0];
486
487 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "up_link");
488 if (!res)
489 return -ENODEV;
490
491 mcpdm->dma_req[1] = res->start;
492 mcpdm->dma_data[1].filter_data = &mcpdm->dma_req[1];
493
494 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
495 if (res == NULL)
496 return -ENOMEM;
497
498 mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
499 if (IS_ERR(mcpdm->io_base))
500 return PTR_ERR(mcpdm->io_base);
501
502 mcpdm->irq = platform_get_irq(pdev, 0);
503 if (mcpdm->irq < 0)
504 return mcpdm->irq;
505
506 mcpdm->dev = &pdev->dev;
507
508 return snd_soc_register_component(&pdev->dev, &omap_mcpdm_component,
509 &omap_mcpdm_dai, 1);
510 }
511
asoc_mcpdm_remove(struct platform_device * pdev)512 static int asoc_mcpdm_remove(struct platform_device *pdev)
513 {
514 snd_soc_unregister_component(&pdev->dev);
515 return 0;
516 }
517
518 static const struct of_device_id omap_mcpdm_of_match[] = {
519 { .compatible = "ti,omap4-mcpdm", },
520 { }
521 };
522 MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
523
524 static struct platform_driver asoc_mcpdm_driver = {
525 .driver = {
526 .name = "omap-mcpdm",
527 .owner = THIS_MODULE,
528 .of_match_table = omap_mcpdm_of_match,
529 },
530
531 .probe = asoc_mcpdm_probe,
532 .remove = asoc_mcpdm_remove,
533 };
534
535 module_platform_driver(asoc_mcpdm_driver);
536
537 MODULE_ALIAS("platform:omap-mcpdm");
538 MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
539 MODULE_DESCRIPTION("OMAP PDM SoC Interface");
540 MODULE_LICENSE("GPL");
541