Lines Matching refs:clks
85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
184 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
194 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195 <&clks IMX5_CLK_UART3_PER_GATE>;
206 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
217 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
229 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
230 <&clks IMX5_CLK_DUMMY>,
231 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
241 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
242 <&clks IMX5_CLK_DUMMY>,
243 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
254 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
264 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
273 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
282 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
291 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
338 clocks = <&clks IMX5_CLK_DUMMY>;
346 clocks = <&clks IMX5_CLK_DUMMY>;
353 clocks = <&clks IMX5_CLK_DUMMY>;
361 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
362 <&clks IMX5_CLK_GPT_HF_GATE>;
375 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
376 <&clks IMX5_CLK_PWM1_HF_GATE>;
385 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
386 <&clks IMX5_CLK_PWM2_HF_GATE>;
395 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
396 <&clks IMX5_CLK_UART1_PER_GATE>;
405 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
406 <&clks IMX5_CLK_UART2_PER_GATE>;
417 clks: ccm@73fd4000{ label
436 clocks = <&clks IMX5_CLK_IIM_GATE>;
443 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
453 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
454 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
463 clocks = <&clks IMX5_CLK_SDMA_GATE>,
464 <&clks IMX5_CLK_SDMA_GATE>;
476 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
477 <&clks IMX5_CLK_CSPI_IPG_GATE>;
488 clocks = <&clks IMX5_CLK_I2C2_GATE>;
498 clocks = <&clks IMX5_CLK_I2C1_GATE>;
507 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
518 clocks = <&clks IMX5_CLK_DUMMY>;
528 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
546 clocks = <&clks IMX5_CLK_NFC_GATE>;
554 clocks = <&clks IMX5_CLK_PATA_GATE>;
563 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
575 clocks = <&clks IMX5_CLK_FEC_GATE>,
576 <&clks IMX5_CLK_FEC_GATE>,
577 <&clks IMX5_CLK_FEC_GATE>;