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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include "skeleton.dtsi"
14#include "imx51-pinfunc.h"
15#include <dt-bindings/clock/imx5-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21	aliases {
22		ethernet0 = &fec;
23		gpio0 = &gpio1;
24		gpio1 = &gpio2;
25		gpio2 = &gpio3;
26		gpio3 = &gpio4;
27		i2c0 = &i2c1;
28		i2c1 = &i2c2;
29		mmc0 = &esdhc1;
30		mmc1 = &esdhc2;
31		mmc2 = &esdhc3;
32		mmc3 = &esdhc4;
33		serial0 = &uart1;
34		serial1 = &uart2;
35		serial2 = &uart3;
36		spi0 = &ecspi1;
37		spi1 = &ecspi2;
38		spi2 = &cspi;
39	};
40
41	tzic: tz-interrupt-controller@e0000000 {
42		compatible = "fsl,imx51-tzic", "fsl,tzic";
43		interrupt-controller;
44		#interrupt-cells = <1>;
45		reg = <0xe0000000 0x4000>;
46	};
47
48	clocks {
49		#address-cells = <1>;
50		#size-cells = <0>;
51
52		ckil {
53			compatible = "fsl,imx-ckil", "fixed-clock";
54			#clock-cells = <0>;
55			clock-frequency = <32768>;
56		};
57
58		ckih1 {
59			compatible = "fsl,imx-ckih1", "fixed-clock";
60			#clock-cells = <0>;
61			clock-frequency = <0>;
62		};
63
64		ckih2 {
65			compatible = "fsl,imx-ckih2", "fixed-clock";
66			#clock-cells = <0>;
67			clock-frequency = <0>;
68		};
69
70		osc {
71			compatible = "fsl,imx-osc", "fixed-clock";
72			#clock-cells = <0>;
73			clock-frequency = <24000000>;
74		};
75	};
76
77	cpus {
78		#address-cells = <1>;
79		#size-cells = <0>;
80		cpu: cpu@0 {
81			device_type = "cpu";
82			compatible = "arm,cortex-a8";
83			reg = <0>;
84			clock-latency = <62500>;
85			clocks = <&clks IMX5_CLK_CPU_PODF>;
86			clock-names = "cpu";
87			operating-points = <
88				166000	1000000
89				600000	1050000
90				800000	1100000
91			>;
92			voltage-tolerance = <5>;
93		};
94	};
95
96	usbphy {
97		#address-cells = <1>;
98		#size-cells = <0>;
99		compatible = "simple-bus";
100
101		usbphy0: usbphy@0 {
102			compatible = "usb-nop-xceiv";
103			reg = <0>;
104			clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
105			clock-names = "main_clk";
106		};
107	};
108
109	display-subsystem {
110		compatible = "fsl,imx-display-subsystem";
111		ports = <&ipu_di0>, <&ipu_di1>;
112	};
113
114	soc {
115		#address-cells = <1>;
116		#size-cells = <1>;
117		compatible = "simple-bus";
118		interrupt-parent = <&tzic>;
119		ranges;
120
121		iram: iram@1ffe0000 {
122			compatible = "mmio-sram";
123			reg = <0x1ffe0000 0x20000>;
124		};
125
126		ipu: ipu@40000000 {
127			#address-cells = <1>;
128			#size-cells = <0>;
129			compatible = "fsl,imx51-ipu";
130			reg = <0x40000000 0x20000000>;
131			interrupts = <11 10>;
132			clocks = <&clks IMX5_CLK_IPU_GATE>,
133			         <&clks IMX5_CLK_IPU_DI0_GATE>,
134			         <&clks IMX5_CLK_IPU_DI1_GATE>;
135			clock-names = "bus", "di0", "di1";
136			resets = <&src 2>;
137
138			ipu_di0: port@2 {
139				reg = <2>;
140
141				ipu_di0_disp0: endpoint {
142				};
143			};
144
145			ipu_di1: port@3 {
146				reg = <3>;
147
148				ipu_di1_disp1: endpoint {
149				};
150			};
151		};
152
153		aips@70000000 { /* AIPS1 */
154			compatible = "fsl,aips-bus", "simple-bus";
155			#address-cells = <1>;
156			#size-cells = <1>;
157			reg = <0x70000000 0x10000000>;
158			ranges;
159
160			spba@70000000 {
161				compatible = "fsl,spba-bus", "simple-bus";
162				#address-cells = <1>;
163				#size-cells = <1>;
164				reg = <0x70000000 0x40000>;
165				ranges;
166
167				esdhc1: esdhc@70004000 {
168					compatible = "fsl,imx51-esdhc";
169					reg = <0x70004000 0x4000>;
170					interrupts = <1>;
171					clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172					         <&clks IMX5_CLK_DUMMY>,
173					         <&clks IMX5_CLK_ESDHC1_PER_GATE>;
174					clock-names = "ipg", "ahb", "per";
175					status = "disabled";
176				};
177
178				esdhc2: esdhc@70008000 {
179					compatible = "fsl,imx51-esdhc";
180					reg = <0x70008000 0x4000>;
181					interrupts = <2>;
182					clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183					         <&clks IMX5_CLK_DUMMY>,
184					         <&clks IMX5_CLK_ESDHC2_PER_GATE>;
185					clock-names = "ipg", "ahb", "per";
186					bus-width = <4>;
187					status = "disabled";
188				};
189
190				uart3: serial@7000c000 {
191					compatible = "fsl,imx51-uart", "fsl,imx21-uart";
192					reg = <0x7000c000 0x4000>;
193					interrupts = <33>;
194					clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
195					         <&clks IMX5_CLK_UART3_PER_GATE>;
196					clock-names = "ipg", "per";
197					status = "disabled";
198				};
199
200				ecspi1: ecspi@70010000 {
201					#address-cells = <1>;
202					#size-cells = <0>;
203					compatible = "fsl,imx51-ecspi";
204					reg = <0x70010000 0x4000>;
205					interrupts = <36>;
206					clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
207					         <&clks IMX5_CLK_ECSPI1_PER_GATE>;
208					clock-names = "ipg", "per";
209					status = "disabled";
210				};
211
212				ssi2: ssi@70014000 {
213					#sound-dai-cells = <0>;
214					compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
215					reg = <0x70014000 0x4000>;
216					interrupts = <30>;
217					clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
218					dmas = <&sdma 24 1 0>,
219					       <&sdma 25 1 0>;
220					dma-names = "rx", "tx";
221					fsl,fifo-depth = <15>;
222					status = "disabled";
223				};
224
225				esdhc3: esdhc@70020000 {
226					compatible = "fsl,imx51-esdhc";
227					reg = <0x70020000 0x4000>;
228					interrupts = <3>;
229					clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
230					         <&clks IMX5_CLK_DUMMY>,
231					         <&clks IMX5_CLK_ESDHC3_PER_GATE>;
232					clock-names = "ipg", "ahb", "per";
233					bus-width = <4>;
234					status = "disabled";
235				};
236
237				esdhc4: esdhc@70024000 {
238					compatible = "fsl,imx51-esdhc";
239					reg = <0x70024000 0x4000>;
240					interrupts = <4>;
241					clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
242					         <&clks IMX5_CLK_DUMMY>,
243					         <&clks IMX5_CLK_ESDHC4_PER_GATE>;
244					clock-names = "ipg", "ahb", "per";
245					bus-width = <4>;
246					status = "disabled";
247				};
248			};
249
250			usbotg: usb@73f80000 {
251				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
252				reg = <0x73f80000 0x0200>;
253				interrupts = <18>;
254				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
255				fsl,usbmisc = <&usbmisc 0>;
256				fsl,usbphy = <&usbphy0>;
257				status = "disabled";
258			};
259
260			usbh1: usb@73f80200 {
261				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
262				reg = <0x73f80200 0x0200>;
263				interrupts = <14>;
264				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
265				fsl,usbmisc = <&usbmisc 1>;
266				status = "disabled";
267			};
268
269			usbh2: usb@73f80400 {
270				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
271				reg = <0x73f80400 0x0200>;
272				interrupts = <16>;
273				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
274				fsl,usbmisc = <&usbmisc 2>;
275				status = "disabled";
276			};
277
278			usbh3: usb@73f80600 {
279				compatible = "fsl,imx51-usb", "fsl,imx27-usb";
280				reg = <0x73f80600 0x0200>;
281				interrupts = <17>;
282				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
283				fsl,usbmisc = <&usbmisc 3>;
284				status = "disabled";
285			};
286
287			usbmisc: usbmisc@73f80800 {
288				#index-cells = <1>;
289				compatible = "fsl,imx51-usbmisc";
290				reg = <0x73f80800 0x200>;
291				clocks = <&clks IMX5_CLK_USBOH3_GATE>;
292			};
293
294			gpio1: gpio@73f84000 {
295				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
296				reg = <0x73f84000 0x4000>;
297				interrupts = <50 51>;
298				gpio-controller;
299				#gpio-cells = <2>;
300				interrupt-controller;
301				#interrupt-cells = <2>;
302			};
303
304			gpio2: gpio@73f88000 {
305				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
306				reg = <0x73f88000 0x4000>;
307				interrupts = <52 53>;
308				gpio-controller;
309				#gpio-cells = <2>;
310				interrupt-controller;
311				#interrupt-cells = <2>;
312			};
313
314			gpio3: gpio@73f8c000 {
315				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
316				reg = <0x73f8c000 0x4000>;
317				interrupts = <54 55>;
318				gpio-controller;
319				#gpio-cells = <2>;
320				interrupt-controller;
321				#interrupt-cells = <2>;
322			};
323
324			gpio4: gpio@73f90000 {
325				compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
326				reg = <0x73f90000 0x4000>;
327				interrupts = <56 57>;
328				gpio-controller;
329				#gpio-cells = <2>;
330				interrupt-controller;
331				#interrupt-cells = <2>;
332			};
333
334			kpp: kpp@73f94000 {
335				compatible = "fsl,imx51-kpp", "fsl,imx21-kpp";
336				reg = <0x73f94000 0x4000>;
337				interrupts = <60>;
338				clocks = <&clks IMX5_CLK_DUMMY>;
339				status = "disabled";
340			};
341
342			wdog1: wdog@73f98000 {
343				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
344				reg = <0x73f98000 0x4000>;
345				interrupts = <58>;
346				clocks = <&clks IMX5_CLK_DUMMY>;
347			};
348
349			wdog2: wdog@73f9c000 {
350				compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
351				reg = <0x73f9c000 0x4000>;
352				interrupts = <59>;
353				clocks = <&clks IMX5_CLK_DUMMY>;
354				status = "disabled";
355			};
356
357			gpt: timer@73fa0000 {
358				compatible = "fsl,imx51-gpt", "fsl,imx31-gpt";
359				reg = <0x73fa0000 0x4000>;
360				interrupts = <39>;
361				clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
362				         <&clks IMX5_CLK_GPT_HF_GATE>;
363				clock-names = "ipg", "per";
364			};
365
366			iomuxc: iomuxc@73fa8000 {
367				compatible = "fsl,imx51-iomuxc";
368				reg = <0x73fa8000 0x4000>;
369			};
370
371			pwm1: pwm@73fb4000 {
372				#pwm-cells = <2>;
373				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
374				reg = <0x73fb4000 0x4000>;
375				clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
376				         <&clks IMX5_CLK_PWM1_HF_GATE>;
377				clock-names = "ipg", "per";
378				interrupts = <61>;
379			};
380
381			pwm2: pwm@73fb8000 {
382				#pwm-cells = <2>;
383				compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
384				reg = <0x73fb8000 0x4000>;
385				clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
386				         <&clks IMX5_CLK_PWM2_HF_GATE>;
387				clock-names = "ipg", "per";
388				interrupts = <94>;
389			};
390
391			uart1: serial@73fbc000 {
392				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
393				reg = <0x73fbc000 0x4000>;
394				interrupts = <31>;
395				clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
396				         <&clks IMX5_CLK_UART1_PER_GATE>;
397				clock-names = "ipg", "per";
398				status = "disabled";
399			};
400
401			uart2: serial@73fc0000 {
402				compatible = "fsl,imx51-uart", "fsl,imx21-uart";
403				reg = <0x73fc0000 0x4000>;
404				interrupts = <32>;
405				clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
406				         <&clks IMX5_CLK_UART2_PER_GATE>;
407				clock-names = "ipg", "per";
408				status = "disabled";
409			};
410
411			src: src@73fd0000 {
412				compatible = "fsl,imx51-src";
413				reg = <0x73fd0000 0x4000>;
414				#reset-cells = <1>;
415			};
416
417			clks: ccm@73fd4000{
418				compatible = "fsl,imx51-ccm";
419				reg = <0x73fd4000 0x4000>;
420				interrupts = <0 71 0x04 0 72 0x04>;
421				#clock-cells = <1>;
422			};
423		};
424
425		aips@80000000 {	/* AIPS2 */
426			compatible = "fsl,aips-bus", "simple-bus";
427			#address-cells = <1>;
428			#size-cells = <1>;
429			reg = <0x80000000 0x10000000>;
430			ranges;
431
432			iim: iim@83f98000 {
433				compatible = "fsl,imx51-iim", "fsl,imx27-iim";
434				reg = <0x83f98000 0x4000>;
435				interrupts = <69>;
436				clocks = <&clks IMX5_CLK_IIM_GATE>;
437			};
438
439			owire: owire@83fa4000 {
440				compatible = "fsl,imx51-owire", "fsl,imx21-owire";
441				reg = <0x83fa4000 0x4000>;
442				interrupts = <88>;
443				clocks = <&clks IMX5_CLK_OWIRE_GATE>;
444				status = "disabled";
445			};
446
447			ecspi2: ecspi@83fac000 {
448				#address-cells = <1>;
449				#size-cells = <0>;
450				compatible = "fsl,imx51-ecspi";
451				reg = <0x83fac000 0x4000>;
452				interrupts = <37>;
453				clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
454				         <&clks IMX5_CLK_ECSPI2_PER_GATE>;
455				clock-names = "ipg", "per";
456				status = "disabled";
457			};
458
459			sdma: sdma@83fb0000 {
460				compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
461				reg = <0x83fb0000 0x4000>;
462				interrupts = <6>;
463				clocks = <&clks IMX5_CLK_SDMA_GATE>,
464				         <&clks IMX5_CLK_SDMA_GATE>;
465				clock-names = "ipg", "ahb";
466				#dma-cells = <3>;
467				fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
468			};
469
470			cspi: cspi@83fc0000 {
471				#address-cells = <1>;
472				#size-cells = <0>;
473				compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
474				reg = <0x83fc0000 0x4000>;
475				interrupts = <38>;
476				clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
477				         <&clks IMX5_CLK_CSPI_IPG_GATE>;
478				clock-names = "ipg", "per";
479				status = "disabled";
480			};
481
482			i2c2: i2c@83fc4000 {
483				#address-cells = <1>;
484				#size-cells = <0>;
485				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
486				reg = <0x83fc4000 0x4000>;
487				interrupts = <63>;
488				clocks = <&clks IMX5_CLK_I2C2_GATE>;
489				status = "disabled";
490			};
491
492			i2c1: i2c@83fc8000 {
493				#address-cells = <1>;
494				#size-cells = <0>;
495				compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
496				reg = <0x83fc8000 0x4000>;
497				interrupts = <62>;
498				clocks = <&clks IMX5_CLK_I2C1_GATE>;
499				status = "disabled";
500			};
501
502			ssi1: ssi@83fcc000 {
503				#sound-dai-cells = <0>;
504				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
505				reg = <0x83fcc000 0x4000>;
506				interrupts = <29>;
507				clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
508				dmas = <&sdma 28 0 0>,
509				       <&sdma 29 0 0>;
510				dma-names = "rx", "tx";
511				fsl,fifo-depth = <15>;
512				status = "disabled";
513			};
514
515			audmux: audmux@83fd0000 {
516				compatible = "fsl,imx51-audmux", "fsl,imx31-audmux";
517				reg = <0x83fd0000 0x4000>;
518				clocks = <&clks IMX5_CLK_DUMMY>;
519				clock-names = "audmux";
520				status = "disabled";
521			};
522
523			weim: weim@83fda000 {
524				#address-cells = <2>;
525				#size-cells = <1>;
526				compatible = "fsl,imx51-weim";
527				reg = <0x83fda000 0x1000>;
528				clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>;
529				ranges = <
530					0 0 0xb0000000 0x08000000
531					1 0 0xb8000000 0x08000000
532					2 0 0xc0000000 0x08000000
533					3 0 0xc8000000 0x04000000
534					4 0 0xcc000000 0x02000000
535					5 0 0xce000000 0x02000000
536				>;
537				status = "disabled";
538			};
539
540			nfc: nand@83fdb000 {
541				#address-cells = <1>;
542				#size-cells = <1>;
543				compatible = "fsl,imx51-nand";
544				reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
545				interrupts = <8>;
546				clocks = <&clks IMX5_CLK_NFC_GATE>;
547				status = "disabled";
548			};
549
550			pata: pata@83fe0000 {
551				compatible = "fsl,imx51-pata", "fsl,imx27-pata";
552				reg = <0x83fe0000 0x4000>;
553				interrupts = <70>;
554				clocks = <&clks IMX5_CLK_PATA_GATE>;
555				status = "disabled";
556			};
557
558			ssi3: ssi@83fe8000 {
559				#sound-dai-cells = <0>;
560				compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
561				reg = <0x83fe8000 0x4000>;
562				interrupts = <96>;
563				clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
564				dmas = <&sdma 46 0 0>,
565				       <&sdma 47 0 0>;
566				dma-names = "rx", "tx";
567				fsl,fifo-depth = <15>;
568				status = "disabled";
569			};
570
571			fec: ethernet@83fec000 {
572				compatible = "fsl,imx51-fec", "fsl,imx27-fec";
573				reg = <0x83fec000 0x4000>;
574				interrupts = <87>;
575				clocks = <&clks IMX5_CLK_FEC_GATE>,
576				         <&clks IMX5_CLK_FEC_GATE>,
577				         <&clks IMX5_CLK_FEC_GATE>;
578				clock-names = "ipg", "ahb", "ptp";
579				status = "disabled";
580			};
581		};
582	};
583};
584