Lines Matching refs:clks
108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
206 <&clks IMX5_CLK_UART3_PER_GATE>;
217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
218 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
243 <&clks IMX5_CLK_DUMMY>,
244 <&clks IMX5_CLK_ESDHC3_PER_GATE>;
254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
255 <&clks IMX5_CLK_DUMMY>,
256 <&clks IMX5_CLK_ESDHC4_PER_GATE>;
270 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
277 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
286 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
296 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
306 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
315 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
324 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
371 clocks = <&clks IMX5_CLK_DUMMY>;
379 clocks = <&clks IMX5_CLK_DUMMY>;
386 clocks = <&clks IMX5_CLK_DUMMY>;
394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
395 <&clks IMX5_CLK_GPT_HF_GATE>;
415 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
416 <&clks IMX5_CLK_LDB_DI1_SEL>,
417 <&clks IMX5_CLK_IPU_DI0_SEL>,
418 <&clks IMX5_CLK_IPU_DI1_SEL>,
419 <&clks IMX5_CLK_LDB_DI0_GATE>,
420 <&clks IMX5_CLK_LDB_DI1_GATE>;
461 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
462 <&clks IMX5_CLK_PWM1_HF_GATE>;
471 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
472 <&clks IMX5_CLK_PWM2_HF_GATE>;
481 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
482 <&clks IMX5_CLK_UART1_PER_GATE>;
491 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
492 <&clks IMX5_CLK_UART2_PER_GATE>;
501 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
502 <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
511 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
512 <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
523 clks: ccm@53fd4000{ label
566 clocks = <&clks IMX5_CLK_I2C3_GATE>;
574 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
575 <&clks IMX5_CLK_UART4_PER_GATE>;
597 clocks = <&clks IMX5_CLK_IIM_GATE>;
604 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
605 <&clks IMX5_CLK_UART5_PER_GATE>;
613 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
623 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
624 <&clks IMX5_CLK_ECSPI2_PER_GATE>;
633 clocks = <&clks IMX5_CLK_SDMA_GATE>,
634 <&clks IMX5_CLK_SDMA_GATE>;
646 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
647 <&clks IMX5_CLK_CSPI_IPG_GATE>;
658 clocks = <&clks IMX5_CLK_I2C2_GATE>;
668 clocks = <&clks IMX5_CLK_I2C1_GATE>;
678 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
696 clocks = <&clks IMX5_CLK_NFC_GATE>;
706 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>;
718 clocks = <&clks IMX5_CLK_FEC_GATE>,
719 <&clks IMX5_CLK_FEC_GATE>,
720 <&clks IMX5_CLK_FEC_GATE>;
729 clocks = <&clks IMX5_CLK_TVE_GATE>,
730 <&clks IMX5_CLK_IPU_DI1_SEL>;
745 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
746 <&clks IMX5_CLK_VPU_GATE>;
756 clocks = <&clks IMX5_CLK_OCRAM>;