1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "skeleton.dtsi" 14#include "imx53-pinfunc.h" 15#include <dt-bindings/clock/imx5-clock.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/input/input.h> 18 19/ { 20 aliases { 21 ethernet0 = &fec; 22 gpio0 = &gpio1; 23 gpio1 = &gpio2; 24 gpio2 = &gpio3; 25 gpio3 = &gpio4; 26 gpio4 = &gpio5; 27 gpio5 = &gpio6; 28 gpio6 = &gpio7; 29 i2c0 = &i2c1; 30 i2c1 = &i2c2; 31 i2c2 = &i2c3; 32 mmc0 = &esdhc1; 33 mmc1 = &esdhc2; 34 mmc2 = &esdhc3; 35 mmc3 = &esdhc4; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 serial4 = &uart5; 41 spi0 = &ecspi1; 42 spi1 = &ecspi2; 43 spi2 = &cspi; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a8"; 52 reg = <0x0>; 53 }; 54 }; 55 56 display-subsystem { 57 compatible = "fsl,imx-display-subsystem"; 58 ports = <&ipu_di0>, <&ipu_di1>; 59 }; 60 61 tzic: tz-interrupt-controller@0fffc000 { 62 compatible = "fsl,imx53-tzic", "fsl,tzic"; 63 interrupt-controller; 64 #interrupt-cells = <1>; 65 reg = <0x0fffc000 0x4000>; 66 }; 67 68 clocks { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 ckil { 73 compatible = "fsl,imx-ckil", "fixed-clock"; 74 #clock-cells = <0>; 75 clock-frequency = <32768>; 76 }; 77 78 ckih1 { 79 compatible = "fsl,imx-ckih1", "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <22579200>; 82 }; 83 84 ckih2 { 85 compatible = "fsl,imx-ckih2", "fixed-clock"; 86 #clock-cells = <0>; 87 clock-frequency = <0>; 88 }; 89 90 osc { 91 compatible = "fsl,imx-osc", "fixed-clock"; 92 #clock-cells = <0>; 93 clock-frequency = <24000000>; 94 }; 95 }; 96 97 soc { 98 #address-cells = <1>; 99 #size-cells = <1>; 100 compatible = "simple-bus"; 101 interrupt-parent = <&tzic>; 102 ranges; 103 104 sata: sata@10000000 { 105 compatible = "fsl,imx53-ahci"; 106 reg = <0x10000000 0x1000>; 107 interrupts = <28>; 108 clocks = <&clks IMX5_CLK_SATA_GATE>, 109 <&clks IMX5_CLK_SATA_REF>, 110 <&clks IMX5_CLK_AHB>; 111 clock-names = "sata", "sata_ref", "ahb"; 112 status = "disabled"; 113 }; 114 115 ipu: ipu@18000000 { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 compatible = "fsl,imx53-ipu"; 119 reg = <0x18000000 0x08000000>; 120 interrupts = <11 10>; 121 clocks = <&clks IMX5_CLK_IPU_GATE>, 122 <&clks IMX5_CLK_IPU_DI0_GATE>, 123 <&clks IMX5_CLK_IPU_DI1_GATE>; 124 clock-names = "bus", "di0", "di1"; 125 resets = <&src 2>; 126 127 ipu_di0: port@2 { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 reg = <2>; 131 132 ipu_di0_disp0: endpoint@0 { 133 reg = <0>; 134 }; 135 136 ipu_di0_lvds0: endpoint@1 { 137 reg = <1>; 138 remote-endpoint = <&lvds0_in>; 139 }; 140 }; 141 142 ipu_di1: port@3 { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 reg = <3>; 146 147 ipu_di1_disp1: endpoint@0 { 148 reg = <0>; 149 }; 150 151 ipu_di1_lvds1: endpoint@1 { 152 reg = <1>; 153 remote-endpoint = <&lvds1_in>; 154 }; 155 156 ipu_di1_tve: endpoint@2 { 157 reg = <2>; 158 remote-endpoint = <&tve_in>; 159 }; 160 }; 161 }; 162 163 aips@50000000 { /* AIPS1 */ 164 compatible = "fsl,aips-bus", "simple-bus"; 165 #address-cells = <1>; 166 #size-cells = <1>; 167 reg = <0x50000000 0x10000000>; 168 ranges; 169 170 spba@50000000 { 171 compatible = "fsl,spba-bus", "simple-bus"; 172 #address-cells = <1>; 173 #size-cells = <1>; 174 reg = <0x50000000 0x40000>; 175 ranges; 176 177 esdhc1: esdhc@50004000 { 178 compatible = "fsl,imx53-esdhc"; 179 reg = <0x50004000 0x4000>; 180 interrupts = <1>; 181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 182 <&clks IMX5_CLK_DUMMY>, 183 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 184 clock-names = "ipg", "ahb", "per"; 185 bus-width = <4>; 186 status = "disabled"; 187 }; 188 189 esdhc2: esdhc@50008000 { 190 compatible = "fsl,imx53-esdhc"; 191 reg = <0x50008000 0x4000>; 192 interrupts = <2>; 193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 194 <&clks IMX5_CLK_DUMMY>, 195 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 196 clock-names = "ipg", "ahb", "per"; 197 bus-width = <4>; 198 status = "disabled"; 199 }; 200 201 uart3: serial@5000c000 { 202 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 203 reg = <0x5000c000 0x4000>; 204 interrupts = <33>; 205 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 206 <&clks IMX5_CLK_UART3_PER_GATE>; 207 clock-names = "ipg", "per"; 208 status = "disabled"; 209 }; 210 211 ecspi1: ecspi@50010000 { 212 #address-cells = <1>; 213 #size-cells = <0>; 214 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 215 reg = <0x50010000 0x4000>; 216 interrupts = <36>; 217 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 218 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 219 clock-names = "ipg", "per"; 220 status = "disabled"; 221 }; 222 223 ssi2: ssi@50014000 { 224 #sound-dai-cells = <0>; 225 compatible = "fsl,imx53-ssi", 226 "fsl,imx51-ssi", 227 "fsl,imx21-ssi"; 228 reg = <0x50014000 0x4000>; 229 interrupts = <30>; 230 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 231 dmas = <&sdma 24 1 0>, 232 <&sdma 25 1 0>; 233 dma-names = "rx", "tx"; 234 fsl,fifo-depth = <15>; 235 status = "disabled"; 236 }; 237 238 esdhc3: esdhc@50020000 { 239 compatible = "fsl,imx53-esdhc"; 240 reg = <0x50020000 0x4000>; 241 interrupts = <3>; 242 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 243 <&clks IMX5_CLK_DUMMY>, 244 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 245 clock-names = "ipg", "ahb", "per"; 246 bus-width = <4>; 247 status = "disabled"; 248 }; 249 250 esdhc4: esdhc@50024000 { 251 compatible = "fsl,imx53-esdhc"; 252 reg = <0x50024000 0x4000>; 253 interrupts = <4>; 254 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 255 <&clks IMX5_CLK_DUMMY>, 256 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 257 clock-names = "ipg", "ahb", "per"; 258 bus-width = <4>; 259 status = "disabled"; 260 }; 261 }; 262 263 aipstz1: bridge@53f00000 { 264 compatible = "fsl,imx53-aipstz"; 265 reg = <0x53f00000 0x60>; 266 }; 267 268 usbphy0: usbphy@0 { 269 compatible = "usb-nop-xceiv"; 270 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 271 clock-names = "main_clk"; 272 status = "okay"; 273 }; 274 275 usbphy1: usbphy@1 { 276 compatible = "usb-nop-xceiv"; 277 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 278 clock-names = "main_clk"; 279 status = "okay"; 280 }; 281 282 usbotg: usb@53f80000 { 283 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 284 reg = <0x53f80000 0x0200>; 285 interrupts = <18>; 286 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 287 fsl,usbmisc = <&usbmisc 0>; 288 fsl,usbphy = <&usbphy0>; 289 status = "disabled"; 290 }; 291 292 usbh1: usb@53f80200 { 293 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 294 reg = <0x53f80200 0x0200>; 295 interrupts = <14>; 296 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 297 fsl,usbmisc = <&usbmisc 1>; 298 fsl,usbphy = <&usbphy1>; 299 status = "disabled"; 300 }; 301 302 usbh2: usb@53f80400 { 303 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 304 reg = <0x53f80400 0x0200>; 305 interrupts = <16>; 306 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 307 fsl,usbmisc = <&usbmisc 2>; 308 status = "disabled"; 309 }; 310 311 usbh3: usb@53f80600 { 312 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 313 reg = <0x53f80600 0x0200>; 314 interrupts = <17>; 315 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 316 fsl,usbmisc = <&usbmisc 3>; 317 status = "disabled"; 318 }; 319 320 usbmisc: usbmisc@53f80800 { 321 #index-cells = <1>; 322 compatible = "fsl,imx53-usbmisc"; 323 reg = <0x53f80800 0x200>; 324 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 325 }; 326 327 gpio1: gpio@53f84000 { 328 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 329 reg = <0x53f84000 0x4000>; 330 interrupts = <50 51>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 }; 336 337 gpio2: gpio@53f88000 { 338 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 339 reg = <0x53f88000 0x4000>; 340 interrupts = <52 53>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 interrupt-controller; 344 #interrupt-cells = <2>; 345 }; 346 347 gpio3: gpio@53f8c000 { 348 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 349 reg = <0x53f8c000 0x4000>; 350 interrupts = <54 55>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 interrupt-controller; 354 #interrupt-cells = <2>; 355 }; 356 357 gpio4: gpio@53f90000 { 358 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 359 reg = <0x53f90000 0x4000>; 360 interrupts = <56 57>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 interrupt-controller; 364 #interrupt-cells = <2>; 365 }; 366 367 kpp: kpp@53f94000 { 368 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; 369 reg = <0x53f94000 0x4000>; 370 interrupts = <60>; 371 clocks = <&clks IMX5_CLK_DUMMY>; 372 status = "disabled"; 373 }; 374 375 wdog1: wdog@53f98000 { 376 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 377 reg = <0x53f98000 0x4000>; 378 interrupts = <58>; 379 clocks = <&clks IMX5_CLK_DUMMY>; 380 }; 381 382 wdog2: wdog@53f9c000 { 383 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 384 reg = <0x53f9c000 0x4000>; 385 interrupts = <59>; 386 clocks = <&clks IMX5_CLK_DUMMY>; 387 status = "disabled"; 388 }; 389 390 gpt: timer@53fa0000 { 391 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 392 reg = <0x53fa0000 0x4000>; 393 interrupts = <39>; 394 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 395 <&clks IMX5_CLK_GPT_HF_GATE>; 396 clock-names = "ipg", "per"; 397 }; 398 399 iomuxc: iomuxc@53fa8000 { 400 compatible = "fsl,imx53-iomuxc"; 401 reg = <0x53fa8000 0x4000>; 402 }; 403 404 gpr: iomuxc-gpr@53fa8000 { 405 compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 406 reg = <0x53fa8000 0xc>; 407 }; 408 409 ldb: ldb@53fa8008 { 410 #address-cells = <1>; 411 #size-cells = <0>; 412 compatible = "fsl,imx53-ldb"; 413 reg = <0x53fa8008 0x4>; 414 gpr = <&gpr>; 415 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 416 <&clks IMX5_CLK_LDB_DI1_SEL>, 417 <&clks IMX5_CLK_IPU_DI0_SEL>, 418 <&clks IMX5_CLK_IPU_DI1_SEL>, 419 <&clks IMX5_CLK_LDB_DI0_GATE>, 420 <&clks IMX5_CLK_LDB_DI1_GATE>; 421 clock-names = "di0_pll", "di1_pll", 422 "di0_sel", "di1_sel", 423 "di0", "di1"; 424 status = "disabled"; 425 426 lvds-channel@0 { 427 #address-cells = <1>; 428 #size-cells = <0>; 429 reg = <0>; 430 status = "disabled"; 431 432 port@0 { 433 reg = <0>; 434 435 lvds0_in: endpoint { 436 remote-endpoint = <&ipu_di0_lvds0>; 437 }; 438 }; 439 }; 440 441 lvds-channel@1 { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 reg = <1>; 445 status = "disabled"; 446 447 port@1 { 448 reg = <1>; 449 450 lvds1_in: endpoint { 451 remote-endpoint = <&ipu_di1_lvds1>; 452 }; 453 }; 454 }; 455 }; 456 457 pwm1: pwm@53fb4000 { 458 #pwm-cells = <2>; 459 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 460 reg = <0x53fb4000 0x4000>; 461 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 462 <&clks IMX5_CLK_PWM1_HF_GATE>; 463 clock-names = "ipg", "per"; 464 interrupts = <61>; 465 }; 466 467 pwm2: pwm@53fb8000 { 468 #pwm-cells = <2>; 469 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 470 reg = <0x53fb8000 0x4000>; 471 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 472 <&clks IMX5_CLK_PWM2_HF_GATE>; 473 clock-names = "ipg", "per"; 474 interrupts = <94>; 475 }; 476 477 uart1: serial@53fbc000 { 478 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 479 reg = <0x53fbc000 0x4000>; 480 interrupts = <31>; 481 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 482 <&clks IMX5_CLK_UART1_PER_GATE>; 483 clock-names = "ipg", "per"; 484 status = "disabled"; 485 }; 486 487 uart2: serial@53fc0000 { 488 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 489 reg = <0x53fc0000 0x4000>; 490 interrupts = <32>; 491 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 492 <&clks IMX5_CLK_UART2_PER_GATE>; 493 clock-names = "ipg", "per"; 494 status = "disabled"; 495 }; 496 497 can1: can@53fc8000 { 498 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 499 reg = <0x53fc8000 0x4000>; 500 interrupts = <82>; 501 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, 502 <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 503 clock-names = "ipg", "per"; 504 status = "disabled"; 505 }; 506 507 can2: can@53fcc000 { 508 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan"; 509 reg = <0x53fcc000 0x4000>; 510 interrupts = <83>; 511 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, 512 <&clks IMX5_CLK_CAN2_SERIAL_GATE>; 513 clock-names = "ipg", "per"; 514 status = "disabled"; 515 }; 516 517 src: src@53fd0000 { 518 compatible = "fsl,imx53-src", "fsl,imx51-src"; 519 reg = <0x53fd0000 0x4000>; 520 #reset-cells = <1>; 521 }; 522 523 clks: ccm@53fd4000{ 524 compatible = "fsl,imx53-ccm"; 525 reg = <0x53fd4000 0x4000>; 526 interrupts = <0 71 0x04 0 72 0x04>; 527 #clock-cells = <1>; 528 }; 529 530 gpio5: gpio@53fdc000 { 531 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 532 reg = <0x53fdc000 0x4000>; 533 interrupts = <103 104>; 534 gpio-controller; 535 #gpio-cells = <2>; 536 interrupt-controller; 537 #interrupt-cells = <2>; 538 }; 539 540 gpio6: gpio@53fe0000 { 541 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 542 reg = <0x53fe0000 0x4000>; 543 interrupts = <105 106>; 544 gpio-controller; 545 #gpio-cells = <2>; 546 interrupt-controller; 547 #interrupt-cells = <2>; 548 }; 549 550 gpio7: gpio@53fe4000 { 551 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 552 reg = <0x53fe4000 0x4000>; 553 interrupts = <107 108>; 554 gpio-controller; 555 #gpio-cells = <2>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 560 i2c3: i2c@53fec000 { 561 #address-cells = <1>; 562 #size-cells = <0>; 563 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 564 reg = <0x53fec000 0x4000>; 565 interrupts = <64>; 566 clocks = <&clks IMX5_CLK_I2C3_GATE>; 567 status = "disabled"; 568 }; 569 570 uart4: serial@53ff0000 { 571 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 572 reg = <0x53ff0000 0x4000>; 573 interrupts = <13>; 574 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, 575 <&clks IMX5_CLK_UART4_PER_GATE>; 576 clock-names = "ipg", "per"; 577 status = "disabled"; 578 }; 579 }; 580 581 aips@60000000 { /* AIPS2 */ 582 compatible = "fsl,aips-bus", "simple-bus"; 583 #address-cells = <1>; 584 #size-cells = <1>; 585 reg = <0x60000000 0x10000000>; 586 ranges; 587 588 aipstz2: bridge@63f00000 { 589 compatible = "fsl,imx53-aipstz"; 590 reg = <0x63f00000 0x60>; 591 }; 592 593 iim: iim@63f98000 { 594 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 595 reg = <0x63f98000 0x4000>; 596 interrupts = <69>; 597 clocks = <&clks IMX5_CLK_IIM_GATE>; 598 }; 599 600 uart5: serial@63f90000 { 601 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 602 reg = <0x63f90000 0x4000>; 603 interrupts = <86>; 604 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, 605 <&clks IMX5_CLK_UART5_PER_GATE>; 606 clock-names = "ipg", "per"; 607 status = "disabled"; 608 }; 609 610 owire: owire@63fa4000 { 611 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 612 reg = <0x63fa4000 0x4000>; 613 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 614 status = "disabled"; 615 }; 616 617 ecspi2: ecspi@63fac000 { 618 #address-cells = <1>; 619 #size-cells = <0>; 620 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 621 reg = <0x63fac000 0x4000>; 622 interrupts = <37>; 623 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 624 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 625 clock-names = "ipg", "per"; 626 status = "disabled"; 627 }; 628 629 sdma: sdma@63fb0000 { 630 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 631 reg = <0x63fb0000 0x4000>; 632 interrupts = <6>; 633 clocks = <&clks IMX5_CLK_SDMA_GATE>, 634 <&clks IMX5_CLK_SDMA_GATE>; 635 clock-names = "ipg", "ahb"; 636 #dma-cells = <3>; 637 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 638 }; 639 640 cspi: cspi@63fc0000 { 641 #address-cells = <1>; 642 #size-cells = <0>; 643 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 644 reg = <0x63fc0000 0x4000>; 645 interrupts = <38>; 646 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 647 <&clks IMX5_CLK_CSPI_IPG_GATE>; 648 clock-names = "ipg", "per"; 649 status = "disabled"; 650 }; 651 652 i2c2: i2c@63fc4000 { 653 #address-cells = <1>; 654 #size-cells = <0>; 655 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 656 reg = <0x63fc4000 0x4000>; 657 interrupts = <63>; 658 clocks = <&clks IMX5_CLK_I2C2_GATE>; 659 status = "disabled"; 660 }; 661 662 i2c1: i2c@63fc8000 { 663 #address-cells = <1>; 664 #size-cells = <0>; 665 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 666 reg = <0x63fc8000 0x4000>; 667 interrupts = <62>; 668 clocks = <&clks IMX5_CLK_I2C1_GATE>; 669 status = "disabled"; 670 }; 671 672 ssi1: ssi@63fcc000 { 673 #sound-dai-cells = <0>; 674 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 675 "fsl,imx21-ssi"; 676 reg = <0x63fcc000 0x4000>; 677 interrupts = <29>; 678 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 679 dmas = <&sdma 28 0 0>, 680 <&sdma 29 0 0>; 681 dma-names = "rx", "tx"; 682 fsl,fifo-depth = <15>; 683 status = "disabled"; 684 }; 685 686 audmux: audmux@63fd0000 { 687 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 688 reg = <0x63fd0000 0x4000>; 689 status = "disabled"; 690 }; 691 692 nfc: nand@63fdb000 { 693 compatible = "fsl,imx53-nand"; 694 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 695 interrupts = <8>; 696 clocks = <&clks IMX5_CLK_NFC_GATE>; 697 status = "disabled"; 698 }; 699 700 ssi3: ssi@63fe8000 { 701 #sound-dai-cells = <0>; 702 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 703 "fsl,imx21-ssi"; 704 reg = <0x63fe8000 0x4000>; 705 interrupts = <96>; 706 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; 707 dmas = <&sdma 46 0 0>, 708 <&sdma 47 0 0>; 709 dma-names = "rx", "tx"; 710 fsl,fifo-depth = <15>; 711 status = "disabled"; 712 }; 713 714 fec: ethernet@63fec000 { 715 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 716 reg = <0x63fec000 0x4000>; 717 interrupts = <87>; 718 clocks = <&clks IMX5_CLK_FEC_GATE>, 719 <&clks IMX5_CLK_FEC_GATE>, 720 <&clks IMX5_CLK_FEC_GATE>; 721 clock-names = "ipg", "ahb", "ptp"; 722 status = "disabled"; 723 }; 724 725 tve: tve@63ff0000 { 726 compatible = "fsl,imx53-tve"; 727 reg = <0x63ff0000 0x1000>; 728 interrupts = <92>; 729 clocks = <&clks IMX5_CLK_TVE_GATE>, 730 <&clks IMX5_CLK_IPU_DI1_SEL>; 731 clock-names = "tve", "di_sel"; 732 status = "disabled"; 733 734 port { 735 tve_in: endpoint { 736 remote-endpoint = <&ipu_di1_tve>; 737 }; 738 }; 739 }; 740 741 vpu: vpu@63ff4000 { 742 compatible = "fsl,imx53-vpu"; 743 reg = <0x63ff4000 0x1000>; 744 interrupts = <9>; 745 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 746 <&clks IMX5_CLK_VPU_GATE>; 747 clock-names = "per", "ahb"; 748 resets = <&src 1>; 749 iram = <&ocram>; 750 }; 751 }; 752 753 ocram: sram@f8000000 { 754 compatible = "mmio-sram"; 755 reg = <0xf8000000 0x20000>; 756 clocks = <&clks IMX5_CLK_OCRAM>; 757 }; 758 759 pmu { 760 compatible = "arm,cortex-a8-pmu"; 761 interrupts = <77>; 762 }; 763 }; 764}; 765