252 	u32 rb_cntl, reg_offset;  in cik_sdma_gfx_stop()  local
261 			reg_offset = SDMA0_REGISTER_OFFSET;  in cik_sdma_gfx_stop()
263 			reg_offset = SDMA1_REGISTER_OFFSET;  in cik_sdma_gfx_stop()
264 		rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);  in cik_sdma_gfx_stop()
266 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);  in cik_sdma_gfx_stop()
267 		WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);  in cik_sdma_gfx_stop()
306 	u32 me_cntl, reg_offset;  in cik_sdma_enable()  local
316 			reg_offset = SDMA0_REGISTER_OFFSET;  in cik_sdma_enable()
318 			reg_offset = SDMA1_REGISTER_OFFSET;  in cik_sdma_enable()
319 		me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);  in cik_sdma_enable()
324 		WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);  in cik_sdma_enable()
341 	u32 reg_offset, wb_offset;  in cik_sdma_gfx_resume()  local
347 			reg_offset = SDMA0_REGISTER_OFFSET;  in cik_sdma_gfx_resume()
351 			reg_offset = SDMA1_REGISTER_OFFSET;  in cik_sdma_gfx_resume()
355 		WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);  in cik_sdma_gfx_resume()
356 		WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);  in cik_sdma_gfx_resume()
364 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);  in cik_sdma_gfx_resume()
367 		WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);  in cik_sdma_gfx_resume()
368 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);  in cik_sdma_gfx_resume()
371 		WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,  in cik_sdma_gfx_resume()
373 		WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,  in cik_sdma_gfx_resume()
379 		WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);  in cik_sdma_gfx_resume()
380 		WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);  in cik_sdma_gfx_resume()
383 		WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);  in cik_sdma_gfx_resume()
386 		WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);  in cik_sdma_gfx_resume()
393 		WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);  in cik_sdma_gfx_resume()