1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <drm/drmP.h>
26 #include "radeon.h"
27 #include "radeon_ucode.h"
28 #include "radeon_asic.h"
29 #include "radeon_trace.h"
30 #include "cikd.h"
31
32 /* sdma */
33 #define CIK_SDMA_UCODE_SIZE 1050
34 #define CIK_SDMA_UCODE_VERSION 64
35
36 u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
37
38 /*
39 * sDMA - System DMA
40 * Starting with CIK, the GPU has new asynchronous
41 * DMA engines. These engines are used for compute
42 * and gfx. There are two DMA engines (SDMA0, SDMA1)
43 * and each one supports 1 ring buffer used for gfx
44 * and 2 queues used for compute.
45 *
46 * The programming model is very similar to the CP
47 * (ring buffer, IBs, etc.), but sDMA has it's own
48 * packet format that is different from the PM4 format
49 * used by the CP. sDMA supports copying data, writing
50 * embedded data, solid fills, and a number of other
51 * things. It also has support for tiling/detiling of
52 * buffers.
53 */
54
55 /**
56 * cik_sdma_get_rptr - get the current read pointer
57 *
58 * @rdev: radeon_device pointer
59 * @ring: radeon ring pointer
60 *
61 * Get the current rptr from the hardware (CIK+).
62 */
cik_sdma_get_rptr(struct radeon_device * rdev,struct radeon_ring * ring)63 uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
64 struct radeon_ring *ring)
65 {
66 u32 rptr, reg;
67
68 if (rdev->wb.enabled) {
69 rptr = rdev->wb.wb[ring->rptr_offs/4];
70 } else {
71 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
72 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
73 else
74 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
75
76 rptr = RREG32(reg);
77 }
78
79 return (rptr & 0x3fffc) >> 2;
80 }
81
82 /**
83 * cik_sdma_get_wptr - get the current write pointer
84 *
85 * @rdev: radeon_device pointer
86 * @ring: radeon ring pointer
87 *
88 * Get the current wptr from the hardware (CIK+).
89 */
cik_sdma_get_wptr(struct radeon_device * rdev,struct radeon_ring * ring)90 uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
91 struct radeon_ring *ring)
92 {
93 u32 reg;
94
95 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
96 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
97 else
98 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
99
100 return (RREG32(reg) & 0x3fffc) >> 2;
101 }
102
103 /**
104 * cik_sdma_set_wptr - commit the write pointer
105 *
106 * @rdev: radeon_device pointer
107 * @ring: radeon ring pointer
108 *
109 * Write the wptr back to the hardware (CIK+).
110 */
cik_sdma_set_wptr(struct radeon_device * rdev,struct radeon_ring * ring)111 void cik_sdma_set_wptr(struct radeon_device *rdev,
112 struct radeon_ring *ring)
113 {
114 u32 reg;
115
116 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
117 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
118 else
119 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
120
121 WREG32(reg, (ring->wptr << 2) & 0x3fffc);
122 (void)RREG32(reg);
123 }
124
125 /**
126 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
127 *
128 * @rdev: radeon_device pointer
129 * @ib: IB object to schedule
130 *
131 * Schedule an IB in the DMA ring (CIK).
132 */
cik_sdma_ring_ib_execute(struct radeon_device * rdev,struct radeon_ib * ib)133 void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
134 struct radeon_ib *ib)
135 {
136 struct radeon_ring *ring = &rdev->ring[ib->ring];
137 u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf;
138
139 if (rdev->wb.enabled) {
140 u32 next_rptr = ring->wptr + 5;
141 while ((next_rptr & 7) != 4)
142 next_rptr++;
143 next_rptr += 4;
144 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
145 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
146 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
147 radeon_ring_write(ring, 1); /* number of DWs to follow */
148 radeon_ring_write(ring, next_rptr);
149 }
150
151 /* IB packet must end on a 8 DW boundary */
152 while ((ring->wptr & 7) != 4)
153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
154 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
155 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
156 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
157 radeon_ring_write(ring, ib->length_dw);
158
159 }
160
161 /**
162 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
163 *
164 * @rdev: radeon_device pointer
165 * @ridx: radeon ring index
166 *
167 * Emit an hdp flush packet on the requested DMA ring.
168 */
cik_sdma_hdp_flush_ring_emit(struct radeon_device * rdev,int ridx)169 static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
170 int ridx)
171 {
172 struct radeon_ring *ring = &rdev->ring[ridx];
173 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
174 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
175 u32 ref_and_mask;
176
177 if (ridx == R600_RING_TYPE_DMA_INDEX)
178 ref_and_mask = SDMA0;
179 else
180 ref_and_mask = SDMA1;
181
182 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
183 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
184 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
185 radeon_ring_write(ring, ref_and_mask); /* reference */
186 radeon_ring_write(ring, ref_and_mask); /* mask */
187 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
188 }
189
190 /**
191 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
192 *
193 * @rdev: radeon_device pointer
194 * @fence: radeon fence object
195 *
196 * Add a DMA fence packet to the ring to write
197 * the fence seq number and DMA trap packet to generate
198 * an interrupt if needed (CIK).
199 */
cik_sdma_fence_ring_emit(struct radeon_device * rdev,struct radeon_fence * fence)200 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
201 struct radeon_fence *fence)
202 {
203 struct radeon_ring *ring = &rdev->ring[fence->ring];
204 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
205
206 /* write the fence */
207 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
208 radeon_ring_write(ring, lower_32_bits(addr));
209 radeon_ring_write(ring, upper_32_bits(addr));
210 radeon_ring_write(ring, fence->seq);
211 /* generate an interrupt */
212 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
213 /* flush HDP */
214 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
215 }
216
217 /**
218 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
219 *
220 * @rdev: radeon_device pointer
221 * @ring: radeon_ring structure holding ring information
222 * @semaphore: radeon semaphore object
223 * @emit_wait: wait or signal semaphore
224 *
225 * Add a DMA semaphore packet to the ring wait on or signal
226 * other rings (CIK).
227 */
cik_sdma_semaphore_ring_emit(struct radeon_device * rdev,struct radeon_ring * ring,struct radeon_semaphore * semaphore,bool emit_wait)228 bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
229 struct radeon_ring *ring,
230 struct radeon_semaphore *semaphore,
231 bool emit_wait)
232 {
233 u64 addr = semaphore->gpu_addr;
234 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
235
236 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
237 radeon_ring_write(ring, addr & 0xfffffff8);
238 radeon_ring_write(ring, upper_32_bits(addr));
239
240 return true;
241 }
242
243 /**
244 * cik_sdma_gfx_stop - stop the gfx async dma engines
245 *
246 * @rdev: radeon_device pointer
247 *
248 * Stop the gfx async dma ring buffers (CIK).
249 */
cik_sdma_gfx_stop(struct radeon_device * rdev)250 static void cik_sdma_gfx_stop(struct radeon_device *rdev)
251 {
252 u32 rb_cntl, reg_offset;
253 int i;
254
255 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
256 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
257 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
258
259 for (i = 0; i < 2; i++) {
260 if (i == 0)
261 reg_offset = SDMA0_REGISTER_OFFSET;
262 else
263 reg_offset = SDMA1_REGISTER_OFFSET;
264 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
265 rb_cntl &= ~SDMA_RB_ENABLE;
266 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
267 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
268 }
269 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;
270 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;
271
272 /* FIXME use something else than big hammer but after few days can not
273 * seem to find good combination so reset SDMA blocks as it seems we
274 * do not shut them down properly. This fix hibernation and does not
275 * affect suspend to ram.
276 */
277 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
278 (void)RREG32(SRBM_SOFT_RESET);
279 udelay(50);
280 WREG32(SRBM_SOFT_RESET, 0);
281 (void)RREG32(SRBM_SOFT_RESET);
282 }
283
284 /**
285 * cik_sdma_rlc_stop - stop the compute async dma engines
286 *
287 * @rdev: radeon_device pointer
288 *
289 * Stop the compute async dma queues (CIK).
290 */
cik_sdma_rlc_stop(struct radeon_device * rdev)291 static void cik_sdma_rlc_stop(struct radeon_device *rdev)
292 {
293 /* XXX todo */
294 }
295
296 /**
297 * cik_sdma_enable - stop the async dma engines
298 *
299 * @rdev: radeon_device pointer
300 * @enable: enable/disable the DMA MEs.
301 *
302 * Halt or unhalt the async dma engines (CIK).
303 */
cik_sdma_enable(struct radeon_device * rdev,bool enable)304 void cik_sdma_enable(struct radeon_device *rdev, bool enable)
305 {
306 u32 me_cntl, reg_offset;
307 int i;
308
309 if (enable == false) {
310 cik_sdma_gfx_stop(rdev);
311 cik_sdma_rlc_stop(rdev);
312 }
313
314 for (i = 0; i < 2; i++) {
315 if (i == 0)
316 reg_offset = SDMA0_REGISTER_OFFSET;
317 else
318 reg_offset = SDMA1_REGISTER_OFFSET;
319 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
320 if (enable)
321 me_cntl &= ~SDMA_HALT;
322 else
323 me_cntl |= SDMA_HALT;
324 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
325 }
326 }
327
328 /**
329 * cik_sdma_gfx_resume - setup and start the async dma engines
330 *
331 * @rdev: radeon_device pointer
332 *
333 * Set up the gfx DMA ring buffers and enable them (CIK).
334 * Returns 0 for success, error for failure.
335 */
cik_sdma_gfx_resume(struct radeon_device * rdev)336 static int cik_sdma_gfx_resume(struct radeon_device *rdev)
337 {
338 struct radeon_ring *ring;
339 u32 rb_cntl, ib_cntl;
340 u32 rb_bufsz;
341 u32 reg_offset, wb_offset;
342 int i, r;
343
344 for (i = 0; i < 2; i++) {
345 if (i == 0) {
346 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
347 reg_offset = SDMA0_REGISTER_OFFSET;
348 wb_offset = R600_WB_DMA_RPTR_OFFSET;
349 } else {
350 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
351 reg_offset = SDMA1_REGISTER_OFFSET;
352 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
353 }
354
355 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
356 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
357
358 /* Set ring buffer size in dwords */
359 rb_bufsz = order_base_2(ring->ring_size / 4);
360 rb_cntl = rb_bufsz << 1;
361 #ifdef __BIG_ENDIAN
362 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
363 #endif
364 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
365
366 /* Initialize the ring buffer's read and write pointers */
367 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
368 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
369
370 /* set the wb address whether it's enabled or not */
371 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
372 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
373 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
374 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
375
376 if (rdev->wb.enabled)
377 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
378
379 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
380 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
381
382 ring->wptr = 0;
383 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
384
385 /* enable DMA RB */
386 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
387
388 ib_cntl = SDMA_IB_ENABLE;
389 #ifdef __BIG_ENDIAN
390 ib_cntl |= SDMA_IB_SWAP_ENABLE;
391 #endif
392 /* enable DMA IBs */
393 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
394
395 ring->ready = true;
396
397 r = radeon_ring_test(rdev, ring->idx, ring);
398 if (r) {
399 ring->ready = false;
400 return r;
401 }
402 }
403
404 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
405 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
406 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
407
408 return 0;
409 }
410
411 /**
412 * cik_sdma_rlc_resume - setup and start the async dma engines
413 *
414 * @rdev: radeon_device pointer
415 *
416 * Set up the compute DMA queues and enable them (CIK).
417 * Returns 0 for success, error for failure.
418 */
cik_sdma_rlc_resume(struct radeon_device * rdev)419 static int cik_sdma_rlc_resume(struct radeon_device *rdev)
420 {
421 /* XXX todo */
422 return 0;
423 }
424
425 /**
426 * cik_sdma_load_microcode - load the sDMA ME ucode
427 *
428 * @rdev: radeon_device pointer
429 *
430 * Loads the sDMA0/1 ucode.
431 * Returns 0 for success, -EINVAL if the ucode is not available.
432 */
cik_sdma_load_microcode(struct radeon_device * rdev)433 static int cik_sdma_load_microcode(struct radeon_device *rdev)
434 {
435 int i;
436
437 if (!rdev->sdma_fw)
438 return -EINVAL;
439
440 /* halt the MEs */
441 cik_sdma_enable(rdev, false);
442
443 if (rdev->new_fw) {
444 const struct sdma_firmware_header_v1_0 *hdr =
445 (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;
446 const __le32 *fw_data;
447 u32 fw_size;
448
449 radeon_ucode_print_sdma_hdr(&hdr->header);
450
451 /* sdma0 */
452 fw_data = (const __le32 *)
453 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
454 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
455 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
456 for (i = 0; i < fw_size; i++)
457 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));
458 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
459
460 /* sdma1 */
461 fw_data = (const __le32 *)
462 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
463 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
464 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
465 for (i = 0; i < fw_size; i++)
466 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));
467 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
468 } else {
469 const __be32 *fw_data;
470
471 /* sdma0 */
472 fw_data = (const __be32 *)rdev->sdma_fw->data;
473 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
474 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
475 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
476 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
477
478 /* sdma1 */
479 fw_data = (const __be32 *)rdev->sdma_fw->data;
480 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
481 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
482 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
483 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
484 }
485
486 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
487 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
488 return 0;
489 }
490
491 /**
492 * cik_sdma_resume - setup and start the async dma engines
493 *
494 * @rdev: radeon_device pointer
495 *
496 * Set up the DMA engines and enable them (CIK).
497 * Returns 0 for success, error for failure.
498 */
cik_sdma_resume(struct radeon_device * rdev)499 int cik_sdma_resume(struct radeon_device *rdev)
500 {
501 int r;
502
503 r = cik_sdma_load_microcode(rdev);
504 if (r)
505 return r;
506
507 /* unhalt the MEs */
508 cik_sdma_enable(rdev, true);
509
510 /* start the gfx rings and rlc compute queues */
511 r = cik_sdma_gfx_resume(rdev);
512 if (r)
513 return r;
514 r = cik_sdma_rlc_resume(rdev);
515 if (r)
516 return r;
517
518 return 0;
519 }
520
521 /**
522 * cik_sdma_fini - tear down the async dma engines
523 *
524 * @rdev: radeon_device pointer
525 *
526 * Stop the async dma engines and free the rings (CIK).
527 */
cik_sdma_fini(struct radeon_device * rdev)528 void cik_sdma_fini(struct radeon_device *rdev)
529 {
530 /* halt the MEs */
531 cik_sdma_enable(rdev, false);
532 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
533 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
534 /* XXX - compute dma queue tear down */
535 }
536
537 /**
538 * cik_copy_dma - copy pages using the DMA engine
539 *
540 * @rdev: radeon_device pointer
541 * @src_offset: src GPU address
542 * @dst_offset: dst GPU address
543 * @num_gpu_pages: number of GPU pages to xfer
544 * @resv: reservation object to sync to
545 *
546 * Copy GPU paging using the DMA engine (CIK).
547 * Used by the radeon ttm implementation to move pages if
548 * registered as the asic copy callback.
549 */
cik_copy_dma(struct radeon_device * rdev,uint64_t src_offset,uint64_t dst_offset,unsigned num_gpu_pages,struct reservation_object * resv)550 struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
551 uint64_t src_offset, uint64_t dst_offset,
552 unsigned num_gpu_pages,
553 struct reservation_object *resv)
554 {
555 struct radeon_semaphore *sem = NULL;
556 struct radeon_fence *fence;
557 int ring_index = rdev->asic->copy.dma_ring_index;
558 struct radeon_ring *ring = &rdev->ring[ring_index];
559 u32 size_in_bytes, cur_size_in_bytes;
560 int i, num_loops;
561 int r = 0;
562
563 r = radeon_semaphore_create(rdev, &sem);
564 if (r) {
565 DRM_ERROR("radeon: moving bo (%d).\n", r);
566 return ERR_PTR(r);
567 }
568
569 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
570 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
571 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
572 if (r) {
573 DRM_ERROR("radeon: moving bo (%d).\n", r);
574 radeon_semaphore_free(rdev, &sem, NULL);
575 return ERR_PTR(r);
576 }
577
578 radeon_semaphore_sync_resv(rdev, sem, resv, false);
579 radeon_semaphore_sync_rings(rdev, sem, ring->idx);
580
581 for (i = 0; i < num_loops; i++) {
582 cur_size_in_bytes = size_in_bytes;
583 if (cur_size_in_bytes > 0x1fffff)
584 cur_size_in_bytes = 0x1fffff;
585 size_in_bytes -= cur_size_in_bytes;
586 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
587 radeon_ring_write(ring, cur_size_in_bytes);
588 radeon_ring_write(ring, 0); /* src/dst endian swap */
589 radeon_ring_write(ring, lower_32_bits(src_offset));
590 radeon_ring_write(ring, upper_32_bits(src_offset));
591 radeon_ring_write(ring, lower_32_bits(dst_offset));
592 radeon_ring_write(ring, upper_32_bits(dst_offset));
593 src_offset += cur_size_in_bytes;
594 dst_offset += cur_size_in_bytes;
595 }
596
597 r = radeon_fence_emit(rdev, &fence, ring->idx);
598 if (r) {
599 radeon_ring_unlock_undo(rdev, ring);
600 radeon_semaphore_free(rdev, &sem, NULL);
601 return ERR_PTR(r);
602 }
603
604 radeon_ring_unlock_commit(rdev, ring, false);
605 radeon_semaphore_free(rdev, &sem, fence);
606
607 return fence;
608 }
609
610 /**
611 * cik_sdma_ring_test - simple async dma engine test
612 *
613 * @rdev: radeon_device pointer
614 * @ring: radeon_ring structure holding ring information
615 *
616 * Test the DMA engine by writing using it to write an
617 * value to memory. (CIK).
618 * Returns 0 for success, error for failure.
619 */
cik_sdma_ring_test(struct radeon_device * rdev,struct radeon_ring * ring)620 int cik_sdma_ring_test(struct radeon_device *rdev,
621 struct radeon_ring *ring)
622 {
623 unsigned i;
624 int r;
625 unsigned index;
626 u32 tmp;
627 u64 gpu_addr;
628
629 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
630 index = R600_WB_DMA_RING_TEST_OFFSET;
631 else
632 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
633
634 gpu_addr = rdev->wb.gpu_addr + index;
635
636 tmp = 0xCAFEDEAD;
637 rdev->wb.wb[index/4] = cpu_to_le32(tmp);
638
639 r = radeon_ring_lock(rdev, ring, 5);
640 if (r) {
641 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
642 return r;
643 }
644 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
645 radeon_ring_write(ring, lower_32_bits(gpu_addr));
646 radeon_ring_write(ring, upper_32_bits(gpu_addr));
647 radeon_ring_write(ring, 1); /* number of DWs to follow */
648 radeon_ring_write(ring, 0xDEADBEEF);
649 radeon_ring_unlock_commit(rdev, ring, false);
650
651 for (i = 0; i < rdev->usec_timeout; i++) {
652 tmp = le32_to_cpu(rdev->wb.wb[index/4]);
653 if (tmp == 0xDEADBEEF)
654 break;
655 DRM_UDELAY(1);
656 }
657
658 if (i < rdev->usec_timeout) {
659 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
660 } else {
661 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
662 ring->idx, tmp);
663 r = -EINVAL;
664 }
665 return r;
666 }
667
668 /**
669 * cik_sdma_ib_test - test an IB on the DMA engine
670 *
671 * @rdev: radeon_device pointer
672 * @ring: radeon_ring structure holding ring information
673 *
674 * Test a simple IB in the DMA ring (CIK).
675 * Returns 0 on success, error on failure.
676 */
cik_sdma_ib_test(struct radeon_device * rdev,struct radeon_ring * ring)677 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
678 {
679 struct radeon_ib ib;
680 unsigned i;
681 unsigned index;
682 int r;
683 u32 tmp = 0;
684 u64 gpu_addr;
685
686 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
687 index = R600_WB_DMA_RING_TEST_OFFSET;
688 else
689 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;
690
691 gpu_addr = rdev->wb.gpu_addr + index;
692
693 tmp = 0xCAFEDEAD;
694 rdev->wb.wb[index/4] = cpu_to_le32(tmp);
695
696 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
697 if (r) {
698 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
699 return r;
700 }
701
702 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
703 ib.ptr[1] = lower_32_bits(gpu_addr);
704 ib.ptr[2] = upper_32_bits(gpu_addr);
705 ib.ptr[3] = 1;
706 ib.ptr[4] = 0xDEADBEEF;
707 ib.length_dw = 5;
708
709 r = radeon_ib_schedule(rdev, &ib, NULL, false);
710 if (r) {
711 radeon_ib_free(rdev, &ib);
712 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
713 return r;
714 }
715 r = radeon_fence_wait(ib.fence, false);
716 if (r) {
717 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
718 return r;
719 }
720 for (i = 0; i < rdev->usec_timeout; i++) {
721 tmp = le32_to_cpu(rdev->wb.wb[index/4]);
722 if (tmp == 0xDEADBEEF)
723 break;
724 DRM_UDELAY(1);
725 }
726 if (i < rdev->usec_timeout) {
727 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
728 } else {
729 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
730 r = -EINVAL;
731 }
732 radeon_ib_free(rdev, &ib);
733 return r;
734 }
735
736 /**
737 * cik_sdma_is_lockup - Check if the DMA engine is locked up
738 *
739 * @rdev: radeon_device pointer
740 * @ring: radeon_ring structure holding ring information
741 *
742 * Check if the async DMA engine is locked up (CIK).
743 * Returns true if the engine appears to be locked up, false if not.
744 */
cik_sdma_is_lockup(struct radeon_device * rdev,struct radeon_ring * ring)745 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
746 {
747 u32 reset_mask = cik_gpu_check_soft_reset(rdev);
748 u32 mask;
749
750 if (ring->idx == R600_RING_TYPE_DMA_INDEX)
751 mask = RADEON_RESET_DMA;
752 else
753 mask = RADEON_RESET_DMA1;
754
755 if (!(reset_mask & mask)) {
756 radeon_ring_lockup_update(rdev, ring);
757 return false;
758 }
759 return radeon_ring_test_lockup(rdev, ring);
760 }
761
762 /**
763 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART
764 *
765 * @rdev: radeon_device pointer
766 * @ib: indirect buffer to fill with commands
767 * @pe: addr of the page entry
768 * @src: src addr to copy from
769 * @count: number of page entries to update
770 *
771 * Update PTEs by copying them from the GART using sDMA (CIK).
772 */
cik_sdma_vm_copy_pages(struct radeon_device * rdev,struct radeon_ib * ib,uint64_t pe,uint64_t src,unsigned count)773 void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
774 struct radeon_ib *ib,
775 uint64_t pe, uint64_t src,
776 unsigned count)
777 {
778 while (count) {
779 unsigned bytes = count * 8;
780 if (bytes > 0x1FFFF8)
781 bytes = 0x1FFFF8;
782
783 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,
784 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
785 ib->ptr[ib->length_dw++] = bytes;
786 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
787 ib->ptr[ib->length_dw++] = lower_32_bits(src);
788 ib->ptr[ib->length_dw++] = upper_32_bits(src);
789 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
790 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
791
792 pe += bytes;
793 src += bytes;
794 count -= bytes / 8;
795 }
796 }
797
798 /**
799 * cik_sdma_vm_write_pages - update PTEs by writing them manually
800 *
801 * @rdev: radeon_device pointer
802 * @ib: indirect buffer to fill with commands
803 * @pe: addr of the page entry
804 * @addr: dst addr to write into pe
805 * @count: number of page entries to update
806 * @incr: increase next addr by incr bytes
807 * @flags: access flags
808 *
809 * Update PTEs by writing them manually using sDMA (CIK).
810 */
cik_sdma_vm_write_pages(struct radeon_device * rdev,struct radeon_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint32_t flags)811 void cik_sdma_vm_write_pages(struct radeon_device *rdev,
812 struct radeon_ib *ib,
813 uint64_t pe,
814 uint64_t addr, unsigned count,
815 uint32_t incr, uint32_t flags)
816 {
817 uint64_t value;
818 unsigned ndw;
819
820 while (count) {
821 ndw = count * 2;
822 if (ndw > 0xFFFFE)
823 ndw = 0xFFFFE;
824
825 /* for non-physically contiguous pages (system) */
826 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,
827 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
828 ib->ptr[ib->length_dw++] = pe;
829 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
830 ib->ptr[ib->length_dw++] = ndw;
831 for (; ndw > 0; ndw -= 2, --count, pe += 8) {
832 if (flags & R600_PTE_SYSTEM) {
833 value = radeon_vm_map_gart(rdev, addr);
834 value &= 0xFFFFFFFFFFFFF000ULL;
835 } else if (flags & R600_PTE_VALID) {
836 value = addr;
837 } else {
838 value = 0;
839 }
840 addr += incr;
841 value |= flags;
842 ib->ptr[ib->length_dw++] = value;
843 ib->ptr[ib->length_dw++] = upper_32_bits(value);
844 }
845 }
846 }
847
848 /**
849 * cik_sdma_vm_set_pages - update the page tables using sDMA
850 *
851 * @rdev: radeon_device pointer
852 * @ib: indirect buffer to fill with commands
853 * @pe: addr of the page entry
854 * @addr: dst addr to write into pe
855 * @count: number of page entries to update
856 * @incr: increase next addr by incr bytes
857 * @flags: access flags
858 *
859 * Update the page tables using sDMA (CIK).
860 */
cik_sdma_vm_set_pages(struct radeon_device * rdev,struct radeon_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint32_t flags)861 void cik_sdma_vm_set_pages(struct radeon_device *rdev,
862 struct radeon_ib *ib,
863 uint64_t pe,
864 uint64_t addr, unsigned count,
865 uint32_t incr, uint32_t flags)
866 {
867 uint64_t value;
868 unsigned ndw;
869
870 while (count) {
871 ndw = count;
872 if (ndw > 0x7FFFF)
873 ndw = 0x7FFFF;
874
875 if (flags & R600_PTE_VALID)
876 value = addr;
877 else
878 value = 0;
879
880 /* for physically contiguous pages (vram) */
881 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);
882 ib->ptr[ib->length_dw++] = pe; /* dst addr */
883 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
884 ib->ptr[ib->length_dw++] = flags; /* mask */
885 ib->ptr[ib->length_dw++] = 0;
886 ib->ptr[ib->length_dw++] = value; /* value */
887 ib->ptr[ib->length_dw++] = upper_32_bits(value);
888 ib->ptr[ib->length_dw++] = incr; /* increment size */
889 ib->ptr[ib->length_dw++] = 0;
890 ib->ptr[ib->length_dw++] = ndw; /* number of entries */
891
892 pe += ndw * 8;
893 addr += ndw * incr;
894 count -= ndw;
895 }
896 }
897
898 /**
899 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw
900 *
901 * @ib: indirect buffer to fill with padding
902 *
903 */
cik_sdma_vm_pad_ib(struct radeon_ib * ib)904 void cik_sdma_vm_pad_ib(struct radeon_ib *ib)
905 {
906 while (ib->length_dw & 0x7)
907 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);
908 }
909
910 /**
911 * cik_dma_vm_flush - cik vm flush using sDMA
912 *
913 * @rdev: radeon_device pointer
914 *
915 * Update the page table base and flush the VM TLB
916 * using sDMA (CIK).
917 */
cik_dma_vm_flush(struct radeon_device * rdev,int ridx,struct radeon_vm * vm)918 void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
919 {
920 struct radeon_ring *ring = &rdev->ring[ridx];
921
922 if (vm == NULL)
923 return;
924
925 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
926 if (vm->id < 8) {
927 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
928 } else {
929 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
930 }
931 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
932
933 /* update SH_MEM_* regs */
934 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
935 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
936 radeon_ring_write(ring, VMID(vm->id));
937
938 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
939 radeon_ring_write(ring, SH_MEM_BASES >> 2);
940 radeon_ring_write(ring, 0);
941
942 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
943 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);
944 radeon_ring_write(ring, 0);
945
946 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
947 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);
948 radeon_ring_write(ring, 1);
949
950 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
951 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);
952 radeon_ring_write(ring, 0);
953
954 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
955 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
956 radeon_ring_write(ring, VMID(0));
957
958 /* flush HDP */
959 cik_sdma_hdp_flush_ring_emit(rdev, ridx);
960
961 /* flush TLB */
962 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
963 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
964 radeon_ring_write(ring, 1 << vm->id);
965 }
966
967