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Searched refs:AT91_DDRSDRC_LPR (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-at91/
Dpm.h64 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR); in at91_ddr_standby()
69 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR); in at91_ddr_standby()
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0); in at91_ddr_standby()
76 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1); in at91_ddr_standby()
80 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0); in at91_ddr_standby()
82 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); in at91_ddr_standby()
Dpm_slowclock.S147 ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
154 ldrne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
160 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
161 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
294 str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
299 strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
/arch/arm/mach-at91/include/mach/
Dat91sam9_ddrsdr.h77 #define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */ macro