1 /*
2 * AT91 Power Management
3 *
4 * Copyright (C) 2005 David Brownell
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #ifndef __ARCH_ARM_MACH_AT91_PM
12 #define __ARCH_ARM_MACH_AT91_PM
13
14 #include <asm/proc-fns.h>
15
16 #include <mach/at91_ramc.h>
17 #include <mach/at91rm9200_sdramc.h>
18
19 #ifdef CONFIG_PM
20 extern void at91_pm_set_standby(void (*at91_standby)(void));
21 #else
at91_pm_set_standby(void (* at91_standby)(void))22 static inline void at91_pm_set_standby(void (*at91_standby)(void)) { }
23 #endif
24
25 /*
26 * The AT91RM9200 goes into self-refresh mode with this command, and will
27 * terminate self-refresh automatically on the next SDRAM access.
28 *
29 * Self-refresh mode is exited as soon as a memory access is made, but we don't
30 * know for sure when that happens. However, we need to restore the low-power
31 * mode if it was enabled before going idle. Restoring low-power mode while
32 * still in self-refresh is "not recommended", but seems to work.
33 */
34
at91rm9200_standby(void)35 static inline void at91rm9200_standby(void)
36 {
37 u32 lpr = at91_ramc_read(0, AT91RM9200_SDRAMC_LPR);
38
39 asm volatile(
40 "b 1f\n\t"
41 ".align 5\n\t"
42 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
43 " str %0, [%1, %2]\n\t"
44 " str %3, [%1, %4]\n\t"
45 " mcr p15, 0, %0, c7, c0, 4\n\t"
46 " str %5, [%1, %2]"
47 :
48 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91RM9200_SDRAMC_LPR),
49 "r" (1), "r" (AT91RM9200_SDRAMC_SRR),
50 "r" (lpr));
51 }
52
53 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
54 * remember.
55 */
at91_ddr_standby(void)56 static inline void at91_ddr_standby(void)
57 {
58 /* Those two values allow us to delay self-refresh activation
59 * to the maximum. */
60 u32 lpr0, lpr1 = 0;
61 u32 saved_lpr0, saved_lpr1 = 0;
62
63 if (at91_ramc_base[1]) {
64 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
65 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
66 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
67 }
68
69 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
70 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
71 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
72
73 /* self-refresh mode now */
74 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
75 if (at91_ramc_base[1])
76 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
77
78 cpu_do_idle();
79
80 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
81 if (at91_ramc_base[1])
82 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
83 }
84
85 /* We manage both DDRAM/SDRAM controllers, we need more than one value to
86 * remember.
87 */
at91sam9_sdram_standby(void)88 static inline void at91sam9_sdram_standby(void)
89 {
90 u32 lpr0, lpr1 = 0;
91 u32 saved_lpr0, saved_lpr1 = 0;
92
93 if (at91_ramc_base[1]) {
94 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
95 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
96 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
97 }
98
99 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
100 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
101 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
102
103 /* self-refresh mode now */
104 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
105 if (at91_ramc_base[1])
106 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
107
108 cpu_do_idle();
109
110 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
111 if (at91_ramc_base[1])
112 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
113 }
114
115 #endif
116