Searched refs:DMA3_IRQ_STATUS (Results 1 – 14 of 14) sorted by relevance
239 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ macro
244 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)245 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
272 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ macro
497 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)498 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
480 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)481 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
248 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register … macro
459 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)460 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS,val)
249 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ macro
582 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)583 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
264 #define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */ macro
414 #define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)415 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
1593 #define DMA3_IRQ_STATUS 0xFFC411B0 /* DMA3 Status Register */ macro
458 #define bfin_read_DMA3_IRQ_STATUS() bfin_read32(DMA3_IRQ_STATUS)459 #define bfin_write_DMA3_IRQ_STATUS(val) bfin_write32(DMA3_IRQ_STATUS, val)