1 /* 2 * System & MMR bit and Address definitions for ADSP-BF532 3 * 4 * Copyright 2005-2010 Analog Devices Inc. 5 * 6 * Licensed under the Clear BSD license or the GPL-2 (or later) 7 */ 8 9 #ifndef _DEF_BF532_H 10 #define _DEF_BF532_H 11 12 /*********************************************************************************** */ 13 /* System MMR Register Map */ 14 /*********************************************************************************** */ 15 /* Clock and System Control (0xFFC00000 - 0xFFC000FF) */ 16 17 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */ 18 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */ 19 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */ 20 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 21 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 22 #define CHIPID 0xFFC00014 /* Chip ID Register */ 23 24 /* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 25 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */ 26 #define SYSCR 0xFFC00104 /* System Configuration registe */ 27 #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 28 #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 29 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 30 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */ 31 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */ 32 #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */ 33 #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */ 34 35 /* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */ 36 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */ 37 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */ 38 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */ 39 40 /* Real Time Clock (0xFFC00300 - 0xFFC003FF) */ 41 #define RTC_STAT 0xFFC00300 /* RTC Status Register */ 42 #define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */ 43 #define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */ 44 #define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */ 45 #define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */ 46 #define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */ 47 #define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Register (alternate macro) */ 48 49 /* UART Controller (0xFFC00400 - 0xFFC004FF) */ 50 51 /* 52 * Because include/linux/serial_reg.h have defined UART_*, 53 * So we define blackfin uart regs to BFIN_UART_*. 54 */ 55 #define BFIN_UART_THR 0xFFC00400 /* Transmit Holding register */ 56 #define BFIN_UART_RBR 0xFFC00400 /* Receive Buffer register */ 57 #define BFIN_UART_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */ 58 #define BFIN_UART_IER 0xFFC00404 /* Interrupt Enable Register */ 59 #define BFIN_UART_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */ 60 #define BFIN_UART_IIR 0xFFC00408 /* Interrupt Identification Register */ 61 #define BFIN_UART_LCR 0xFFC0040C /* Line Control Register */ 62 #define BFIN_UART_MCR 0xFFC00410 /* Modem Control Register */ 63 #define BFIN_UART_LSR 0xFFC00414 /* Line Status Register */ 64 #if 0 65 #define BFIN_UART_MSR 0xFFC00418 /* Modem Status Register (UNUSED in ADSP-BF532) */ 66 #endif 67 #define BFIN_UART_SCR 0xFFC0041C /* SCR Scratch Register */ 68 #define BFIN_UART_GCTL 0xFFC00424 /* Global Control Register */ 69 70 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 71 #define SPI0_REGBASE 0xFFC00500 72 #define SPI_CTL 0xFFC00500 /* SPI Control Register */ 73 #define SPI_FLG 0xFFC00504 /* SPI Flag register */ 74 #define SPI_STAT 0xFFC00508 /* SPI Status register */ 75 #define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */ 76 #define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */ 77 #define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */ 78 #define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */ 79 80 /* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */ 81 82 #define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */ 83 #define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */ 84 #define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */ 85 #define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */ 86 87 #define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */ 88 #define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */ 89 #define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */ 90 #define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */ 91 92 #define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */ 93 #define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */ 94 #define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */ 95 #define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */ 96 97 #define TIMER_ENABLE 0xFFC00640 /* Timer Enable Register */ 98 #define TIMER_DISABLE 0xFFC00644 /* Timer Disable Register */ 99 #define TIMER_STATUS 0xFFC00648 /* Timer Status Register */ 100 101 /* General Purpose IO (0xFFC00700 - 0xFFC007FF) */ 102 103 #define FIO_FLAG_D 0xFFC00700 /* Flag Mask to directly specify state of pins */ 104 #define FIO_FLAG_C 0xFFC00704 /* Peripheral Interrupt Flag Register (clear) */ 105 #define FIO_FLAG_S 0xFFC00708 /* Peripheral Interrupt Flag Register (set) */ 106 #define FIO_FLAG_T 0xFFC0070C /* Flag Mask to directly toggle state of pins */ 107 #define FIO_MASKA_D 0xFFC00710 /* Flag Mask Interrupt A Register (set directly) */ 108 #define FIO_MASKA_C 0xFFC00714 /* Flag Mask Interrupt A Register (clear) */ 109 #define FIO_MASKA_S 0xFFC00718 /* Flag Mask Interrupt A Register (set) */ 110 #define FIO_MASKA_T 0xFFC0071C /* Flag Mask Interrupt A Register (toggle) */ 111 #define FIO_MASKB_D 0xFFC00720 /* Flag Mask Interrupt B Register (set directly) */ 112 #define FIO_MASKB_C 0xFFC00724 /* Flag Mask Interrupt B Register (clear) */ 113 #define FIO_MASKB_S 0xFFC00728 /* Flag Mask Interrupt B Register (set) */ 114 #define FIO_MASKB_T 0xFFC0072C /* Flag Mask Interrupt B Register (toggle) */ 115 #define FIO_DIR 0xFFC00730 /* Peripheral Flag Direction Register */ 116 #define FIO_POLAR 0xFFC00734 /* Flag Source Polarity Register */ 117 #define FIO_EDGE 0xFFC00738 /* Flag Source Sensitivity Register */ 118 #define FIO_BOTH 0xFFC0073C /* Flag Set on BOTH Edges Register */ 119 #define FIO_INEN 0xFFC00740 /* Flag Input Enable Register */ 120 121 /* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */ 122 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */ 123 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ 124 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */ 125 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */ 126 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */ 127 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */ 128 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */ 129 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */ 130 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */ 131 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */ 132 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */ 133 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */ 134 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */ 135 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */ 136 #define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */ 137 #define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */ 138 #define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */ 139 #define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */ 140 #define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */ 141 #define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */ 142 #define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */ 143 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ 144 145 /* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */ 146 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */ 147 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */ 148 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */ 149 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */ 150 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */ 151 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */ 152 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */ 153 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */ 154 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */ 155 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */ 156 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */ 157 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */ 158 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */ 159 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */ 160 #define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */ 161 #define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */ 162 #define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */ 163 #define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */ 164 #define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */ 165 #define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */ 166 #define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */ 167 #define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */ 168 169 /* Asynchronous Memory Controller - External Bus Interface Unit */ 170 #define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */ 171 #define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */ 172 #define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */ 173 174 /* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */ 175 176 #define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */ 177 #define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */ 178 #define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */ 179 #define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 180 181 /* DMA Traffic controls */ 182 #define DMAC_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 183 #define DMAC_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 184 185 /* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 186 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 187 #define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 188 #define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */ 189 #define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */ 190 #define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */ 191 #define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */ 192 #define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */ 193 #define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */ 194 #define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */ 195 #define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */ 196 #define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */ 197 #define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */ 198 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */ 199 200 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */ 201 #define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */ 202 #define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */ 203 #define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */ 204 #define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */ 205 #define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */ 206 #define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */ 207 #define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */ 208 #define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */ 209 #define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */ 210 #define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */ 211 #define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */ 212 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */ 213 214 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */ 215 #define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */ 216 #define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */ 217 #define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */ 218 #define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */ 219 #define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */ 220 #define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */ 221 #define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */ 222 #define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */ 223 #define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */ 224 #define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */ 225 #define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */ 226 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */ 227 228 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */ 229 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */ 230 #define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */ 231 #define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */ 232 #define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */ 233 #define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */ 234 #define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */ 235 #define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */ 236 #define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */ 237 #define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */ 238 #define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */ 239 #define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */ 240 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */ 241 242 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */ 243 #define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */ 244 #define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */ 245 #define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */ 246 #define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */ 247 #define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */ 248 #define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */ 249 #define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */ 250 #define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */ 251 #define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */ 252 #define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */ 253 #define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */ 254 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */ 255 256 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ 257 #define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */ 258 #define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */ 259 #define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */ 260 #define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */ 261 #define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */ 262 #define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */ 263 #define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */ 264 #define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */ 265 #define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */ 266 #define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */ 267 #define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */ 268 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */ 269 270 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */ 271 #define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */ 272 #define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */ 273 #define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */ 274 #define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */ 275 #define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */ 276 #define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */ 277 #define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */ 278 #define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */ 279 #define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */ 280 #define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */ 281 #define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */ 282 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */ 283 284 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */ 285 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */ 286 #define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */ 287 #define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */ 288 #define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */ 289 #define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */ 290 #define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */ 291 #define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */ 292 #define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */ 293 #define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */ 294 #define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */ 295 #define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */ 296 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */ 297 298 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */ 299 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */ 300 #define MDMA_D1_START_ADDR 0xFFC00E84 /* MemDMA Stream 1 Destination Start Address Register */ 301 #define MDMA_D1_X_COUNT 0xFFC00E90 /* MemDMA Stream 1 Destination X Count Register */ 302 #define MDMA_D1_Y_COUNT 0xFFC00E98 /* MemDMA Stream 1 Destination Y Count Register */ 303 #define MDMA_D1_X_MODIFY 0xFFC00E94 /* MemDMA Stream 1 Destination X Modify Register */ 304 #define MDMA_D1_Y_MODIFY 0xFFC00E9C /* MemDMA Stream 1 Destination Y Modify Register */ 305 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */ 306 #define MDMA_D1_CURR_ADDR 0xFFC00EA4 /* MemDMA Stream 1 Destination Current Address Register */ 307 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0 /* MemDMA Stream 1 Destination Current X Count Register */ 308 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8 /* MemDMA Stream 1 Destination Current Y Count Register */ 309 #define MDMA_D1_IRQ_STATUS 0xFFC00EA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */ 310 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC /* MemDMA Stream 1 Destination Peripheral Map Register */ 311 312 #define MDMA_S1_CONFIG 0xFFC00EC8 /* MemDMA Stream 1 Source Configuration Register */ 313 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */ 314 #define MDMA_S1_START_ADDR 0xFFC00EC4 /* MemDMA Stream 1 Source Start Address Register */ 315 #define MDMA_S1_X_COUNT 0xFFC00ED0 /* MemDMA Stream 1 Source X Count Register */ 316 #define MDMA_S1_Y_COUNT 0xFFC00ED8 /* MemDMA Stream 1 Source Y Count Register */ 317 #define MDMA_S1_X_MODIFY 0xFFC00ED4 /* MemDMA Stream 1 Source X Modify Register */ 318 #define MDMA_S1_Y_MODIFY 0xFFC00EDC /* MemDMA Stream 1 Source Y Modify Register */ 319 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */ 320 #define MDMA_S1_CURR_ADDR 0xFFC00EE4 /* MemDMA Stream 1 Source Current Address Register */ 321 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0 /* MemDMA Stream 1 Source Current X Count Register */ 322 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8 /* MemDMA Stream 1 Source Current Y Count Register */ 323 #define MDMA_S1_IRQ_STATUS 0xFFC00EE8 /* MemDMA Stream 1 Source Interrupt/Status Register */ 324 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC /* MemDMA Stream 1 Source Peripheral Map Register */ 325 326 #define MDMA_D0_CONFIG 0xFFC00E08 /* MemDMA Stream 0 Destination Configuration Register */ 327 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */ 328 #define MDMA_D0_START_ADDR 0xFFC00E04 /* MemDMA Stream 0 Destination Start Address Register */ 329 #define MDMA_D0_X_COUNT 0xFFC00E10 /* MemDMA Stream 0 Destination X Count Register */ 330 #define MDMA_D0_Y_COUNT 0xFFC00E18 /* MemDMA Stream 0 Destination Y Count Register */ 331 #define MDMA_D0_X_MODIFY 0xFFC00E14 /* MemDMA Stream 0 Destination X Modify Register */ 332 #define MDMA_D0_Y_MODIFY 0xFFC00E1C /* MemDMA Stream 0 Destination Y Modify Register */ 333 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */ 334 #define MDMA_D0_CURR_ADDR 0xFFC00E24 /* MemDMA Stream 0 Destination Current Address Register */ 335 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30 /* MemDMA Stream 0 Destination Current X Count Register */ 336 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38 /* MemDMA Stream 0 Destination Current Y Count Register */ 337 #define MDMA_D0_IRQ_STATUS 0xFFC00E28 /* MemDMA Stream 0 Destination Interrupt/Status Register */ 338 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C /* MemDMA Stream 0 Destination Peripheral Map Register */ 339 340 #define MDMA_S0_CONFIG 0xFFC00E48 /* MemDMA Stream 0 Source Configuration Register */ 341 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */ 342 #define MDMA_S0_START_ADDR 0xFFC00E44 /* MemDMA Stream 0 Source Start Address Register */ 343 #define MDMA_S0_X_COUNT 0xFFC00E50 /* MemDMA Stream 0 Source X Count Register */ 344 #define MDMA_S0_Y_COUNT 0xFFC00E58 /* MemDMA Stream 0 Source Y Count Register */ 345 #define MDMA_S0_X_MODIFY 0xFFC00E54 /* MemDMA Stream 0 Source X Modify Register */ 346 #define MDMA_S0_Y_MODIFY 0xFFC00E5C /* MemDMA Stream 0 Source Y Modify Register */ 347 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */ 348 #define MDMA_S0_CURR_ADDR 0xFFC00E64 /* MemDMA Stream 0 Source Current Address Register */ 349 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70 /* MemDMA Stream 0 Source Current X Count Register */ 350 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78 /* MemDMA Stream 0 Source Current Y Count Register */ 351 #define MDMA_S0_IRQ_STATUS 0xFFC00E68 /* MemDMA Stream 0 Source Interrupt/Status Register */ 352 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C /* MemDMA Stream 0 Source Peripheral Map Register */ 353 354 /* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */ 355 356 #define PPI_CONTROL 0xFFC01000 /* PPI Control Register */ 357 #define PPI_STATUS 0xFFC01004 /* PPI Status Register */ 358 #define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */ 359 #define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */ 360 #define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 361 362 /*********************************************************************************** */ 363 /* System MMR Register Bits */ 364 /******************************************************************************* */ 365 366 /* CHIPID Masks */ 367 #define CHIPID_VERSION 0xF0000000 368 #define CHIPID_FAMILY 0x0FFFF000 369 #define CHIPID_MANUFACTURE 0x00000FFE 370 371 /* SWRST Mask */ 372 #define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ 373 #define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ 374 #define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ 375 #define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ 376 #define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 377 378 /* SYSCR Masks */ 379 #define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ 380 #define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 381 382 /* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 383 384 /* SIC_IAR0 Masks */ 385 386 #define P0_IVG(x) ((x)-7) /* Peripheral #0 assigned IVG #x */ 387 #define P1_IVG(x) ((x)-7) << 0x4 /* Peripheral #1 assigned IVG #x */ 388 #define P2_IVG(x) ((x)-7) << 0x8 /* Peripheral #2 assigned IVG #x */ 389 #define P3_IVG(x) ((x)-7) << 0xC /* Peripheral #3 assigned IVG #x */ 390 #define P4_IVG(x) ((x)-7) << 0x10 /* Peripheral #4 assigned IVG #x */ 391 #define P5_IVG(x) ((x)-7) << 0x14 /* Peripheral #5 assigned IVG #x */ 392 #define P6_IVG(x) ((x)-7) << 0x18 /* Peripheral #6 assigned IVG #x */ 393 #define P7_IVG(x) ((x)-7) << 0x1C /* Peripheral #7 assigned IVG #x */ 394 395 /* SIC_IAR1 Masks */ 396 397 #define P8_IVG(x) ((x)-7) /* Peripheral #8 assigned IVG #x */ 398 #define P9_IVG(x) ((x)-7) << 0x4 /* Peripheral #9 assigned IVG #x */ 399 #define P10_IVG(x) ((x)-7) << 0x8 /* Peripheral #10 assigned IVG #x */ 400 #define P11_IVG(x) ((x)-7) << 0xC /* Peripheral #11 assigned IVG #x */ 401 #define P12_IVG(x) ((x)-7) << 0x10 /* Peripheral #12 assigned IVG #x */ 402 #define P13_IVG(x) ((x)-7) << 0x14 /* Peripheral #13 assigned IVG #x */ 403 #define P14_IVG(x) ((x)-7) << 0x18 /* Peripheral #14 assigned IVG #x */ 404 #define P15_IVG(x) ((x)-7) << 0x1C /* Peripheral #15 assigned IVG #x */ 405 406 /* SIC_IAR2 Masks */ 407 #define P16_IVG(x) ((x)-7) /* Peripheral #16 assigned IVG #x */ 408 #define P17_IVG(x) ((x)-7) << 0x4 /* Peripheral #17 assigned IVG #x */ 409 #define P18_IVG(x) ((x)-7) << 0x8 /* Peripheral #18 assigned IVG #x */ 410 #define P19_IVG(x) ((x)-7) << 0xC /* Peripheral #19 assigned IVG #x */ 411 #define P20_IVG(x) ((x)-7) << 0x10 /* Peripheral #20 assigned IVG #x */ 412 #define P21_IVG(x) ((x)-7) << 0x14 /* Peripheral #21 assigned IVG #x */ 413 #define P22_IVG(x) ((x)-7) << 0x18 /* Peripheral #22 assigned IVG #x */ 414 #define P23_IVG(x) ((x)-7) << 0x1C /* Peripheral #23 assigned IVG #x */ 415 416 /* SIC_IMASK Masks */ 417 #define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */ 418 #define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */ 419 #define SIC_MASK(x) (1 << (x)) /* Mask Peripheral #x interrupt */ 420 #define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */ 421 422 /* SIC_IWR Masks */ 423 #define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */ 424 #define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */ 425 #define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 426 #define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 427 428 /* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 429 430 /* PPI_CONTROL Masks */ 431 #define PORT_EN 0x00000001 /* PPI Port Enable */ 432 #define PORT_DIR 0x00000002 /* PPI Port Direction */ 433 #define XFR_TYPE 0x0000000C /* PPI Transfer Type */ 434 #define PORT_CFG 0x00000030 /* PPI Port Configuration */ 435 #define FLD_SEL 0x00000040 /* PPI Active Field Select */ 436 #define PACK_EN 0x00000080 /* PPI Packing Mode */ 437 #define DMA32 0x00000100 /* PPI 32-bit DMA Enable */ 438 #define SKIP_EN 0x00000200 /* PPI Skip Element Enable */ 439 #define SKIP_EO 0x00000400 /* PPI Skip Even/Odd Elements */ 440 #define DLENGTH 0x00003800 /* PPI Data Length */ 441 #define DLEN_8 0x0000 /* Data Length = 8 Bits */ 442 #define DLEN_10 0x0800 /* Data Length = 10 Bits */ 443 #define DLEN_11 0x1000 /* Data Length = 11 Bits */ 444 #define DLEN_12 0x1800 /* Data Length = 12 Bits */ 445 #define DLEN_13 0x2000 /* Data Length = 13 Bits */ 446 #define DLEN_14 0x2800 /* Data Length = 14 Bits */ 447 #define DLEN_15 0x3000 /* Data Length = 15 Bits */ 448 #define DLEN_16 0x3800 /* Data Length = 16 Bits */ 449 #define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 450 #define POL 0x0000C000 /* PPI Signal Polarities */ 451 #define POLC 0x4000 /* PPI Clock Polarity */ 452 #define POLS 0x8000 /* PPI Frame Sync Polarity */ 453 454 /* PPI_STATUS Masks */ 455 #define FLD 0x00000400 /* Field Indicator */ 456 #define FT_ERR 0x00000800 /* Frame Track Error */ 457 #define OVR 0x00001000 /* FIFO Overflow Error */ 458 #define UNDR 0x00002000 /* FIFO Underrun Error */ 459 #define ERR_DET 0x00004000 /* Error Detected Indicator */ 460 #define ERR_NCOR 0x00008000 /* Error Not Corrected Indicator */ 461 462 /* ********** DMA CONTROLLER MASKS *********************8 */ 463 464 /* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */ 465 466 #define CTYPE 0x00000040 /* DMA Channel Type Indicator */ 467 #define CTYPE_P 6 /* DMA Channel Type Indicator BIT POSITION */ 468 #define PCAP8 0x00000080 /* DMA 8-bit Operation Indicator */ 469 #define PCAP16 0x00000100 /* DMA 16-bit Operation Indicator */ 470 #define PCAP32 0x00000200 /* DMA 32-bit Operation Indicator */ 471 #define PCAPWR 0x00000400 /* DMA Write Operation Indicator */ 472 #define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ 473 #define PMAP 0x00007000 /* DMA Peripheral Map Field */ 474 475 #define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */ 476 #define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */ 477 #define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */ 478 #define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */ 479 #define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */ 480 #define PMAP_SPI 0x5000 /* PMAP SPI DMA */ 481 #define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */ 482 #define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */ 483 484 /* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 485 486 /* PWM Timer bit definitions */ 487 488 /* TIMER_ENABLE Register */ 489 #define TIMEN0 0x0001 490 #define TIMEN1 0x0002 491 #define TIMEN2 0x0004 492 493 #define TIMEN0_P 0x00 494 #define TIMEN1_P 0x01 495 #define TIMEN2_P 0x02 496 497 /* TIMER_DISABLE Register */ 498 #define TIMDIS0 0x0001 499 #define TIMDIS1 0x0002 500 #define TIMDIS2 0x0004 501 502 #define TIMDIS0_P 0x00 503 #define TIMDIS1_P 0x01 504 #define TIMDIS2_P 0x02 505 506 /* TIMER_STATUS Register */ 507 #define TIMIL0 0x0001 508 #define TIMIL1 0x0002 509 #define TIMIL2 0x0004 510 #define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */ 511 #define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */ 512 #define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */ 513 #define TRUN0 0x1000 514 #define TRUN1 0x2000 515 #define TRUN2 0x4000 516 517 #define TIMIL0_P 0x00 518 #define TIMIL1_P 0x01 519 #define TIMIL2_P 0x02 520 #define TOVF_ERR0_P 0x04 521 #define TOVF_ERR1_P 0x05 522 #define TOVF_ERR2_P 0x06 523 #define TRUN0_P 0x0C 524 #define TRUN1_P 0x0D 525 #define TRUN2_P 0x0E 526 527 /* Alternate Deprecated Macros Provided For Backwards Code Compatibility */ 528 #define TOVL_ERR0 TOVF_ERR0 529 #define TOVL_ERR1 TOVF_ERR1 530 #define TOVL_ERR2 TOVF_ERR2 531 #define TOVL_ERR0_P TOVF_ERR0_P 532 #define TOVL_ERR1_P TOVF_ERR1_P 533 #define TOVL_ERR2_P TOVF_ERR2_P 534 535 /* TIMERx_CONFIG Registers */ 536 #define PWM_OUT 0x0001 537 #define WDTH_CAP 0x0002 538 #define EXT_CLK 0x0003 539 #define PULSE_HI 0x0004 540 #define PERIOD_CNT 0x0008 541 #define IRQ_ENA 0x0010 542 #define TIN_SEL 0x0020 543 #define OUT_DIS 0x0040 544 #define CLK_SEL 0x0080 545 #define TOGGLE_HI 0x0100 546 #define EMU_RUN 0x0200 547 #define ERR_TYP(x) ((x & 0x03) << 14) 548 549 #define TMODE_P0 0x00 550 #define TMODE_P1 0x01 551 #define PULSE_HI_P 0x02 552 #define PERIOD_CNT_P 0x03 553 #define IRQ_ENA_P 0x04 554 #define TIN_SEL_P 0x05 555 #define OUT_DIS_P 0x06 556 #define CLK_SEL_P 0x07 557 #define TOGGLE_HI_P 0x08 558 #define EMU_RUN_P 0x09 559 #define ERR_TYP_P0 0x0E 560 #define ERR_TYP_P1 0x0F 561 562 /* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 563 564 /* AMGCTL Masks */ 565 #define AMCKEN 0x00000001 /* Enable CLKOUT */ 566 #define AMBEN_NONE 0x00000000 /* All Banks Disabled */ 567 #define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ 568 #define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 569 #define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 570 #define AMBEN_ALL 0x00000008 /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */ 571 572 /* AMGCTL Bit Positions */ 573 #define AMCKEN_P 0x00000000 /* Enable CLKOUT */ 574 #define AMBEN_P0 0x00000001 /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */ 575 #define AMBEN_P1 0x00000002 /* Asynchronous Memory Enable, 010 - banks 0&1 enabled, 011 - banks 0-3 enabled */ 576 #define AMBEN_P2 0x00000003 /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */ 577 578 /* AMBCTL0 Masks */ 579 #define B0RDYEN 0x00000001 /* Bank 0 RDY Enable, 0=disable, 1=enable */ 580 #define B0RDYPOL 0x00000002 /* Bank 0 RDY Active high, 0=active low, 1=active high */ 581 #define B0TT_1 0x00000004 /* Bank 0 Transition Time from Read to Write = 1 cycle */ 582 #define B0TT_2 0x00000008 /* Bank 0 Transition Time from Read to Write = 2 cycles */ 583 #define B0TT_3 0x0000000C /* Bank 0 Transition Time from Read to Write = 3 cycles */ 584 #define B0TT_4 0x00000000 /* Bank 0 Transition Time from Read to Write = 4 cycles */ 585 #define B0ST_1 0x00000010 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */ 586 #define B0ST_2 0x00000020 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */ 587 #define B0ST_3 0x00000030 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */ 588 #define B0ST_4 0x00000000 /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */ 589 #define B0HT_1 0x00000040 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */ 590 #define B0HT_2 0x00000080 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */ 591 #define B0HT_3 0x000000C0 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */ 592 #define B0HT_0 0x00000000 /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */ 593 #define B0RAT_1 0x00000100 /* Bank 0 Read Access Time = 1 cycle */ 594 #define B0RAT_2 0x00000200 /* Bank 0 Read Access Time = 2 cycles */ 595 #define B0RAT_3 0x00000300 /* Bank 0 Read Access Time = 3 cycles */ 596 #define B0RAT_4 0x00000400 /* Bank 0 Read Access Time = 4 cycles */ 597 #define B0RAT_5 0x00000500 /* Bank 0 Read Access Time = 5 cycles */ 598 #define B0RAT_6 0x00000600 /* Bank 0 Read Access Time = 6 cycles */ 599 #define B0RAT_7 0x00000700 /* Bank 0 Read Access Time = 7 cycles */ 600 #define B0RAT_8 0x00000800 /* Bank 0 Read Access Time = 8 cycles */ 601 #define B0RAT_9 0x00000900 /* Bank 0 Read Access Time = 9 cycles */ 602 #define B0RAT_10 0x00000A00 /* Bank 0 Read Access Time = 10 cycles */ 603 #define B0RAT_11 0x00000B00 /* Bank 0 Read Access Time = 11 cycles */ 604 #define B0RAT_12 0x00000C00 /* Bank 0 Read Access Time = 12 cycles */ 605 #define B0RAT_13 0x00000D00 /* Bank 0 Read Access Time = 13 cycles */ 606 #define B0RAT_14 0x00000E00 /* Bank 0 Read Access Time = 14 cycles */ 607 #define B0RAT_15 0x00000F00 /* Bank 0 Read Access Time = 15 cycles */ 608 #define B0WAT_1 0x00001000 /* Bank 0 Write Access Time = 1 cycle */ 609 #define B0WAT_2 0x00002000 /* Bank 0 Write Access Time = 2 cycles */ 610 #define B0WAT_3 0x00003000 /* Bank 0 Write Access Time = 3 cycles */ 611 #define B0WAT_4 0x00004000 /* Bank 0 Write Access Time = 4 cycles */ 612 #define B0WAT_5 0x00005000 /* Bank 0 Write Access Time = 5 cycles */ 613 #define B0WAT_6 0x00006000 /* Bank 0 Write Access Time = 6 cycles */ 614 #define B0WAT_7 0x00007000 /* Bank 0 Write Access Time = 7 cycles */ 615 #define B0WAT_8 0x00008000 /* Bank 0 Write Access Time = 8 cycles */ 616 #define B0WAT_9 0x00009000 /* Bank 0 Write Access Time = 9 cycles */ 617 #define B0WAT_10 0x0000A000 /* Bank 0 Write Access Time = 10 cycles */ 618 #define B0WAT_11 0x0000B000 /* Bank 0 Write Access Time = 11 cycles */ 619 #define B0WAT_12 0x0000C000 /* Bank 0 Write Access Time = 12 cycles */ 620 #define B0WAT_13 0x0000D000 /* Bank 0 Write Access Time = 13 cycles */ 621 #define B0WAT_14 0x0000E000 /* Bank 0 Write Access Time = 14 cycles */ 622 #define B0WAT_15 0x0000F000 /* Bank 0 Write Access Time = 15 cycles */ 623 #define B1RDYEN 0x00010000 /* Bank 1 RDY enable, 0=disable, 1=enable */ 624 #define B1RDYPOL 0x00020000 /* Bank 1 RDY Active high, 0=active low, 1=active high */ 625 #define B1TT_1 0x00040000 /* Bank 1 Transition Time from Read to Write = 1 cycle */ 626 #define B1TT_2 0x00080000 /* Bank 1 Transition Time from Read to Write = 2 cycles */ 627 #define B1TT_3 0x000C0000 /* Bank 1 Transition Time from Read to Write = 3 cycles */ 628 #define B1TT_4 0x00000000 /* Bank 1 Transition Time from Read to Write = 4 cycles */ 629 #define B1ST_1 0x00100000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 630 #define B1ST_2 0x00200000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 631 #define B1ST_3 0x00300000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 632 #define B1ST_4 0x00000000 /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 633 #define B1HT_1 0x00400000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 634 #define B1HT_2 0x00800000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 635 #define B1HT_3 0x00C00000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 636 #define B1HT_0 0x00000000 /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 637 #define B1RAT_1 0x01000000 /* Bank 1 Read Access Time = 1 cycle */ 638 #define B1RAT_2 0x02000000 /* Bank 1 Read Access Time = 2 cycles */ 639 #define B1RAT_3 0x03000000 /* Bank 1 Read Access Time = 3 cycles */ 640 #define B1RAT_4 0x04000000 /* Bank 1 Read Access Time = 4 cycles */ 641 #define B1RAT_5 0x05000000 /* Bank 1 Read Access Time = 5 cycles */ 642 #define B1RAT_6 0x06000000 /* Bank 1 Read Access Time = 6 cycles */ 643 #define B1RAT_7 0x07000000 /* Bank 1 Read Access Time = 7 cycles */ 644 #define B1RAT_8 0x08000000 /* Bank 1 Read Access Time = 8 cycles */ 645 #define B1RAT_9 0x09000000 /* Bank 1 Read Access Time = 9 cycles */ 646 #define B1RAT_10 0x0A000000 /* Bank 1 Read Access Time = 10 cycles */ 647 #define B1RAT_11 0x0B000000 /* Bank 1 Read Access Time = 11 cycles */ 648 #define B1RAT_12 0x0C000000 /* Bank 1 Read Access Time = 12 cycles */ 649 #define B1RAT_13 0x0D000000 /* Bank 1 Read Access Time = 13 cycles */ 650 #define B1RAT_14 0x0E000000 /* Bank 1 Read Access Time = 14 cycles */ 651 #define B1RAT_15 0x0F000000 /* Bank 1 Read Access Time = 15 cycles */ 652 #define B1WAT_1 0x10000000 /* Bank 1 Write Access Time = 1 cycle */ 653 #define B1WAT_2 0x20000000 /* Bank 1 Write Access Time = 2 cycles */ 654 #define B1WAT_3 0x30000000 /* Bank 1 Write Access Time = 3 cycles */ 655 #define B1WAT_4 0x40000000 /* Bank 1 Write Access Time = 4 cycles */ 656 #define B1WAT_5 0x50000000 /* Bank 1 Write Access Time = 5 cycles */ 657 #define B1WAT_6 0x60000000 /* Bank 1 Write Access Time = 6 cycles */ 658 #define B1WAT_7 0x70000000 /* Bank 1 Write Access Time = 7 cycles */ 659 #define B1WAT_8 0x80000000 /* Bank 1 Write Access Time = 8 cycles */ 660 #define B1WAT_9 0x90000000 /* Bank 1 Write Access Time = 9 cycles */ 661 #define B1WAT_10 0xA0000000 /* Bank 1 Write Access Time = 10 cycles */ 662 #define B1WAT_11 0xB0000000 /* Bank 1 Write Access Time = 11 cycles */ 663 #define B1WAT_12 0xC0000000 /* Bank 1 Write Access Time = 12 cycles */ 664 #define B1WAT_13 0xD0000000 /* Bank 1 Write Access Time = 13 cycles */ 665 #define B1WAT_14 0xE0000000 /* Bank 1 Write Access Time = 14 cycles */ 666 #define B1WAT_15 0xF0000000 /* Bank 1 Write Access Time = 15 cycles */ 667 668 /* AMBCTL1 Masks */ 669 #define B2RDYEN 0x00000001 /* Bank 2 RDY Enable, 0=disable, 1=enable */ 670 #define B2RDYPOL 0x00000002 /* Bank 2 RDY Active high, 0=active low, 1=active high */ 671 #define B2TT_1 0x00000004 /* Bank 2 Transition Time from Read to Write = 1 cycle */ 672 #define B2TT_2 0x00000008 /* Bank 2 Transition Time from Read to Write = 2 cycles */ 673 #define B2TT_3 0x0000000C /* Bank 2 Transition Time from Read to Write = 3 cycles */ 674 #define B2TT_4 0x00000000 /* Bank 2 Transition Time from Read to Write = 4 cycles */ 675 #define B2ST_1 0x00000010 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 676 #define B2ST_2 0x00000020 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 677 #define B2ST_3 0x00000030 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 678 #define B2ST_4 0x00000000 /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 679 #define B2HT_1 0x00000040 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 680 #define B2HT_2 0x00000080 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 681 #define B2HT_3 0x000000C0 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 682 #define B2HT_0 0x00000000 /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 683 #define B2RAT_1 0x00000100 /* Bank 2 Read Access Time = 1 cycle */ 684 #define B2RAT_2 0x00000200 /* Bank 2 Read Access Time = 2 cycles */ 685 #define B2RAT_3 0x00000300 /* Bank 2 Read Access Time = 3 cycles */ 686 #define B2RAT_4 0x00000400 /* Bank 2 Read Access Time = 4 cycles */ 687 #define B2RAT_5 0x00000500 /* Bank 2 Read Access Time = 5 cycles */ 688 #define B2RAT_6 0x00000600 /* Bank 2 Read Access Time = 6 cycles */ 689 #define B2RAT_7 0x00000700 /* Bank 2 Read Access Time = 7 cycles */ 690 #define B2RAT_8 0x00000800 /* Bank 2 Read Access Time = 8 cycles */ 691 #define B2RAT_9 0x00000900 /* Bank 2 Read Access Time = 9 cycles */ 692 #define B2RAT_10 0x00000A00 /* Bank 2 Read Access Time = 10 cycles */ 693 #define B2RAT_11 0x00000B00 /* Bank 2 Read Access Time = 11 cycles */ 694 #define B2RAT_12 0x00000C00 /* Bank 2 Read Access Time = 12 cycles */ 695 #define B2RAT_13 0x00000D00 /* Bank 2 Read Access Time = 13 cycles */ 696 #define B2RAT_14 0x00000E00 /* Bank 2 Read Access Time = 14 cycles */ 697 #define B2RAT_15 0x00000F00 /* Bank 2 Read Access Time = 15 cycles */ 698 #define B2WAT_1 0x00001000 /* Bank 2 Write Access Time = 1 cycle */ 699 #define B2WAT_2 0x00002000 /* Bank 2 Write Access Time = 2 cycles */ 700 #define B2WAT_3 0x00003000 /* Bank 2 Write Access Time = 3 cycles */ 701 #define B2WAT_4 0x00004000 /* Bank 2 Write Access Time = 4 cycles */ 702 #define B2WAT_5 0x00005000 /* Bank 2 Write Access Time = 5 cycles */ 703 #define B2WAT_6 0x00006000 /* Bank 2 Write Access Time = 6 cycles */ 704 #define B2WAT_7 0x00007000 /* Bank 2 Write Access Time = 7 cycles */ 705 #define B2WAT_8 0x00008000 /* Bank 2 Write Access Time = 8 cycles */ 706 #define B2WAT_9 0x00009000 /* Bank 2 Write Access Time = 9 cycles */ 707 #define B2WAT_10 0x0000A000 /* Bank 2 Write Access Time = 10 cycles */ 708 #define B2WAT_11 0x0000B000 /* Bank 2 Write Access Time = 11 cycles */ 709 #define B2WAT_12 0x0000C000 /* Bank 2 Write Access Time = 12 cycles */ 710 #define B2WAT_13 0x0000D000 /* Bank 2 Write Access Time = 13 cycles */ 711 #define B2WAT_14 0x0000E000 /* Bank 2 Write Access Time = 14 cycles */ 712 #define B2WAT_15 0x0000F000 /* Bank 2 Write Access Time = 15 cycles */ 713 #define B3RDYEN 0x00010000 /* Bank 3 RDY enable, 0=disable, 1=enable */ 714 #define B3RDYPOL 0x00020000 /* Bank 3 RDY Active high, 0=active low, 1=active high */ 715 #define B3TT_1 0x00040000 /* Bank 3 Transition Time from Read to Write = 1 cycle */ 716 #define B3TT_2 0x00080000 /* Bank 3 Transition Time from Read to Write = 2 cycles */ 717 #define B3TT_3 0x000C0000 /* Bank 3 Transition Time from Read to Write = 3 cycles */ 718 #define B3TT_4 0x00000000 /* Bank 3 Transition Time from Read to Write = 4 cycles */ 719 #define B3ST_1 0x00100000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */ 720 #define B3ST_2 0x00200000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */ 721 #define B3ST_3 0x00300000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */ 722 #define B3ST_4 0x00000000 /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */ 723 #define B3HT_1 0x00400000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */ 724 #define B3HT_2 0x00800000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */ 725 #define B3HT_3 0x00C00000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */ 726 #define B3HT_0 0x00000000 /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */ 727 #define B3RAT_1 0x01000000 /* Bank 3 Read Access Time = 1 cycle */ 728 #define B3RAT_2 0x02000000 /* Bank 3 Read Access Time = 2 cycles */ 729 #define B3RAT_3 0x03000000 /* Bank 3 Read Access Time = 3 cycles */ 730 #define B3RAT_4 0x04000000 /* Bank 3 Read Access Time = 4 cycles */ 731 #define B3RAT_5 0x05000000 /* Bank 3 Read Access Time = 5 cycles */ 732 #define B3RAT_6 0x06000000 /* Bank 3 Read Access Time = 6 cycles */ 733 #define B3RAT_7 0x07000000 /* Bank 3 Read Access Time = 7 cycles */ 734 #define B3RAT_8 0x08000000 /* Bank 3 Read Access Time = 8 cycles */ 735 #define B3RAT_9 0x09000000 /* Bank 3 Read Access Time = 9 cycles */ 736 #define B3RAT_10 0x0A000000 /* Bank 3 Read Access Time = 10 cycles */ 737 #define B3RAT_11 0x0B000000 /* Bank 3 Read Access Time = 11 cycles */ 738 #define B3RAT_12 0x0C000000 /* Bank 3 Read Access Time = 12 cycles */ 739 #define B3RAT_13 0x0D000000 /* Bank 3 Read Access Time = 13 cycles */ 740 #define B3RAT_14 0x0E000000 /* Bank 3 Read Access Time = 14 cycles */ 741 #define B3RAT_15 0x0F000000 /* Bank 3 Read Access Time = 15 cycles */ 742 #define B3WAT_1 0x10000000 /* Bank 3 Write Access Time = 1 cycle */ 743 #define B3WAT_2 0x20000000 /* Bank 3 Write Access Time = 2 cycles */ 744 #define B3WAT_3 0x30000000 /* Bank 3 Write Access Time = 3 cycles */ 745 #define B3WAT_4 0x40000000 /* Bank 3 Write Access Time = 4 cycles */ 746 #define B3WAT_5 0x50000000 /* Bank 3 Write Access Time = 5 cycles */ 747 #define B3WAT_6 0x60000000 /* Bank 3 Write Access Time = 6 cycles */ 748 #define B3WAT_7 0x70000000 /* Bank 3 Write Access Time = 7 cycles */ 749 #define B3WAT_8 0x80000000 /* Bank 3 Write Access Time = 8 cycles */ 750 #define B3WAT_9 0x90000000 /* Bank 3 Write Access Time = 9 cycles */ 751 #define B3WAT_10 0xA0000000 /* Bank 3 Write Access Time = 10 cycles */ 752 #define B3WAT_11 0xB0000000 /* Bank 3 Write Access Time = 11 cycles */ 753 #define B3WAT_12 0xC0000000 /* Bank 3 Write Access Time = 12 cycles */ 754 #define B3WAT_13 0xD0000000 /* Bank 3 Write Access Time = 13 cycles */ 755 #define B3WAT_14 0xE0000000 /* Bank 3 Write Access Time = 14 cycles */ 756 #define B3WAT_15 0xF0000000 /* Bank 3 Write Access Time = 15 cycles */ 757 758 /* ********************** SDRAM CONTROLLER MASKS *************************** */ 759 760 /* SDGCTL Masks */ 761 #define SCTLE 0x00000001 /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */ 762 #define CL_2 0x00000008 /* SDRAM CAS latency = 2 cycles */ 763 #define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 764 #define PFE 0x00000010 /* Enable SDRAM prefetch */ 765 #define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 766 #define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */ 767 #define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */ 768 #define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */ 769 #define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 770 #define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 771 #define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 772 #define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */ 773 #define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */ 774 #define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */ 775 #define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */ 776 #define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */ 777 #define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */ 778 #define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */ 779 #define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */ 780 #define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */ 781 #define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */ 782 #define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */ 783 #define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */ 784 #define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */ 785 #define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */ 786 #define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */ 787 #define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */ 788 #define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */ 789 #define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */ 790 #define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */ 791 #define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */ 792 #define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */ 793 #define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */ 794 #define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */ 795 #define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */ 796 #define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */ 797 #define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */ 798 #define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */ 799 #define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */ 800 #define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */ 801 #define PUPSD 0x00200000 /*Power-up start delay */ 802 #define PSM 0x00400000 /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */ 803 #define PSS 0x00800000 /* enable SDRAM power-up sequence on next SDRAM access */ 804 #define SRFS 0x01000000 /* Start SDRAM self-refresh mode */ 805 #define EBUFE 0x02000000 /* Enable external buffering timing */ 806 #define FBBRW 0x04000000 /* Fast back-to-back read write enable */ 807 #define EMREN 0x10000000 /* Extended mode register enable */ 808 #define TCSR 0x20000000 /* Temp compensated self refresh value 85 deg C */ 809 #define CDDBG 0x40000000 /* Tristate SDRAM controls during bus grant */ 810 811 /* EBIU_SDBCTL Masks */ 812 #define EBE 0x00000001 /* Enable SDRAM external bank */ 813 #define EBSZ_16 0x00000000 /* SDRAM external bank size = 16MB */ 814 #define EBSZ_32 0x00000002 /* SDRAM external bank size = 32MB */ 815 #define EBSZ_64 0x00000004 /* SDRAM external bank size = 64MB */ 816 #define EBSZ_128 0x00000006 /* SDRAM external bank size = 128MB */ 817 #define EBCAW_8 0x00000000 /* SDRAM external bank column address width = 8 bits */ 818 #define EBCAW_9 0x00000010 /* SDRAM external bank column address width = 9 bits */ 819 #define EBCAW_10 0x00000020 /* SDRAM external bank column address width = 9 bits */ 820 #define EBCAW_11 0x00000030 /* SDRAM external bank column address width = 9 bits */ 821 822 /* EBIU_SDSTAT Masks */ 823 #define SDCI 0x00000001 /* SDRAM controller is idle */ 824 #define SDSRA 0x00000002 /* SDRAM SDRAM self refresh is active */ 825 #define SDPUA 0x00000004 /* SDRAM power up active */ 826 #define SDRS 0x00000008 /* SDRAM is in reset state */ 827 #define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 828 #define BGSTAT 0x00000020 /* Bus granted */ 829 830 831 #endif /* _DEF_BF532_H */ 832