Searched refs:DMA5_CONFIG (Results 1 – 14 of 14) sorted by relevance
256 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
276 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)277 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
293 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
529 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)530 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
512 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)513 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
269 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register … macro
491 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)492 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG,val)
270 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */ macro
620 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)621 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
289 #define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */ macro
458 #define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)459 #define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
1627 #define DMA5_CONFIG 0xFFC41288 /* DMA5 Configuration Register */ macro
516 #define bfin_read_DMA5_CONFIG() bfin_read32(DMA5_CONFIG)517 #define bfin_write_DMA5_CONFIG(val) bfin_write32(DMA5_CONFIG, val)