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Searched refs:DPLL_CTL (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-omap1/
Dreset.c33 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in omap1_restart()
Dsram.S28 mov r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0xff000000
29 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
30 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
Dboard-voiceblue.c226 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4), DPLL_CTL); in voiceblue_restart()
Dclock_data.c821 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), in omap1_clk_init()
835 unsigned pll_ctl_val = omap_readw(DPLL_CTL); in omap1_clk_init()
/arch/arm/mach-omap1/include/mach/
Dhardware.h123 #define DPLL_CTL (0xfffecf00) macro