| /arch/sh/include/cpu-sh4/cpu/ |
| D | freq.h | 33 #define FRQCRA 0xa4150000 macro
39 #define FRQCR FRQCRA
|
| /arch/sh/kernel/cpu/sh4a/ |
| D | clock-sh7724.c | 31 #define FRQCRA 0xa4150000 macro
88 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; in pll_recalc()
143 value = __raw_readl(FRQCRA); in div4_kick()
145 __raw_writel(value, FRQCRA); in div4_kick()
166 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
168 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
169 [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0),
|
| /arch/sh/boards/mach-se/7724/ |
| D | sdram.S | 62 mov.l FRQCRA,r0
127 FRQCRA: .long 0xa4150000 label
|
| /arch/arm/mach-shmobile/ |
| D | clock-sh73a0.c | 28 #define FRQCRA IOMEM(0xe6150000) macro
230 [DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
236 [DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
237 [DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
238 [DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
239 [DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
240 [DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
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| D | clock-sh7372.c | 28 #define FRQCRA IOMEM(0xe6150000) macro
120 .enable_reg = (void __iomem *)FRQCRA,
324 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
326 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
327 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
328 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
|
| D | clock-r8a73a4.c | 36 #define FRQCRA 0xE6150000 macro
390 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
391 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
392 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
393 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
394 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
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| D | clock-r8a7740.c | 46 #define FRQCRA IOMEM(0xe6150000) macro
152 .enable_reg = (void __iomem *)FRQCRA,
322 [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
325 [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
|
| /arch/arm/mach-shmobile/include/mach/ |
| D | head-kzm9g.txt | 92 #define FRQCRA (CPG_BASE + 0x0000)
185 ED FRQCRA, 0x0012453C
|