1LIST "KZM9G low-level initialization routine." 2LIST "Adapted from u-boot KZM9G support code." 3 4LIST "Copyright (C) 2013 Ulrich Hecht" 5 6LIST "This program is free software; you can redistribute it and/or modify" 7LIST "it under the terms of the GNU General Public License version 2 as" 8LIST "published by the Free Software Foundation." 9 10LIST "This program is distributed in the hope that it will be useful," 11LIST "but WITHOUT ANY WARRANTY; without even the implied warranty of" 12LIST "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the" 13LIST "GNU General Public License for more details." 14 15 16LIST "Register definitions:" 17 18LIST "Secure control register" 19#define LIFEC_SEC_SRC (0xE6110008) 20 21LIST "RWDT" 22#define RWDT_BASE (0xE6020000) 23#define RWTCSRA0 (RWDT_BASE + 0x04) 24 25LIST "HPB Semaphore Control Registers" 26#define HPBSCR_BASE (0xE6000000) 27#define HPBCTRL6 (HPBSCR_BASE + 0x1030) 28 29#define SBSC1_BASE (0xFE400000) 30#define SDCR0A (SBSC1_BASE + 0x0008) 31#define SDCR1A (SBSC1_BASE + 0x000C) 32#define SDPCRA (SBSC1_BASE + 0x0010) 33#define SDCR0SA (SBSC1_BASE + 0x0018) 34#define SDCR1SA (SBSC1_BASE + 0x001C) 35#define RTCSRA (SBSC1_BASE + 0x0020) 36#define RTCORA (SBSC1_BASE + 0x0028) 37#define RTCORHA (SBSC1_BASE + 0x002C) 38#define SDWCRC0A (SBSC1_BASE + 0x0040) 39#define SDWCRC1A (SBSC1_BASE + 0x0044) 40#define SDWCR00A (SBSC1_BASE + 0x0048) 41#define SDWCR01A (SBSC1_BASE + 0x004C) 42#define SDWCR10A (SBSC1_BASE + 0x0050) 43#define SDWCR11A (SBSC1_BASE + 0x0054) 44#define SDWCR2A (SBSC1_BASE + 0x0060) 45#define SDWCRC2A (SBSC1_BASE + 0x0064) 46#define ZQCCRA (SBSC1_BASE + 0x0068) 47#define SDMRACR0A (SBSC1_BASE + 0x0084) 48#define SDMRTMPCRA (SBSC1_BASE + 0x008C) 49#define SDMRTMPMSKA (SBSC1_BASE + 0x0094) 50#define SDGENCNTA (SBSC1_BASE + 0x009C) 51#define SDDRVCR0A (SBSC1_BASE + 0x00B4) 52#define DLLCNT0A (SBSC1_BASE + 0x0354) 53 54#define SDMRA1 (0xFE500000) 55#define SDMRA2 (0xFE5C0000) 56#define SDMRA3 (0xFE504000) 57 58#define SBSC2_BASE (0xFB400000) 59#define SDCR0B (SBSC2_BASE + 0x0008) 60#define SDCR1B (SBSC2_BASE + 0x000C) 61#define SDPCRB (SBSC2_BASE + 0x0010) 62#define SDCR0SB (SBSC2_BASE + 0x0018) 63#define SDCR1SB (SBSC2_BASE + 0x001C) 64#define RTCSRB (SBSC2_BASE + 0x0020) 65#define RTCORB (SBSC2_BASE + 0x0028) 66#define RTCORHB (SBSC2_BASE + 0x002C) 67#define SDWCRC0B (SBSC2_BASE + 0x0040) 68#define SDWCRC1B (SBSC2_BASE + 0x0044) 69#define SDWCR00B (SBSC2_BASE + 0x0048) 70#define SDWCR01B (SBSC2_BASE + 0x004C) 71#define SDWCR10B (SBSC2_BASE + 0x0050) 72#define SDWCR11B (SBSC2_BASE + 0x0054) 73#define SDPDCR0B (SBSC2_BASE + 0x0058) 74#define SDWCR2B (SBSC2_BASE + 0x0060) 75#define SDWCRC2B (SBSC2_BASE + 0x0064) 76#define ZQCCRB (SBSC2_BASE + 0x0068) 77#define SDMRACR0B (SBSC2_BASE + 0x0084) 78#define SDMRTMPCRB (SBSC2_BASE + 0x008C) 79#define SDMRTMPMSKB (SBSC2_BASE + 0x0094) 80#define SDGENCNTB (SBSC2_BASE + 0x009C) 81#define DPHYCNT0B (SBSC2_BASE + 0x00A0) 82#define DPHYCNT1B (SBSC2_BASE + 0x00A4) 83#define DPHYCNT2B (SBSC2_BASE + 0x00A8) 84#define SDDRVCR0B (SBSC2_BASE + 0x00B4) 85#define DLLCNT0B (SBSC2_BASE + 0x0354) 86 87#define SDMRB1 (0xFB500000) 88#define SDMRB2 (0xFB5C0000) 89#define SDMRB3 (0xFB504000) 90 91#define CPG_BASE (0xE6150000) 92#define FRQCRA (CPG_BASE + 0x0000) 93#define FRQCRB (CPG_BASE + 0x0004) 94#define FRQCRD (CPG_BASE + 0x00E4) 95#define VCLKCR1 (CPG_BASE + 0x0008) 96#define VCLKCR2 (CPG_BASE + 0x000C) 97#define VCLKCR3 (CPG_BASE + 0x001C) 98#define ZBCKCR (CPG_BASE + 0x0010) 99#define FLCKCR (CPG_BASE + 0x0014) 100#define SD0CKCR (CPG_BASE + 0x0074) 101#define SD1CKCR (CPG_BASE + 0x0078) 102#define SD2CKCR (CPG_BASE + 0x007C) 103#define FSIACKCR (CPG_BASE + 0x0018) 104#define SUBCKCR (CPG_BASE + 0x0080) 105#define SPUACKCR (CPG_BASE + 0x0084) 106#define SPUVCKCR (CPG_BASE + 0x0094) 107#define MSUCKCR (CPG_BASE + 0x0088) 108#define HSICKCR (CPG_BASE + 0x008C) 109#define FSIBCKCR (CPG_BASE + 0x0090) 110#define MFCK1CR (CPG_BASE + 0x0098) 111#define MFCK2CR (CPG_BASE + 0x009C) 112#define DSITCKCR (CPG_BASE + 0x0060) 113#define DSI0PCKCR (CPG_BASE + 0x0064) 114#define DSI1PCKCR (CPG_BASE + 0x0068) 115#define DSI0PHYCR (CPG_BASE + 0x006C) 116#define DVFSCR3 (CPG_BASE + 0x0174) 117#define DVFSCR4 (CPG_BASE + 0x0178) 118#define DVFSCR5 (CPG_BASE + 0x017C) 119#define MPMODE (CPG_BASE + 0x00CC) 120 121#define PLLECR (CPG_BASE + 0x00D0) 122#define PLL0CR (CPG_BASE + 0x00D8) 123#define PLL1CR (CPG_BASE + 0x0028) 124#define PLL2CR (CPG_BASE + 0x002C) 125#define PLL3CR (CPG_BASE + 0x00DC) 126#define PLL0STPCR (CPG_BASE + 0x00F0) 127#define PLL1STPCR (CPG_BASE + 0x00C8) 128#define PLL2STPCR (CPG_BASE + 0x00F8) 129#define PLL3STPCR (CPG_BASE + 0x00FC) 130#define RMSTPCR0 (CPG_BASE + 0x0110) 131#define RMSTPCR1 (CPG_BASE + 0x0114) 132#define RMSTPCR2 (CPG_BASE + 0x0118) 133#define RMSTPCR3 (CPG_BASE + 0x011C) 134#define RMSTPCR4 (CPG_BASE + 0x0120) 135#define RMSTPCR5 (CPG_BASE + 0x0124) 136#define SMSTPCR0 (CPG_BASE + 0x0130) 137#define SMSTPCR2 (CPG_BASE + 0x0138) 138#define SMSTPCR3 (CPG_BASE + 0x013C) 139#define CPGXXCR4 (CPG_BASE + 0x0150) 140#define SRCR0 (CPG_BASE + 0x80A0) 141#define SRCR2 (CPG_BASE + 0x80B0) 142#define SRCR3 (CPG_BASE + 0x80A8) 143#define VREFCR (CPG_BASE + 0x00EC) 144#define PCLKCR (CPG_BASE + 0x1020) 145 146#define PORT32CR (0xE6051020) 147#define PORT33CR (0xE6051021) 148#define PORT34CR (0xE6051022) 149#define PORT35CR (0xE6051023) 150 151LIST "DRAM initialization code:" 152 153EW RWTCSRA0, 0xA507 154 155ED_AND LIFEC_SEC_SRC, 0xFFFF7FFF 156 157ED_AND SMSTPCR3,0xFFFF7FFF 158ED_AND SRCR3, 0xFFFF7FFF 159ED_AND SMSTPCR2,0xFFFBFFFF 160ED_AND SRCR2, 0xFFFBFFFF 161ED PLLECR, 0x00000000 162 163WAIT_MASK PLLECR, 0x00000F00, 0x00000000 164WAIT_MASK FRQCRB, 0x80000000, 0x00000000 165 166ED PLL0CR, 0x2D000000 167ED PLL1CR, 0x17100000 168ED FRQCRB, 0x96235880 169WAIT_MASK FRQCRB, 0x80000000, 0x00000000 170 171ED FLCKCR, 0x0000000B 172ED_AND SMSTPCR0, 0xFFFFFFFD 173 174ED_AND SRCR0, 0xFFFFFFFD 175ED 0xE6001628, 0x514 176ED 0xE6001648, 0x514 177ED 0xE6001658, 0x514 178ED 0xE6001678, 0x514 179 180ED DVFSCR4, 0x00092000 181ED DVFSCR5, 0x000000DC 182ED PLLECR, 0x00000000 183WAIT_MASK PLLECR, 0x00000F00, 0x00000000 184 185ED FRQCRA, 0x0012453C 186ED FRQCRB, 0x80431350 187WAIT_MASK FRQCRB, 0x80000000, 0x00000000 188ED FRQCRD, 0x00000B0B 189WAIT_MASK FRQCRD, 0x80000000, 0x00000000 190 191ED PCLKCR, 0x00000003 192ED VCLKCR1, 0x0000012F 193ED VCLKCR2, 0x00000119 194ED VCLKCR3, 0x00000119 195ED ZBCKCR, 0x00000002 196ED FLCKCR, 0x00000005 197ED SD0CKCR, 0x00000080 198ED SD1CKCR, 0x00000080 199ED SD2CKCR, 0x00000080 200ED FSIACKCR, 0x0000003F 201ED FSIBCKCR, 0x0000003F 202ED SUBCKCR, 0x00000080 203ED SPUACKCR, 0x0000000B 204ED SPUVCKCR, 0x0000000B 205ED MSUCKCR, 0x0000013F 206ED HSICKCR, 0x00000080 207ED MFCK1CR, 0x0000003F 208ED MFCK2CR, 0x0000003F 209ED DSITCKCR, 0x00000107 210ED DSI0PCKCR, 0x00000313 211ED DSI1PCKCR, 0x0000130D 212ED DSI0PHYCR, 0x2A800E0E 213ED PLL0CR, 0x1E000000 214ED PLL0CR, 0x2D000000 215ED PLL1CR, 0x17100000 216ED PLL2CR, 0x27000080 217ED PLL3CR, 0x1D000000 218ED PLL0STPCR, 0x00080000 219ED PLL1STPCR, 0x000120C0 220ED PLL2STPCR, 0x00012000 221ED PLL3STPCR, 0x00000030 222ED PLLECR, 0x0000000B 223WAIT_MASK PLLECR, 0x00000B00, 0x00000B00 224 225ED DVFSCR3, 0x000120F0 226ED MPMODE, 0x00000020 227ED VREFCR, 0x0000028A 228ED RMSTPCR0, 0xE4628087 229ED RMSTPCR1, 0xFFFFFFFF 230ED RMSTPCR2, 0x53FFFFFF 231ED RMSTPCR3, 0xFFFFFFFF 232ED RMSTPCR4, 0x00800D3D 233ED RMSTPCR5, 0xFFFFF3FF 234ED SMSTPCR2, 0x00000000 235ED SRCR2, 0x00040000 236ED_AND PLLECR, 0xFFFFFFF7 237WAIT_MASK PLLECR, 0x00000800, 0x00000000 238 239LIST "set SBSC operational" 240ED HPBCTRL6, 0x00000001 241WAIT_MASK HPBCTRL6, 0x00000001, 0x00000001 242 243LIST "set SBSC operating frequency" 244ED FRQCRD, 0x00001414 245WAIT_MASK FRQCRD, 0x80000000, 0x00000000 246ED PLL3CR, 0x1D000000 247ED_OR PLLECR, 0x00000008 248WAIT_MASK PLLECR, 0x00000800, 0x00000800 249 250LIST "enable DLL oscillation in DDRPHY" 251ED_OR DLLCNT0A, 0x00000002 252 253LIST "wait >= 100 ns" 254ED SDGENCNTA, 0x00000005 255WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 256 257LIST "target LPDDR2 device settings" 258ED SDCR0A, 0xACC90159 259ED SDCR1A, 0x00010059 260ED SDWCRC0A, 0x50874114 261ED SDWCRC1A, 0x33199B37 262ED SDWCRC2A, 0x008F2313 263ED SDWCR00A, 0x31020707 264ED SDWCR01A, 0x0017040A 265ED SDWCR10A, 0x31020707 266ED SDWCR11A, 0x0017040A 267 268ED SDDRVCR0A, 0x055557ff 269 270ED SDWCR2A, 0x30000000 271 272LIST "drive CKE high" 273ED_OR SDPCRA, 0x00000080 274WAIT_MASK SDPCRA, 0x00000080, 0x00000080 275 276LIST "wait >= 200 us" 277ED SDGENCNTA, 0x00002710 278WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 279 280LIST "issue reset command to LPDDR2 device" 281ED SDMRACR0A, 0x0000003F 282ED SDMRA1, 0x00000000 283 284LIST "wait >= 10 (or 1) us (docs inconsistent)" 285ED SDGENCNTA, 0x000001F4 286WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 287 288LIST "MRW ZS initialization calibration command" 289ED SDMRACR0A, 0x0000FF0A 290ED SDMRA3, 0x00000000 291 292LIST "wait >= 1 us" 293ED SDGENCNTA, 0x00000032 294WAIT_MASK SDGENCNTA, 0xFFFFFFFF, 0x00000000 295 296LIST "specify operating mode in LPDDR2" 297ED SDMRACR0A, 0x00002201 298ED SDMRA1, 0x00000000 299ED SDMRACR0A, 0x00000402 300ED SDMRA1, 0x00000000 301ED SDMRACR0A, 0x00000203 302ED SDMRA1, 0x00000000 303 304LIST "initialize DDR interface" 305ED SDMRA2, 0x00000000 306 307LIST "temperature sensor control" 308ED SDMRTMPCRA, 0x88800004 309ED SDMRTMPMSKA,0x00000004 310 311LIST "auto-refreshing control" 312ED RTCORA, 0xA55A0032 313ED RTCORHA, 0xA55A000C 314ED RTCSRA, 0xA55A2048 315 316ED_OR SDCR0A, 0x00000800 317ED_OR SDCR1A, 0x00000400 318 319LIST "auto ZQ calibration control" 320ED ZQCCRA, 0xFFF20000 321 322ED_OR DLLCNT0B, 0x00000002 323ED SDGENCNTB, 0x00000005 324WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 325 326ED SDCR0B, 0xACC90159 327ED SDCR1B, 0x00010059 328ED SDWCRC0B, 0x50874114 329ED SDWCRC1B, 0x33199B37 330ED SDWCRC2B, 0x008F2313 331ED SDWCR00B, 0x31020707 332ED SDWCR01B, 0x0017040A 333ED SDWCR10B, 0x31020707 334ED SDWCR11B, 0x0017040A 335ED SDDRVCR0B, 0x055557ff 336ED SDWCR2B, 0x30000000 337ED_OR SDPCRB, 0x00000080 338WAIT_MASK SDPCRB, 0x00000080, 0x00000080 339 340ED SDGENCNTB, 0x00002710 341WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 342ED SDMRACR0B, 0x0000003F 343 344LIST "upstream u-boot writes to SDMRA1A for both SBSC 1 and 2, which does" 345LIST "not seem to make a lot of sense..." 346ED SDMRB1, 0x00000000 347 348ED SDGENCNTB, 0x000001F4 349WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 350 351ED SDMRACR0B, 0x0000FF0A 352ED SDMRB3, 0x00000000 353ED SDGENCNTB, 0x00000032 354WAIT_MASK SDGENCNTB, 0xFFFFFFFF, 0x00000000 355 356ED SDMRACR0B, 0x00002201 357ED SDMRB1, 0x00000000 358ED SDMRACR0B, 0x00000402 359ED SDMRB1, 0x00000000 360ED SDMRACR0B, 0x00000203 361ED SDMRB1, 0x00000000 362ED SDMRB2, 0x00000000 363ED SDMRTMPCRB, 0x88800004 364ED SDMRTMPMSKB, 0x00000004 365ED RTCORB, 0xA55A0032 366ED RTCORHB, 0xA55A000C 367ED RTCSRB, 0xA55A2048 368ED_OR SDCR0B, 0x00000800 369ED_OR SDCR1B, 0x00000400 370ED ZQCCRB, 0xFFF20000 371ED_OR SDPDCR0B, 0x00030000 372ED DPHYCNT1B, 0xA5390000 373ED DPHYCNT0B, 0x00001200 374ED DPHYCNT1B, 0x07CE0000 375ED DPHYCNT0B, 0x00001247 376WAIT_MASK DPHYCNT2B, 0xFFFFFFFF, 0x07CE0000 377 378ED_AND SDPDCR0B, 0xFFFCFFFF 379 380ED FRQCRD, 0x00000B0B 381WAIT_MASK FRQCRD, 0x80000000, 0x00000000 382 383ED CPGXXCR4, 0xfffffffc 384 385LIST "Setup SCIF4 / workaround" 386EB PORT32CR, 0x12 387EB PORT33CR, 0x22 388EB PORT34CR, 0x12 389EB PORT35CR, 0x22 390 391EW 0xE6C80000, 0 392EB 0xE6C80004, 0x19 393EW 0xE6C80008, 0x0030 394EW 0xE6C80018, 0 395EW 0xE6C80030, 0x0014 396 397LIST "Magic to avoid hangs and corruption on DRAM writes." 398 399LIST "It has been observed that the system would most often hang while" 400LIST "decompressing the kernel, and if it didn't it would always write" 401LIST "a corrupt image to DRAM." 402LIST "This problem does not occur in u-boot, and the reason is that" 403LIST "u-boot performs an additional cache invalidation after setting up" 404LIST "the DRAM controller. Such an invalidation should not be necessary at" 405LIST "this point, and attempts at removing parts of the routine to arrive" 406LIST "at the minimal snippet of code necessary to avoid the DRAM stability" 407LIST "problem yielded the following:" 408 409MRC p15, 0, r0, c1, c0, 0 410MCR p15, 0, r0, c1, c0, 0 411