Home
last modified time | relevance | path

Searched refs:FRQCRB (Results 1 – 7 of 7) sorted by relevance

/arch/arm/mach-shmobile/
Dclock-sh73a0.c29 #define FRQCRB IOMEM(0xe6150004) macro
195 __raw_writel(__raw_readl(FRQCRB) | (1 << 31), FRQCRB); in frqcr_kick()
197 if (__raw_readl(FRQCRB) & (1 << 31)) in frqcr_kick()
241 [DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
242 [DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
243 [DIV4_HP] = DIV4(FRQCRB, 4, 0xdff, 0),
270 if (readl(FRQCRB) & (1 << 31)) in zclk_set_rate()
275 __raw_writel(__raw_readl(FRQCRB) & ~(1 << 28), FRQCRB); in zclk_set_rate()
284 __raw_writel(__raw_readl(FRQCRB) | (1 << 28), FRQCRB); in zclk_set_rate()
321 if (__raw_readl(FRQCRB) & (1 << 28)) in zclk_recalc()
[all …]
Dclock-r8a73a4.c37 #define FRQCRB 0xE6150004 macro
196 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31)); in frqcr_kick_check()
204 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB)); in frqcr_kick_do()
206 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31)) in frqcr_kick_do()
323 .enable_reg = (void __iomem *)FRQCRB,
338 .enable_reg = (void __iomem *)FRQCRB,
395 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
396 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
397 [DIV4_HP] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 4, 0x0dff, 0),
Dclock-sh7372.c29 #define FRQCRB IOMEM(0xe6150004) macro
297 value = __raw_readl(FRQCRB); in div4_kick()
299 __raw_writel(value, FRQCRB); in div4_kick()
329 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
330 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
Dclock-r8a7740.c47 #define FRQCRB IOMEM(0xe6150004) macro
297 value = __raw_readl(FRQCRB); in div4_kick()
299 __raw_writel(value, FRQCRB); in div4_kick()
326 [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
/arch/sh/include/cpu-sh4/cpu/
Dfreq.h34 #define FRQCRB 0xa4150004 macro
/arch/arm/mach-shmobile/include/mach/
Dhead-kzm9g.txt93 #define FRQCRB (CPG_BASE + 0x0004)
164 WAIT_MASK FRQCRB, 0x80000000, 0x00000000
168 ED FRQCRB, 0x96235880
169 WAIT_MASK FRQCRB, 0x80000000, 0x00000000
186 ED FRQCRB, 0x80431350
187 WAIT_MASK FRQCRB, 0x80000000, 0x00000000
/arch/sh/kernel/cpu/sh4a/
Dclock-sh7724.c32 #define FRQCRB 0xa4150004 macro
170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),