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Searched refs:MIPS_CPU_RW_LLB (Results 1 – 3 of 3) sorted by relevance

/arch/mips/include/asm/
Dcpu.h378 #define MIPS_CPU_RW_LLB 0x1000000000ull /* LLADDR/LLB writes are allowed */ macro
Dcpu-features.h45 #define cpu_has_rw_llb (cpu_data[0].options & MIPS_CPU_RW_LLB)
/arch/mips/kernel/
Dcpu-probe.c621 c->options |= MIPS_CPU_RW_LLB; in decode_config5()