1 /*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
20
21 #include <asm/bugs.h>
22 #include <asm/cpu.h>
23 #include <asm/cpu-features.h>
24 #include <asm/cpu-type.h>
25 #include <asm/fpu.h>
26 #include <asm/mipsregs.h>
27 #include <asm/mipsmtregs.h>
28 #include <asm/msa.h>
29 #include <asm/watch.h>
30 #include <asm/elf.h>
31 #include <asm/pgtable-bits.h>
32 #include <asm/spram.h>
33 #include <asm/uaccess.h>
34
35 /*
36 * Get the FPU Implementation/Revision.
37 */
cpu_get_fpu_id(void)38 static inline unsigned long cpu_get_fpu_id(void)
39 {
40 unsigned long tmp, fpu_id;
41
42 tmp = read_c0_status();
43 __enable_fpu(FPU_AS_IS);
44 fpu_id = read_32bit_cp1_register(CP1_REVISION);
45 write_c0_status(tmp);
46 return fpu_id;
47 }
48
49 /*
50 * Check if the CPU has an external FPU.
51 */
__cpu_has_fpu(void)52 static inline int __cpu_has_fpu(void)
53 {
54 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
55 }
56
cpu_get_msa_id(void)57 static inline unsigned long cpu_get_msa_id(void)
58 {
59 unsigned long status, msa_id;
60
61 status = read_c0_status();
62 __enable_fpu(FPU_64BIT);
63 enable_msa();
64 msa_id = read_msa_ir();
65 disable_msa();
66 write_c0_status(status);
67 return msa_id;
68 }
69
70 /*
71 * Determine the FCSR mask for FPU hardware.
72 */
cpu_set_fpu_fcsr_mask(struct cpuinfo_mips * c)73 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
74 {
75 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
76
77 fcsr = c->fpu_csr31;
78 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
79
80 sr = read_c0_status();
81 __enable_fpu(FPU_AS_IS);
82
83 fcsr0 = fcsr & mask;
84 write_32bit_cp1_register(CP1_STATUS, fcsr0);
85 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
86
87 fcsr1 = fcsr | ~mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr1);
89 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
90
91 write_32bit_cp1_register(CP1_STATUS, fcsr);
92
93 write_c0_status(sr);
94
95 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
96 }
97
98 /*
99 * Set the FIR feature flags for the FPU emulator.
100 */
cpu_set_nofpu_id(struct cpuinfo_mips * c)101 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
102 {
103 u32 value;
104
105 value = 0;
106 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
107 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
108 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
109 value |= MIPS_FPIR_D | MIPS_FPIR_S;
110 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
111 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
112 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
113 if (c->options & MIPS_CPU_NAN_2008)
114 value |= MIPS_FPIR_HAS2008;
115 c->fpu_id = value;
116 }
117
118 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
119 static unsigned int mips_nofpu_msk31;
120
121 /*
122 * Set options for FPU hardware.
123 */
cpu_set_fpu_opts(struct cpuinfo_mips * c)124 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
125 {
126 c->fpu_id = cpu_get_fpu_id();
127 mips_nofpu_msk31 = c->fpu_msk31;
128
129 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
130 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
131 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
132 if (c->fpu_id & MIPS_FPIR_3D)
133 c->ases |= MIPS_ASE_MIPS3D;
134 if (c->fpu_id & MIPS_FPIR_FREP)
135 c->options |= MIPS_CPU_FRE;
136 }
137
138 cpu_set_fpu_fcsr_mask(c);
139 c->options |= MIPS_CPU_NAN_LEGACY;
140 }
141
142 /*
143 * Set options for the FPU emulator.
144 */
cpu_set_nofpu_opts(struct cpuinfo_mips * c)145 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
146 {
147 c->options &= ~MIPS_CPU_FPU;
148 c->fpu_msk31 = mips_nofpu_msk31;
149
150 c->options |= MIPS_CPU_NAN_LEGACY;
151 cpu_set_nofpu_id(c);
152 }
153
154 static int mips_fpu_disabled;
155
fpu_disable(char * s)156 static int __init fpu_disable(char *s)
157 {
158 cpu_set_nofpu_opts(&boot_cpu_data);
159 mips_fpu_disabled = 1;
160
161 return 1;
162 }
163
164 __setup("nofpu", fpu_disable);
165
166 int mips_dsp_disabled;
167
dsp_disable(char * s)168 static int __init dsp_disable(char *s)
169 {
170 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
171 mips_dsp_disabled = 1;
172
173 return 1;
174 }
175
176 __setup("nodsp", dsp_disable);
177
178 static int mips_htw_disabled;
179
htw_disable(char * s)180 static int __init htw_disable(char *s)
181 {
182 mips_htw_disabled = 1;
183 cpu_data[0].options &= ~MIPS_CPU_HTW;
184 write_c0_pwctl(read_c0_pwctl() &
185 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
186
187 return 1;
188 }
189
190 __setup("nohtw", htw_disable);
191
192 static int mips_ftlb_disabled;
193 static int mips_has_ftlb_configured;
194
195 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable);
196
ftlb_disable(char * s)197 static int __init ftlb_disable(char *s)
198 {
199 unsigned int config4, mmuextdef;
200
201 /*
202 * If the core hasn't done any FTLB configuration, there is nothing
203 * for us to do here.
204 */
205 if (!mips_has_ftlb_configured)
206 return 1;
207
208 /* Disable it in the boot cpu */
209 set_ftlb_enable(&cpu_data[0], 0);
210
211 back_to_back_c0_hazard();
212
213 config4 = read_c0_config4();
214
215 /* Check that FTLB has been disabled */
216 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
217 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
218 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
219 /* This should never happen */
220 pr_warn("FTLB could not be disabled!\n");
221 return 1;
222 }
223
224 mips_ftlb_disabled = 1;
225 mips_has_ftlb_configured = 0;
226
227 /*
228 * noftlb is mainly used for debug purposes so print
229 * an informative message instead of using pr_debug()
230 */
231 pr_info("FTLB has been disabled\n");
232
233 /*
234 * Some of these bits are duplicated in the decode_config4.
235 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
236 * once FTLB has been disabled so undo what decode_config4 did.
237 */
238 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
239 cpu_data[0].tlbsizeftlbsets;
240 cpu_data[0].tlbsizeftlbsets = 0;
241 cpu_data[0].tlbsizeftlbways = 0;
242
243 return 1;
244 }
245
246 __setup("noftlb", ftlb_disable);
247
248
check_errata(void)249 static inline void check_errata(void)
250 {
251 struct cpuinfo_mips *c = ¤t_cpu_data;
252
253 switch (current_cpu_type()) {
254 case CPU_34K:
255 /*
256 * Erratum "RPS May Cause Incorrect Instruction Execution"
257 * This code only handles VPE0, any SMP/RTOS code
258 * making use of VPE1 will be responsable for that VPE.
259 */
260 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
261 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
262 break;
263 default:
264 break;
265 }
266 }
267
check_bugs32(void)268 void __init check_bugs32(void)
269 {
270 check_errata();
271 }
272
273 /*
274 * Probe whether cpu has config register by trying to play with
275 * alternate cache bit and see whether it matters.
276 * It's used by cpu_probe to distinguish between R3000A and R3081.
277 */
cpu_has_confreg(void)278 static inline int cpu_has_confreg(void)
279 {
280 #ifdef CONFIG_CPU_R3000
281 extern unsigned long r3k_cache_size(unsigned long);
282 unsigned long size1, size2;
283 unsigned long cfg = read_c0_conf();
284
285 size1 = r3k_cache_size(ST0_ISC);
286 write_c0_conf(cfg ^ R30XX_CONF_AC);
287 size2 = r3k_cache_size(ST0_ISC);
288 write_c0_conf(cfg);
289 return size1 != size2;
290 #else
291 return 0;
292 #endif
293 }
294
set_elf_platform(int cpu,const char * plat)295 static inline void set_elf_platform(int cpu, const char *plat)
296 {
297 if (cpu == 0)
298 __elf_platform = plat;
299 }
300
cpu_probe_vmbits(struct cpuinfo_mips * c)301 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
302 {
303 #ifdef __NEED_VMBITS_PROBE
304 write_c0_entryhi(0x3fffffffffffe000ULL);
305 back_to_back_c0_hazard();
306 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
307 #endif
308 }
309
set_isa(struct cpuinfo_mips * c,unsigned int isa)310 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
311 {
312 switch (isa) {
313 case MIPS_CPU_ISA_M64R2:
314 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
315 case MIPS_CPU_ISA_M64R1:
316 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
317 case MIPS_CPU_ISA_V:
318 c->isa_level |= MIPS_CPU_ISA_V;
319 case MIPS_CPU_ISA_IV:
320 c->isa_level |= MIPS_CPU_ISA_IV;
321 case MIPS_CPU_ISA_III:
322 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
323 break;
324
325 /* R6 incompatible with everything else */
326 case MIPS_CPU_ISA_M64R6:
327 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
328 case MIPS_CPU_ISA_M32R6:
329 c->isa_level |= MIPS_CPU_ISA_M32R6;
330 /* Break here so we don't add incompatible ISAs */
331 break;
332 case MIPS_CPU_ISA_M32R2:
333 c->isa_level |= MIPS_CPU_ISA_M32R2;
334 case MIPS_CPU_ISA_M32R1:
335 c->isa_level |= MIPS_CPU_ISA_M32R1;
336 case MIPS_CPU_ISA_II:
337 c->isa_level |= MIPS_CPU_ISA_II;
338 break;
339 }
340 }
341
342 static char unknown_isa[] = KERN_ERR \
343 "Unsupported ISA type, c0.config0: %d.";
344
calculate_ftlb_probability(struct cpuinfo_mips * c)345 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
346 {
347
348 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
349
350 /*
351 * 0 = All TLBWR instructions go to FTLB
352 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
353 * FTLB and 1 goes to the VTLB.
354 * 2 = 7:1: As above with 7:1 ratio.
355 * 3 = 3:1: As above with 3:1 ratio.
356 *
357 * Use the linear midpoint as the probability threshold.
358 */
359 if (probability >= 12)
360 return 1;
361 else if (probability >= 6)
362 return 2;
363 else
364 /*
365 * So FTLB is less than 4 times bigger than VTLB.
366 * A 3:1 ratio can still be useful though.
367 */
368 return 3;
369 }
370
set_ftlb_enable(struct cpuinfo_mips * c,int enable)371 static void set_ftlb_enable(struct cpuinfo_mips *c, int enable)
372 {
373 unsigned int config6;
374
375 /* It's implementation dependent how the FTLB can be enabled */
376 switch (c->cputype) {
377 case CPU_PROAPTIV:
378 case CPU_P5600:
379 /* proAptiv & related cores use Config6 to enable the FTLB */
380 config6 = read_c0_config6();
381 /* Clear the old probability value */
382 config6 &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
383 if (enable)
384 /* Enable FTLB */
385 write_c0_config6(config6 |
386 (calculate_ftlb_probability(c)
387 << MIPS_CONF6_FTLBP_SHIFT)
388 | MIPS_CONF6_FTLBEN);
389 else
390 /* Disable FTLB */
391 write_c0_config6(config6 & ~MIPS_CONF6_FTLBEN);
392 back_to_back_c0_hazard();
393 break;
394 }
395 }
396
decode_config0(struct cpuinfo_mips * c)397 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
398 {
399 unsigned int config0;
400 int isa, mt;
401
402 config0 = read_c0_config();
403
404 /*
405 * Look for Standard TLB or Dual VTLB and FTLB
406 */
407 mt = config0 & MIPS_CONF_MT;
408 if (mt == MIPS_CONF_MT_TLB)
409 c->options |= MIPS_CPU_TLB;
410 else if (mt == MIPS_CONF_MT_FTLB)
411 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
412
413 isa = (config0 & MIPS_CONF_AT) >> 13;
414 switch (isa) {
415 case 0:
416 switch ((config0 & MIPS_CONF_AR) >> 10) {
417 case 0:
418 set_isa(c, MIPS_CPU_ISA_M32R1);
419 break;
420 case 1:
421 set_isa(c, MIPS_CPU_ISA_M32R2);
422 break;
423 case 2:
424 set_isa(c, MIPS_CPU_ISA_M32R6);
425 break;
426 default:
427 goto unknown;
428 }
429 break;
430 case 2:
431 switch ((config0 & MIPS_CONF_AR) >> 10) {
432 case 0:
433 set_isa(c, MIPS_CPU_ISA_M64R1);
434 break;
435 case 1:
436 set_isa(c, MIPS_CPU_ISA_M64R2);
437 break;
438 case 2:
439 set_isa(c, MIPS_CPU_ISA_M64R6);
440 break;
441 default:
442 goto unknown;
443 }
444 break;
445 default:
446 goto unknown;
447 }
448
449 return config0 & MIPS_CONF_M;
450
451 unknown:
452 panic(unknown_isa, config0);
453 }
454
decode_config1(struct cpuinfo_mips * c)455 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
456 {
457 unsigned int config1;
458
459 config1 = read_c0_config1();
460
461 if (config1 & MIPS_CONF1_MD)
462 c->ases |= MIPS_ASE_MDMX;
463 if (config1 & MIPS_CONF1_WR)
464 c->options |= MIPS_CPU_WATCH;
465 if (config1 & MIPS_CONF1_CA)
466 c->ases |= MIPS_ASE_MIPS16;
467 if (config1 & MIPS_CONF1_EP)
468 c->options |= MIPS_CPU_EJTAG;
469 if (config1 & MIPS_CONF1_FP) {
470 c->options |= MIPS_CPU_FPU;
471 c->options |= MIPS_CPU_32FPR;
472 }
473 if (cpu_has_tlb) {
474 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
475 c->tlbsizevtlb = c->tlbsize;
476 c->tlbsizeftlbsets = 0;
477 }
478
479 return config1 & MIPS_CONF_M;
480 }
481
decode_config2(struct cpuinfo_mips * c)482 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
483 {
484 unsigned int config2;
485
486 config2 = read_c0_config2();
487
488 if (config2 & MIPS_CONF2_SL)
489 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
490
491 return config2 & MIPS_CONF_M;
492 }
493
decode_config3(struct cpuinfo_mips * c)494 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
495 {
496 unsigned int config3;
497
498 config3 = read_c0_config3();
499
500 if (config3 & MIPS_CONF3_SM) {
501 c->ases |= MIPS_ASE_SMARTMIPS;
502 c->options |= MIPS_CPU_RIXI;
503 }
504 if (config3 & MIPS_CONF3_RXI)
505 c->options |= MIPS_CPU_RIXI;
506 if (config3 & MIPS_CONF3_DSP)
507 c->ases |= MIPS_ASE_DSP;
508 if (config3 & MIPS_CONF3_DSP2P)
509 c->ases |= MIPS_ASE_DSP2P;
510 if (config3 & MIPS_CONF3_VINT)
511 c->options |= MIPS_CPU_VINT;
512 if (config3 & MIPS_CONF3_VEIC)
513 c->options |= MIPS_CPU_VEIC;
514 if (config3 & MIPS_CONF3_MT)
515 c->ases |= MIPS_ASE_MIPSMT;
516 if (config3 & MIPS_CONF3_ULRI)
517 c->options |= MIPS_CPU_ULRI;
518 if (config3 & MIPS_CONF3_ISA)
519 c->options |= MIPS_CPU_MICROMIPS;
520 if (config3 & MIPS_CONF3_VZ)
521 c->ases |= MIPS_ASE_VZ;
522 if (config3 & MIPS_CONF3_SC)
523 c->options |= MIPS_CPU_SEGMENTS;
524 if (config3 & MIPS_CONF3_MSA)
525 c->ases |= MIPS_ASE_MSA;
526 /* Only tested on 32-bit cores */
527 if ((config3 & MIPS_CONF3_PW) && config_enabled(CONFIG_32BIT)) {
528 c->htw_seq = 0;
529 c->options |= MIPS_CPU_HTW;
530 }
531 if (config3 & MIPS_CONF3_CDMM)
532 c->options |= MIPS_CPU_CDMM;
533 if (config3 & MIPS_CONF3_SP)
534 c->options |= MIPS_CPU_SP;
535
536 return config3 & MIPS_CONF_M;
537 }
538
decode_config4(struct cpuinfo_mips * c)539 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
540 {
541 unsigned int config4;
542 unsigned int newcf4;
543 unsigned int mmuextdef;
544 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
545
546 config4 = read_c0_config4();
547
548 if (cpu_has_tlb) {
549 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
550 c->options |= MIPS_CPU_TLBINV;
551
552 /*
553 * R6 has dropped the MMUExtDef field from config4.
554 * On R6 the fields always describe the FTLB, and only if it is
555 * present according to Config.MT.
556 */
557 if (!cpu_has_mips_r6)
558 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
559 else if (cpu_has_ftlb)
560 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
561 else
562 mmuextdef = 0;
563
564 switch (mmuextdef) {
565 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
566 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
567 c->tlbsizevtlb = c->tlbsize;
568 break;
569 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
570 c->tlbsizevtlb +=
571 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
572 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
573 c->tlbsize = c->tlbsizevtlb;
574 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
575 /* fall through */
576 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
577 if (mips_ftlb_disabled)
578 break;
579 newcf4 = (config4 & ~ftlb_page) |
580 (page_size_ftlb(mmuextdef) <<
581 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
582 write_c0_config4(newcf4);
583 back_to_back_c0_hazard();
584 config4 = read_c0_config4();
585 if (config4 != newcf4) {
586 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
587 PAGE_SIZE, config4);
588 /* Switch FTLB off */
589 set_ftlb_enable(c, 0);
590 break;
591 }
592 c->tlbsizeftlbsets = 1 <<
593 ((config4 & MIPS_CONF4_FTLBSETS) >>
594 MIPS_CONF4_FTLBSETS_SHIFT);
595 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
596 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
597 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
598 mips_has_ftlb_configured = 1;
599 break;
600 }
601 }
602
603 c->kscratch_mask = (config4 >> 16) & 0xff;
604
605 return config4 & MIPS_CONF_M;
606 }
607
decode_config5(struct cpuinfo_mips * c)608 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
609 {
610 unsigned int config5;
611
612 config5 = read_c0_config5();
613 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
614 write_c0_config5(config5);
615
616 if (config5 & MIPS_CONF5_EVA)
617 c->options |= MIPS_CPU_EVA;
618 if (config5 & MIPS_CONF5_MRP)
619 c->options |= MIPS_CPU_MAAR;
620 if (config5 & MIPS_CONF5_LLB)
621 c->options |= MIPS_CPU_RW_LLB;
622 #ifdef CONFIG_XPA
623 if (config5 & MIPS_CONF5_MVH)
624 c->options |= MIPS_CPU_XPA;
625 #endif
626
627 return config5 & MIPS_CONF_M;
628 }
629
decode_configs(struct cpuinfo_mips * c)630 static void decode_configs(struct cpuinfo_mips *c)
631 {
632 int ok;
633
634 /* MIPS32 or MIPS64 compliant CPU. */
635 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
636 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
637
638 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
639
640 /* Enable FTLB if present and not disabled */
641 set_ftlb_enable(c, !mips_ftlb_disabled);
642
643 ok = decode_config0(c); /* Read Config registers. */
644 BUG_ON(!ok); /* Arch spec violation! */
645 if (ok)
646 ok = decode_config1(c);
647 if (ok)
648 ok = decode_config2(c);
649 if (ok)
650 ok = decode_config3(c);
651 if (ok)
652 ok = decode_config4(c);
653 if (ok)
654 ok = decode_config5(c);
655
656 mips_probe_watch_registers(c);
657
658 if (cpu_has_rixi) {
659 /* Enable the RIXI exceptions */
660 set_c0_pagegrain(PG_IEC);
661 back_to_back_c0_hazard();
662 /* Verify the IEC bit is set */
663 if (read_c0_pagegrain() & PG_IEC)
664 c->options |= MIPS_CPU_RIXIEX;
665 }
666
667 #ifndef CONFIG_MIPS_CPS
668 if (cpu_has_mips_r2_r6) {
669 c->core = get_ebase_cpunum();
670 if (cpu_has_mipsmt)
671 c->core >>= fls(core_nvpes()) - 1;
672 }
673 #endif
674 }
675
676 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
677 | MIPS_CPU_COUNTER)
678
cpu_probe_legacy(struct cpuinfo_mips * c,unsigned int cpu)679 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
680 {
681 switch (c->processor_id & PRID_IMP_MASK) {
682 case PRID_IMP_R2000:
683 c->cputype = CPU_R2000;
684 __cpu_name[cpu] = "R2000";
685 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
686 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
687 MIPS_CPU_NOFPUEX;
688 if (__cpu_has_fpu())
689 c->options |= MIPS_CPU_FPU;
690 c->tlbsize = 64;
691 break;
692 case PRID_IMP_R3000:
693 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
694 if (cpu_has_confreg()) {
695 c->cputype = CPU_R3081E;
696 __cpu_name[cpu] = "R3081";
697 } else {
698 c->cputype = CPU_R3000A;
699 __cpu_name[cpu] = "R3000A";
700 }
701 } else {
702 c->cputype = CPU_R3000;
703 __cpu_name[cpu] = "R3000";
704 }
705 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
706 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
707 MIPS_CPU_NOFPUEX;
708 if (__cpu_has_fpu())
709 c->options |= MIPS_CPU_FPU;
710 c->tlbsize = 64;
711 break;
712 case PRID_IMP_R4000:
713 if (read_c0_config() & CONF_SC) {
714 if ((c->processor_id & PRID_REV_MASK) >=
715 PRID_REV_R4400) {
716 c->cputype = CPU_R4400PC;
717 __cpu_name[cpu] = "R4400PC";
718 } else {
719 c->cputype = CPU_R4000PC;
720 __cpu_name[cpu] = "R4000PC";
721 }
722 } else {
723 int cca = read_c0_config() & CONF_CM_CMASK;
724 int mc;
725
726 /*
727 * SC and MC versions can't be reliably told apart,
728 * but only the latter support coherent caching
729 * modes so assume the firmware has set the KSEG0
730 * coherency attribute reasonably (if uncached, we
731 * assume SC).
732 */
733 switch (cca) {
734 case CONF_CM_CACHABLE_CE:
735 case CONF_CM_CACHABLE_COW:
736 case CONF_CM_CACHABLE_CUW:
737 mc = 1;
738 break;
739 default:
740 mc = 0;
741 break;
742 }
743 if ((c->processor_id & PRID_REV_MASK) >=
744 PRID_REV_R4400) {
745 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
746 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
747 } else {
748 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
749 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
750 }
751 }
752
753 set_isa(c, MIPS_CPU_ISA_III);
754 c->fpu_msk31 |= FPU_CSR_CONDX;
755 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
756 MIPS_CPU_WATCH | MIPS_CPU_VCE |
757 MIPS_CPU_LLSC;
758 c->tlbsize = 48;
759 break;
760 case PRID_IMP_VR41XX:
761 set_isa(c, MIPS_CPU_ISA_III);
762 c->fpu_msk31 |= FPU_CSR_CONDX;
763 c->options = R4K_OPTS;
764 c->tlbsize = 32;
765 switch (c->processor_id & 0xf0) {
766 case PRID_REV_VR4111:
767 c->cputype = CPU_VR4111;
768 __cpu_name[cpu] = "NEC VR4111";
769 break;
770 case PRID_REV_VR4121:
771 c->cputype = CPU_VR4121;
772 __cpu_name[cpu] = "NEC VR4121";
773 break;
774 case PRID_REV_VR4122:
775 if ((c->processor_id & 0xf) < 0x3) {
776 c->cputype = CPU_VR4122;
777 __cpu_name[cpu] = "NEC VR4122";
778 } else {
779 c->cputype = CPU_VR4181A;
780 __cpu_name[cpu] = "NEC VR4181A";
781 }
782 break;
783 case PRID_REV_VR4130:
784 if ((c->processor_id & 0xf) < 0x4) {
785 c->cputype = CPU_VR4131;
786 __cpu_name[cpu] = "NEC VR4131";
787 } else {
788 c->cputype = CPU_VR4133;
789 c->options |= MIPS_CPU_LLSC;
790 __cpu_name[cpu] = "NEC VR4133";
791 }
792 break;
793 default:
794 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
795 c->cputype = CPU_VR41XX;
796 __cpu_name[cpu] = "NEC Vr41xx";
797 break;
798 }
799 break;
800 case PRID_IMP_R4300:
801 c->cputype = CPU_R4300;
802 __cpu_name[cpu] = "R4300";
803 set_isa(c, MIPS_CPU_ISA_III);
804 c->fpu_msk31 |= FPU_CSR_CONDX;
805 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
806 MIPS_CPU_LLSC;
807 c->tlbsize = 32;
808 break;
809 case PRID_IMP_R4600:
810 c->cputype = CPU_R4600;
811 __cpu_name[cpu] = "R4600";
812 set_isa(c, MIPS_CPU_ISA_III);
813 c->fpu_msk31 |= FPU_CSR_CONDX;
814 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
815 MIPS_CPU_LLSC;
816 c->tlbsize = 48;
817 break;
818 #if 0
819 case PRID_IMP_R4650:
820 /*
821 * This processor doesn't have an MMU, so it's not
822 * "real easy" to run Linux on it. It is left purely
823 * for documentation. Commented out because it shares
824 * it's c0_prid id number with the TX3900.
825 */
826 c->cputype = CPU_R4650;
827 __cpu_name[cpu] = "R4650";
828 set_isa(c, MIPS_CPU_ISA_III);
829 c->fpu_msk31 |= FPU_CSR_CONDX;
830 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
831 c->tlbsize = 48;
832 break;
833 #endif
834 case PRID_IMP_TX39:
835 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
836 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
837
838 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
839 c->cputype = CPU_TX3927;
840 __cpu_name[cpu] = "TX3927";
841 c->tlbsize = 64;
842 } else {
843 switch (c->processor_id & PRID_REV_MASK) {
844 case PRID_REV_TX3912:
845 c->cputype = CPU_TX3912;
846 __cpu_name[cpu] = "TX3912";
847 c->tlbsize = 32;
848 break;
849 case PRID_REV_TX3922:
850 c->cputype = CPU_TX3922;
851 __cpu_name[cpu] = "TX3922";
852 c->tlbsize = 64;
853 break;
854 }
855 }
856 break;
857 case PRID_IMP_R4700:
858 c->cputype = CPU_R4700;
859 __cpu_name[cpu] = "R4700";
860 set_isa(c, MIPS_CPU_ISA_III);
861 c->fpu_msk31 |= FPU_CSR_CONDX;
862 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
863 MIPS_CPU_LLSC;
864 c->tlbsize = 48;
865 break;
866 case PRID_IMP_TX49:
867 c->cputype = CPU_TX49XX;
868 __cpu_name[cpu] = "R49XX";
869 set_isa(c, MIPS_CPU_ISA_III);
870 c->fpu_msk31 |= FPU_CSR_CONDX;
871 c->options = R4K_OPTS | MIPS_CPU_LLSC;
872 if (!(c->processor_id & 0x08))
873 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
874 c->tlbsize = 48;
875 break;
876 case PRID_IMP_R5000:
877 c->cputype = CPU_R5000;
878 __cpu_name[cpu] = "R5000";
879 set_isa(c, MIPS_CPU_ISA_IV);
880 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
881 MIPS_CPU_LLSC;
882 c->tlbsize = 48;
883 break;
884 case PRID_IMP_R5432:
885 c->cputype = CPU_R5432;
886 __cpu_name[cpu] = "R5432";
887 set_isa(c, MIPS_CPU_ISA_IV);
888 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
889 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
890 c->tlbsize = 48;
891 break;
892 case PRID_IMP_R5500:
893 c->cputype = CPU_R5500;
894 __cpu_name[cpu] = "R5500";
895 set_isa(c, MIPS_CPU_ISA_IV);
896 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
897 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
898 c->tlbsize = 48;
899 break;
900 case PRID_IMP_NEVADA:
901 c->cputype = CPU_NEVADA;
902 __cpu_name[cpu] = "Nevada";
903 set_isa(c, MIPS_CPU_ISA_IV);
904 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
905 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
906 c->tlbsize = 48;
907 break;
908 case PRID_IMP_R6000:
909 c->cputype = CPU_R6000;
910 __cpu_name[cpu] = "R6000";
911 set_isa(c, MIPS_CPU_ISA_II);
912 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
913 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
914 MIPS_CPU_LLSC;
915 c->tlbsize = 32;
916 break;
917 case PRID_IMP_R6000A:
918 c->cputype = CPU_R6000A;
919 __cpu_name[cpu] = "R6000A";
920 set_isa(c, MIPS_CPU_ISA_II);
921 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
922 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
923 MIPS_CPU_LLSC;
924 c->tlbsize = 32;
925 break;
926 case PRID_IMP_RM7000:
927 c->cputype = CPU_RM7000;
928 __cpu_name[cpu] = "RM7000";
929 set_isa(c, MIPS_CPU_ISA_IV);
930 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
931 MIPS_CPU_LLSC;
932 /*
933 * Undocumented RM7000: Bit 29 in the info register of
934 * the RM7000 v2.0 indicates if the TLB has 48 or 64
935 * entries.
936 *
937 * 29 1 => 64 entry JTLB
938 * 0 => 48 entry JTLB
939 */
940 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
941 break;
942 case PRID_IMP_R8000:
943 c->cputype = CPU_R8000;
944 __cpu_name[cpu] = "RM8000";
945 set_isa(c, MIPS_CPU_ISA_IV);
946 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
947 MIPS_CPU_FPU | MIPS_CPU_32FPR |
948 MIPS_CPU_LLSC;
949 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
950 break;
951 case PRID_IMP_R10000:
952 c->cputype = CPU_R10000;
953 __cpu_name[cpu] = "R10000";
954 set_isa(c, MIPS_CPU_ISA_IV);
955 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
956 MIPS_CPU_FPU | MIPS_CPU_32FPR |
957 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
958 MIPS_CPU_LLSC;
959 c->tlbsize = 64;
960 break;
961 case PRID_IMP_R12000:
962 c->cputype = CPU_R12000;
963 __cpu_name[cpu] = "R12000";
964 set_isa(c, MIPS_CPU_ISA_IV);
965 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
966 MIPS_CPU_FPU | MIPS_CPU_32FPR |
967 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
968 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
969 c->tlbsize = 64;
970 break;
971 case PRID_IMP_R14000:
972 c->cputype = CPU_R14000;
973 __cpu_name[cpu] = "R14000";
974 set_isa(c, MIPS_CPU_ISA_IV);
975 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
976 MIPS_CPU_FPU | MIPS_CPU_32FPR |
977 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
978 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
979 c->tlbsize = 64;
980 break;
981 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
982 switch (c->processor_id & PRID_REV_MASK) {
983 case PRID_REV_LOONGSON2E:
984 c->cputype = CPU_LOONGSON2;
985 __cpu_name[cpu] = "ICT Loongson-2";
986 set_elf_platform(cpu, "loongson2e");
987 set_isa(c, MIPS_CPU_ISA_III);
988 c->fpu_msk31 |= FPU_CSR_CONDX;
989 break;
990 case PRID_REV_LOONGSON2F:
991 c->cputype = CPU_LOONGSON2;
992 __cpu_name[cpu] = "ICT Loongson-2";
993 set_elf_platform(cpu, "loongson2f");
994 set_isa(c, MIPS_CPU_ISA_III);
995 c->fpu_msk31 |= FPU_CSR_CONDX;
996 break;
997 case PRID_REV_LOONGSON3A:
998 c->cputype = CPU_LOONGSON3;
999 __cpu_name[cpu] = "ICT Loongson-3";
1000 set_elf_platform(cpu, "loongson3a");
1001 set_isa(c, MIPS_CPU_ISA_M64R1);
1002 break;
1003 case PRID_REV_LOONGSON3B_R1:
1004 case PRID_REV_LOONGSON3B_R2:
1005 c->cputype = CPU_LOONGSON3;
1006 __cpu_name[cpu] = "ICT Loongson-3";
1007 set_elf_platform(cpu, "loongson3b");
1008 set_isa(c, MIPS_CPU_ISA_M64R1);
1009 break;
1010 }
1011
1012 c->options = R4K_OPTS |
1013 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1014 MIPS_CPU_32FPR;
1015 c->tlbsize = 64;
1016 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1017 break;
1018 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1019 decode_configs(c);
1020
1021 c->cputype = CPU_LOONGSON1;
1022
1023 switch (c->processor_id & PRID_REV_MASK) {
1024 case PRID_REV_LOONGSON1B:
1025 __cpu_name[cpu] = "Loongson 1B";
1026 break;
1027 }
1028
1029 break;
1030 }
1031 }
1032
cpu_probe_mips(struct cpuinfo_mips * c,unsigned int cpu)1033 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1034 {
1035 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1036 switch (c->processor_id & PRID_IMP_MASK) {
1037 case PRID_IMP_QEMU_GENERIC:
1038 c->writecombine = _CACHE_UNCACHED;
1039 c->cputype = CPU_QEMU_GENERIC;
1040 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1041 break;
1042 case PRID_IMP_4KC:
1043 c->cputype = CPU_4KC;
1044 c->writecombine = _CACHE_UNCACHED;
1045 __cpu_name[cpu] = "MIPS 4Kc";
1046 break;
1047 case PRID_IMP_4KEC:
1048 case PRID_IMP_4KECR2:
1049 c->cputype = CPU_4KEC;
1050 c->writecombine = _CACHE_UNCACHED;
1051 __cpu_name[cpu] = "MIPS 4KEc";
1052 break;
1053 case PRID_IMP_4KSC:
1054 case PRID_IMP_4KSD:
1055 c->cputype = CPU_4KSC;
1056 c->writecombine = _CACHE_UNCACHED;
1057 __cpu_name[cpu] = "MIPS 4KSc";
1058 break;
1059 case PRID_IMP_5KC:
1060 c->cputype = CPU_5KC;
1061 c->writecombine = _CACHE_UNCACHED;
1062 __cpu_name[cpu] = "MIPS 5Kc";
1063 break;
1064 case PRID_IMP_5KE:
1065 c->cputype = CPU_5KE;
1066 c->writecombine = _CACHE_UNCACHED;
1067 __cpu_name[cpu] = "MIPS 5KE";
1068 break;
1069 case PRID_IMP_20KC:
1070 c->cputype = CPU_20KC;
1071 c->writecombine = _CACHE_UNCACHED;
1072 __cpu_name[cpu] = "MIPS 20Kc";
1073 break;
1074 case PRID_IMP_24K:
1075 c->cputype = CPU_24K;
1076 c->writecombine = _CACHE_UNCACHED;
1077 __cpu_name[cpu] = "MIPS 24Kc";
1078 break;
1079 case PRID_IMP_24KE:
1080 c->cputype = CPU_24K;
1081 c->writecombine = _CACHE_UNCACHED;
1082 __cpu_name[cpu] = "MIPS 24KEc";
1083 break;
1084 case PRID_IMP_25KF:
1085 c->cputype = CPU_25KF;
1086 c->writecombine = _CACHE_UNCACHED;
1087 __cpu_name[cpu] = "MIPS 25Kc";
1088 break;
1089 case PRID_IMP_34K:
1090 c->cputype = CPU_34K;
1091 c->writecombine = _CACHE_UNCACHED;
1092 __cpu_name[cpu] = "MIPS 34Kc";
1093 break;
1094 case PRID_IMP_74K:
1095 c->cputype = CPU_74K;
1096 c->writecombine = _CACHE_UNCACHED;
1097 __cpu_name[cpu] = "MIPS 74Kc";
1098 break;
1099 case PRID_IMP_M14KC:
1100 c->cputype = CPU_M14KC;
1101 c->writecombine = _CACHE_UNCACHED;
1102 __cpu_name[cpu] = "MIPS M14Kc";
1103 break;
1104 case PRID_IMP_M14KEC:
1105 c->cputype = CPU_M14KEC;
1106 c->writecombine = _CACHE_UNCACHED;
1107 __cpu_name[cpu] = "MIPS M14KEc";
1108 break;
1109 case PRID_IMP_1004K:
1110 c->cputype = CPU_1004K;
1111 c->writecombine = _CACHE_UNCACHED;
1112 __cpu_name[cpu] = "MIPS 1004Kc";
1113 break;
1114 case PRID_IMP_1074K:
1115 c->cputype = CPU_1074K;
1116 c->writecombine = _CACHE_UNCACHED;
1117 __cpu_name[cpu] = "MIPS 1074Kc";
1118 break;
1119 case PRID_IMP_INTERAPTIV_UP:
1120 c->cputype = CPU_INTERAPTIV;
1121 __cpu_name[cpu] = "MIPS interAptiv";
1122 break;
1123 case PRID_IMP_INTERAPTIV_MP:
1124 c->cputype = CPU_INTERAPTIV;
1125 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1126 break;
1127 case PRID_IMP_PROAPTIV_UP:
1128 c->cputype = CPU_PROAPTIV;
1129 __cpu_name[cpu] = "MIPS proAptiv";
1130 break;
1131 case PRID_IMP_PROAPTIV_MP:
1132 c->cputype = CPU_PROAPTIV;
1133 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1134 break;
1135 case PRID_IMP_P5600:
1136 c->cputype = CPU_P5600;
1137 __cpu_name[cpu] = "MIPS P5600";
1138 break;
1139 case PRID_IMP_M5150:
1140 c->cputype = CPU_M5150;
1141 __cpu_name[cpu] = "MIPS M5150";
1142 break;
1143 }
1144
1145 decode_configs(c);
1146
1147 spram_config();
1148 }
1149
cpu_probe_alchemy(struct cpuinfo_mips * c,unsigned int cpu)1150 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1151 {
1152 decode_configs(c);
1153 switch (c->processor_id & PRID_IMP_MASK) {
1154 case PRID_IMP_AU1_REV1:
1155 case PRID_IMP_AU1_REV2:
1156 c->cputype = CPU_ALCHEMY;
1157 switch ((c->processor_id >> 24) & 0xff) {
1158 case 0:
1159 __cpu_name[cpu] = "Au1000";
1160 break;
1161 case 1:
1162 __cpu_name[cpu] = "Au1500";
1163 break;
1164 case 2:
1165 __cpu_name[cpu] = "Au1100";
1166 break;
1167 case 3:
1168 __cpu_name[cpu] = "Au1550";
1169 break;
1170 case 4:
1171 __cpu_name[cpu] = "Au1200";
1172 if ((c->processor_id & PRID_REV_MASK) == 2)
1173 __cpu_name[cpu] = "Au1250";
1174 break;
1175 case 5:
1176 __cpu_name[cpu] = "Au1210";
1177 break;
1178 default:
1179 __cpu_name[cpu] = "Au1xxx";
1180 break;
1181 }
1182 break;
1183 }
1184 }
1185
cpu_probe_sibyte(struct cpuinfo_mips * c,unsigned int cpu)1186 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1187 {
1188 decode_configs(c);
1189
1190 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1191 switch (c->processor_id & PRID_IMP_MASK) {
1192 case PRID_IMP_SB1:
1193 c->cputype = CPU_SB1;
1194 __cpu_name[cpu] = "SiByte SB1";
1195 /* FPU in pass1 is known to have issues. */
1196 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1197 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1198 break;
1199 case PRID_IMP_SB1A:
1200 c->cputype = CPU_SB1A;
1201 __cpu_name[cpu] = "SiByte SB1A";
1202 break;
1203 }
1204 }
1205
cpu_probe_sandcraft(struct cpuinfo_mips * c,unsigned int cpu)1206 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1207 {
1208 decode_configs(c);
1209 switch (c->processor_id & PRID_IMP_MASK) {
1210 case PRID_IMP_SR71000:
1211 c->cputype = CPU_SR71000;
1212 __cpu_name[cpu] = "Sandcraft SR71000";
1213 c->scache.ways = 8;
1214 c->tlbsize = 64;
1215 break;
1216 }
1217 }
1218
cpu_probe_nxp(struct cpuinfo_mips * c,unsigned int cpu)1219 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1220 {
1221 decode_configs(c);
1222 switch (c->processor_id & PRID_IMP_MASK) {
1223 case PRID_IMP_PR4450:
1224 c->cputype = CPU_PR4450;
1225 __cpu_name[cpu] = "Philips PR4450";
1226 set_isa(c, MIPS_CPU_ISA_M32R1);
1227 break;
1228 }
1229 }
1230
cpu_probe_broadcom(struct cpuinfo_mips * c,unsigned int cpu)1231 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1232 {
1233 decode_configs(c);
1234 switch (c->processor_id & PRID_IMP_MASK) {
1235 case PRID_IMP_BMIPS32_REV4:
1236 case PRID_IMP_BMIPS32_REV8:
1237 c->cputype = CPU_BMIPS32;
1238 __cpu_name[cpu] = "Broadcom BMIPS32";
1239 set_elf_platform(cpu, "bmips32");
1240 break;
1241 case PRID_IMP_BMIPS3300:
1242 case PRID_IMP_BMIPS3300_ALT:
1243 case PRID_IMP_BMIPS3300_BUG:
1244 c->cputype = CPU_BMIPS3300;
1245 __cpu_name[cpu] = "Broadcom BMIPS3300";
1246 set_elf_platform(cpu, "bmips3300");
1247 break;
1248 case PRID_IMP_BMIPS43XX: {
1249 int rev = c->processor_id & PRID_REV_MASK;
1250
1251 if (rev >= PRID_REV_BMIPS4380_LO &&
1252 rev <= PRID_REV_BMIPS4380_HI) {
1253 c->cputype = CPU_BMIPS4380;
1254 __cpu_name[cpu] = "Broadcom BMIPS4380";
1255 set_elf_platform(cpu, "bmips4380");
1256 } else {
1257 c->cputype = CPU_BMIPS4350;
1258 __cpu_name[cpu] = "Broadcom BMIPS4350";
1259 set_elf_platform(cpu, "bmips4350");
1260 }
1261 break;
1262 }
1263 case PRID_IMP_BMIPS5000:
1264 c->cputype = CPU_BMIPS5000;
1265 __cpu_name[cpu] = "Broadcom BMIPS5000";
1266 set_elf_platform(cpu, "bmips5000");
1267 c->options |= MIPS_CPU_ULRI;
1268 break;
1269 }
1270 }
1271
cpu_probe_cavium(struct cpuinfo_mips * c,unsigned int cpu)1272 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1273 {
1274 decode_configs(c);
1275 switch (c->processor_id & PRID_IMP_MASK) {
1276 case PRID_IMP_CAVIUM_CN38XX:
1277 case PRID_IMP_CAVIUM_CN31XX:
1278 case PRID_IMP_CAVIUM_CN30XX:
1279 c->cputype = CPU_CAVIUM_OCTEON;
1280 __cpu_name[cpu] = "Cavium Octeon";
1281 goto platform;
1282 case PRID_IMP_CAVIUM_CN58XX:
1283 case PRID_IMP_CAVIUM_CN56XX:
1284 case PRID_IMP_CAVIUM_CN50XX:
1285 case PRID_IMP_CAVIUM_CN52XX:
1286 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1287 __cpu_name[cpu] = "Cavium Octeon+";
1288 platform:
1289 set_elf_platform(cpu, "octeon");
1290 break;
1291 case PRID_IMP_CAVIUM_CN61XX:
1292 case PRID_IMP_CAVIUM_CN63XX:
1293 case PRID_IMP_CAVIUM_CN66XX:
1294 case PRID_IMP_CAVIUM_CN68XX:
1295 case PRID_IMP_CAVIUM_CNF71XX:
1296 c->cputype = CPU_CAVIUM_OCTEON2;
1297 __cpu_name[cpu] = "Cavium Octeon II";
1298 set_elf_platform(cpu, "octeon2");
1299 break;
1300 case PRID_IMP_CAVIUM_CN70XX:
1301 case PRID_IMP_CAVIUM_CN78XX:
1302 c->cputype = CPU_CAVIUM_OCTEON3;
1303 __cpu_name[cpu] = "Cavium Octeon III";
1304 set_elf_platform(cpu, "octeon3");
1305 break;
1306 default:
1307 printk(KERN_INFO "Unknown Octeon chip!\n");
1308 c->cputype = CPU_UNKNOWN;
1309 break;
1310 }
1311 }
1312
cpu_probe_ingenic(struct cpuinfo_mips * c,unsigned int cpu)1313 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1314 {
1315 decode_configs(c);
1316 /* JZRISC does not implement the CP0 counter. */
1317 c->options &= ~MIPS_CPU_COUNTER;
1318 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1319 switch (c->processor_id & PRID_IMP_MASK) {
1320 case PRID_IMP_JZRISC:
1321 c->cputype = CPU_JZRISC;
1322 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1323 __cpu_name[cpu] = "Ingenic JZRISC";
1324 break;
1325 default:
1326 panic("Unknown Ingenic Processor ID!");
1327 break;
1328 }
1329 }
1330
cpu_probe_netlogic(struct cpuinfo_mips * c,int cpu)1331 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1332 {
1333 decode_configs(c);
1334
1335 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1336 c->cputype = CPU_ALCHEMY;
1337 __cpu_name[cpu] = "Au1300";
1338 /* following stuff is not for Alchemy */
1339 return;
1340 }
1341
1342 c->options = (MIPS_CPU_TLB |
1343 MIPS_CPU_4KEX |
1344 MIPS_CPU_COUNTER |
1345 MIPS_CPU_DIVEC |
1346 MIPS_CPU_WATCH |
1347 MIPS_CPU_EJTAG |
1348 MIPS_CPU_LLSC);
1349
1350 switch (c->processor_id & PRID_IMP_MASK) {
1351 case PRID_IMP_NETLOGIC_XLP2XX:
1352 case PRID_IMP_NETLOGIC_XLP9XX:
1353 case PRID_IMP_NETLOGIC_XLP5XX:
1354 c->cputype = CPU_XLP;
1355 __cpu_name[cpu] = "Broadcom XLPII";
1356 break;
1357
1358 case PRID_IMP_NETLOGIC_XLP8XX:
1359 case PRID_IMP_NETLOGIC_XLP3XX:
1360 c->cputype = CPU_XLP;
1361 __cpu_name[cpu] = "Netlogic XLP";
1362 break;
1363
1364 case PRID_IMP_NETLOGIC_XLR732:
1365 case PRID_IMP_NETLOGIC_XLR716:
1366 case PRID_IMP_NETLOGIC_XLR532:
1367 case PRID_IMP_NETLOGIC_XLR308:
1368 case PRID_IMP_NETLOGIC_XLR532C:
1369 case PRID_IMP_NETLOGIC_XLR516C:
1370 case PRID_IMP_NETLOGIC_XLR508C:
1371 case PRID_IMP_NETLOGIC_XLR308C:
1372 c->cputype = CPU_XLR;
1373 __cpu_name[cpu] = "Netlogic XLR";
1374 break;
1375
1376 case PRID_IMP_NETLOGIC_XLS608:
1377 case PRID_IMP_NETLOGIC_XLS408:
1378 case PRID_IMP_NETLOGIC_XLS404:
1379 case PRID_IMP_NETLOGIC_XLS208:
1380 case PRID_IMP_NETLOGIC_XLS204:
1381 case PRID_IMP_NETLOGIC_XLS108:
1382 case PRID_IMP_NETLOGIC_XLS104:
1383 case PRID_IMP_NETLOGIC_XLS616B:
1384 case PRID_IMP_NETLOGIC_XLS608B:
1385 case PRID_IMP_NETLOGIC_XLS416B:
1386 case PRID_IMP_NETLOGIC_XLS412B:
1387 case PRID_IMP_NETLOGIC_XLS408B:
1388 case PRID_IMP_NETLOGIC_XLS404B:
1389 c->cputype = CPU_XLR;
1390 __cpu_name[cpu] = "Netlogic XLS";
1391 break;
1392
1393 default:
1394 pr_info("Unknown Netlogic chip id [%02x]!\n",
1395 c->processor_id);
1396 c->cputype = CPU_XLR;
1397 break;
1398 }
1399
1400 if (c->cputype == CPU_XLP) {
1401 set_isa(c, MIPS_CPU_ISA_M64R2);
1402 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1403 /* This will be updated again after all threads are woken up */
1404 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1405 } else {
1406 set_isa(c, MIPS_CPU_ISA_M64R1);
1407 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1408 }
1409 c->kscratch_mask = 0xf;
1410 }
1411
1412 #ifdef CONFIG_64BIT
1413 /* For use by uaccess.h */
1414 u64 __ua_limit;
1415 EXPORT_SYMBOL(__ua_limit);
1416 #endif
1417
1418 const char *__cpu_name[NR_CPUS];
1419 const char *__elf_platform;
1420
cpu_probe(void)1421 void cpu_probe(void)
1422 {
1423 struct cpuinfo_mips *c = ¤t_cpu_data;
1424 unsigned int cpu = smp_processor_id();
1425
1426 c->processor_id = PRID_IMP_UNKNOWN;
1427 c->fpu_id = FPIR_IMP_NONE;
1428 c->cputype = CPU_UNKNOWN;
1429 c->writecombine = _CACHE_UNCACHED;
1430
1431 c->fpu_csr31 = FPU_CSR_RN;
1432 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1433
1434 c->processor_id = read_c0_prid();
1435 switch (c->processor_id & PRID_COMP_MASK) {
1436 case PRID_COMP_LEGACY:
1437 cpu_probe_legacy(c, cpu);
1438 break;
1439 case PRID_COMP_MIPS:
1440 cpu_probe_mips(c, cpu);
1441 break;
1442 case PRID_COMP_ALCHEMY:
1443 cpu_probe_alchemy(c, cpu);
1444 break;
1445 case PRID_COMP_SIBYTE:
1446 cpu_probe_sibyte(c, cpu);
1447 break;
1448 case PRID_COMP_BROADCOM:
1449 cpu_probe_broadcom(c, cpu);
1450 break;
1451 case PRID_COMP_SANDCRAFT:
1452 cpu_probe_sandcraft(c, cpu);
1453 break;
1454 case PRID_COMP_NXP:
1455 cpu_probe_nxp(c, cpu);
1456 break;
1457 case PRID_COMP_CAVIUM:
1458 cpu_probe_cavium(c, cpu);
1459 break;
1460 case PRID_COMP_INGENIC:
1461 cpu_probe_ingenic(c, cpu);
1462 break;
1463 case PRID_COMP_NETLOGIC:
1464 cpu_probe_netlogic(c, cpu);
1465 break;
1466 }
1467
1468 BUG_ON(!__cpu_name[cpu]);
1469 BUG_ON(c->cputype == CPU_UNKNOWN);
1470
1471 /*
1472 * Platform code can force the cpu type to optimize code
1473 * generation. In that case be sure the cpu type is correctly
1474 * manually setup otherwise it could trigger some nasty bugs.
1475 */
1476 BUG_ON(current_cpu_type() != c->cputype);
1477
1478 if (mips_fpu_disabled)
1479 c->options &= ~MIPS_CPU_FPU;
1480
1481 if (mips_dsp_disabled)
1482 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1483
1484 if (mips_htw_disabled) {
1485 c->options &= ~MIPS_CPU_HTW;
1486 write_c0_pwctl(read_c0_pwctl() &
1487 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1488 }
1489
1490 if (c->options & MIPS_CPU_FPU)
1491 cpu_set_fpu_opts(c);
1492 else
1493 cpu_set_nofpu_opts(c);
1494
1495 if (cpu_has_bp_ghist)
1496 write_c0_r10k_diag(read_c0_r10k_diag() |
1497 R10K_DIAG_E_GHIST);
1498
1499 if (cpu_has_mips_r2_r6) {
1500 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1501 /* R2 has Performance Counter Interrupt indicator */
1502 c->options |= MIPS_CPU_PCI;
1503 }
1504 else
1505 c->srsets = 1;
1506
1507 if (cpu_has_msa) {
1508 c->msa_id = cpu_get_msa_id();
1509 WARN(c->msa_id & MSA_IR_WRPF,
1510 "Vector register partitioning unimplemented!");
1511 }
1512
1513 cpu_probe_vmbits(c);
1514
1515 #ifdef CONFIG_64BIT
1516 if (cpu == 0)
1517 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1518 #endif
1519 }
1520
cpu_report(void)1521 void cpu_report(void)
1522 {
1523 struct cpuinfo_mips *c = ¤t_cpu_data;
1524
1525 pr_info("CPU%d revision is: %08x (%s)\n",
1526 smp_processor_id(), c->processor_id, cpu_name_string());
1527 if (c->options & MIPS_CPU_FPU)
1528 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1529 if (cpu_has_msa)
1530 pr_info("MSA revision is: %08x\n", c->msa_id);
1531 }
1532