Home
last modified time | relevance | path

Searched refs:SH_CLK_SET_RATIO (Results 1 – 5 of 5) sorted by relevance

/arch/arm/mach-shmobile/
Dclock-r8a7778.c265 SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1); in r8a7778_clock_init()
266 SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); in r8a7778_clock_init()
270 SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); in r8a7778_clock_init()
271 SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1); in r8a7778_clock_init()
275 SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1); in r8a7778_clock_init()
276 SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1); in r8a7778_clock_init()
280 SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1); in r8a7778_clock_init()
281 SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1); in r8a7778_clock_init()
285 SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1); in r8a7778_clock_init()
286 SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1); in r8a7778_clock_init()
[all …]
Dclock-r8a7779.c216 SH_CLK_SET_RATIO(&clkz_clk_ratio, 2, 3); in r8a7779_clock_init()
217 SH_CLK_SET_RATIO(&clkzs_clk_ratio, 1, 6); in r8a7779_clock_init()
218 SH_CLK_SET_RATIO(&clki_clk_ratio, 1, 2); in r8a7779_clock_init()
219 SH_CLK_SET_RATIO(&clks_clk_ratio, 1, 6); in r8a7779_clock_init()
220 SH_CLK_SET_RATIO(&clks1_clk_ratio, 1, 12); in r8a7779_clock_init()
221 SH_CLK_SET_RATIO(&clks3_clk_ratio, 1, 8); in r8a7779_clock_init()
222 SH_CLK_SET_RATIO(&clks4_clk_ratio, 1, 16); in r8a7779_clock_init()
223 SH_CLK_SET_RATIO(&clkp_clk_ratio, 1, 24); in r8a7779_clock_init()
224 SH_CLK_SET_RATIO(&clkg_clk_ratio, 1, 24); in r8a7779_clock_init()
226 SH_CLK_SET_RATIO(&clkb_clk_ratio, 1, 36); in r8a7779_clock_init()
[all …]
Dclock-r8a7791.c287 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
289 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
291 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
315 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); in r8a7791_clock_init()
317 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); in r8a7791_clock_init()
Dclock-r8a7790.c408 SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
410 SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
412 SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
436 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36); in r8a7790_clock_init()
438 SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24); in r8a7790_clock_init()
441 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16); in r8a7790_clock_init()
443 SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20); in r8a7790_clock_init()
Dclock.h49 #define SH_CLK_SET_RATIO(p, m, d) \ macro