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Searched refs:SIC_IAR0 (Results 1 – 17 of 17) sorted by relevance

/arch/blackfin/include/asm/
Ddpmc.h190 #ifdef SIC_IAR0
191 PM_SYS_PUSH(3, SIC_IAR0)
346 #ifdef SIC_IAR0
349 PM_SYS_POP(3, SIC_IAR0)
/arch/blackfin/mach-common/
Dints-priority.c84 bfin_read32((unsigned long *)SIC_IAR0 + in search_IAR()
87 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) in search_IAR()
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h29 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
DcdefBF532.h26 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
27 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h31 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
DcdefBF522.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h28 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
DcdefBF512.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h35 #define SIC_IAR0 0xFFC00124 /* SIC Interrupt Assignment Register 0 */ macro
DcdefBF561.h36 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
37 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h26 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
DcdefBF534.h30 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
31 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h28 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ macro
DcdefBF538.h46 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
47 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h48 #define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */ macro
DcdefBF54x_base.h65 #define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
66 #define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
/arch/blackfin/kernel/
Ddebug-mmrs.c1463 D32(SIC_IAR0); in bfin_debug_mmrs_init()