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Searched refs:SPORT0_TCR2 (Results 1 – 14 of 14) sorted by relevance

/arch/blackfin/mach-bf548/include/mach/
DdefBF547.h39 #define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register … macro
DcdefBF547.h55 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
56 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h123 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF532.h564 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
565 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h158 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF522.h263 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
264 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h161 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF512.h246 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
247 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h235 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF561.h374 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
375 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h137 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF534.h228 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
229 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h127 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */ macro
DcdefBF538.h218 #define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
219 #define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)