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Searched refs:UART1_THR (Results 1 – 25 of 27) sorted by relevance

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/arch/blackfin/mach-bf537/boards/
Ddnp5370.c284 .start = UART1_THR,
Dpnav10.c352 .start = UART1_THR,
Dminotaur.c284 .start = UART1_THR,
Dtcm_bf537.c354 .start = UART1_THR,
Dcm_bf537u.c354 .start = UART1_THR,
Dcm_bf537e.c437 .start = UART1_THR,
Dstamp.c1665 .start = UART1_THR,
/arch/blackfin/mach-bf518/boards/
Dtcm-bf518.c353 .start = UART1_THR,
Dezbrd.c418 .start = UART1_THR,
/arch/blackfin/mach-bf527/boards/
Dad7160eval.c416 .start = UART1_THR,
Dezbrd.c462 .start = UART1_THR,
Dcm_bf527.c583 .start = UART1_THR,
Dtll6527m.c538 .start = UART1_THR,
Dezkit.c748 .start = UART1_THR,
/arch/blackfin/mach-bf538/boards/
Dezkit.c107 .start = UART1_THR,
/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h515 #define UART1_THR 0xFFC02000 /* Transmit Holding register */ macro
DcdefBF522.h918 #define bfin_read_UART1_THR() bfin_read16(UART1_THR)
919 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h515 #define UART1_THR 0xFFC02000 /* Transmit Holding register */ macro
DcdefBF512.h901 #define bfin_read_UART1_THR() bfin_read16(UART1_THR)
902 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h486 #define UART1_THR 0xFFC02000 /* Transmit Holding register */ macro
DcdefBF534.h876 #define bfin_read_UART1_THR() bfin_read16(UART1_THR)
877 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR,val)
/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h664 #define UART1_THR 0xFFC02000 /* Transmit Holding register */ macro
DcdefBF538.h100 #define bfin_read_UART1_THR() bfin_read16(UART1_THR)
101 #define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
/arch/blackfin/mach-bf548/include/mach/
DdefBF54x_base.h957 #define UART1_THR 0xffc02028 /* Transmit Hold Register */ macro
/arch/blackfin/mach-bf609/include/mach/
DdefBF60x_base.h669 #define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */ macro

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