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/arch/cris/include/uapi/arch-v10/arch/
Dsv_addr_ag.h28 #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
30 ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
34 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
36 ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
40 #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
41 #define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
42 - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
47 IO_STATE_VALUE_ (reg##_, field##_, _##state)
48 #define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
52 #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
[all …]
/arch/arm/crypto/
Dsha1-armv7-neon.S335 W4, W5, W6, W7, W0, _, _, _ );
338 W4, W5, W6, W7, W0, _, _, _ );
341 W4, W5, W6, W7, W0, _, _, _ );
344 W4, W5, W6, W7, W0, _, _, _ );
350 W3, W4, W5, W6, W7, _, _, _ );
353 W3, W4, W5, W6, W7, _, _, _ );
356 W3, W4, W5, W6, W7, _, _, _ );
359 W3, W4, W5, W6, W7, _, _, _ );
363 W2, W3, W4, W5, W6, _, _, _ );
366 W2, W3, W4, W5, W6, _, _, _ );
[all …]
/arch/cris/include/arch-v32/arch/hwregs/
Dirq_nmi_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dstrcop_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Drt_trace_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
/arch/cris/include/arch-v32/arch/hwregs/iop/
Diop_version_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_scrc_out_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_scrc_in_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_fifo_in_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_fifo_out_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_trigger_grp_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_sap_in_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_mpu_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_crc_par_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
Diop_version_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Diop_sap_in_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
Dstrmux_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dmarb_bar_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dl2cache_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dclkgen_defs.h16 REG_READ( reg_##scope##_##reg, \
17 (inst) + REG_RD_ADDR_##scope##_##reg )
22 REG_WRITE( reg_##scope##_##reg, \
23 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
28 REG_READ( reg_##scope##_##reg, \
29 (inst) + REG_RD_ADDR_##scope##_##reg + \
30 (index) * STRIDE_##scope##_##reg )
35 REG_WRITE( reg_##scope##_##reg, \
36 (inst) + REG_WR_ADDR_##scope##_##reg + \
37 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
Dstrmux_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]
Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
20 (inst) + REG_RD_ADDR_##scope##_##reg )
25 REG_WRITE( reg_##scope##_##reg, \
26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
31 REG_READ( reg_##scope##_##reg, \
32 (inst) + REG_RD_ADDR_##scope##_##reg + \
33 (index) * STRIDE_##scope##_##reg )
38 REG_WRITE( reg_##scope##_##reg, \
39 (inst) + REG_WR_ADDR_##scope##_##reg + \
40 (index) * STRIDE_##scope##_##reg, (val) )
[all …]

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