1 #ifndef __iop_sap_in_defs_h 2 #define __iop_sap_in_defs_h 3 4 /* 5 * This file is autogenerated from 6 * file: ../../inst/io_proc/rtl/iop_sap_in.r 7 * id: <not found> 8 * last modfied: Mon Apr 11 16:08:45 2005 9 * 10 * by /n/asic/design/tools/rdesc/src/rdes2c --outfile iop_sap_in_defs.h ../../inst/io_proc/rtl/iop_sap_in.r 11 * id: $Id: iop_sap_in_defs.h,v 1.5 2005/04/24 18:31:05 starvik Exp $ 12 * Any changes here will be lost. 13 * 14 * -*- buffer-read-only: t -*- 15 */ 16 /* Main access macros */ 17 #ifndef REG_RD 18 #define REG_RD( scope, inst, reg ) \ 19 REG_READ( reg_##scope##_##reg, \ 20 (inst) + REG_RD_ADDR_##scope##_##reg ) 21 #endif 22 23 #ifndef REG_WR 24 #define REG_WR( scope, inst, reg, val ) \ 25 REG_WRITE( reg_##scope##_##reg, \ 26 (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 27 #endif 28 29 #ifndef REG_RD_VECT 30 #define REG_RD_VECT( scope, inst, reg, index ) \ 31 REG_READ( reg_##scope##_##reg, \ 32 (inst) + REG_RD_ADDR_##scope##_##reg + \ 33 (index) * STRIDE_##scope##_##reg ) 34 #endif 35 36 #ifndef REG_WR_VECT 37 #define REG_WR_VECT( scope, inst, reg, index, val ) \ 38 REG_WRITE( reg_##scope##_##reg, \ 39 (inst) + REG_WR_ADDR_##scope##_##reg + \ 40 (index) * STRIDE_##scope##_##reg, (val) ) 41 #endif 42 43 #ifndef REG_RD_INT 44 #define REG_RD_INT( scope, inst, reg ) \ 45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) 46 #endif 47 48 #ifndef REG_WR_INT 49 #define REG_WR_INT( scope, inst, reg, val ) \ 50 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) 51 #endif 52 53 #ifndef REG_RD_INT_VECT 54 #define REG_RD_INT_VECT( scope, inst, reg, index ) \ 55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ 56 (index) * STRIDE_##scope##_##reg ) 57 #endif 58 59 #ifndef REG_WR_INT_VECT 60 #define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ 61 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ 62 (index) * STRIDE_##scope##_##reg, (val) ) 63 #endif 64 65 #ifndef REG_TYPE_CONV 66 #define REG_TYPE_CONV( type, orgtype, val ) \ 67 ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) 68 #endif 69 70 #ifndef reg_page_size 71 #define reg_page_size 8192 72 #endif 73 74 #ifndef REG_ADDR 75 #define REG_ADDR( scope, inst, reg ) \ 76 ( (inst) + REG_RD_ADDR_##scope##_##reg ) 77 #endif 78 79 #ifndef REG_ADDR_VECT 80 #define REG_ADDR_VECT( scope, inst, reg, index ) \ 81 ( (inst) + REG_RD_ADDR_##scope##_##reg + \ 82 (index) * STRIDE_##scope##_##reg ) 83 #endif 84 85 /* C-code for register scope iop_sap_in */ 86 87 /* Register rw_bus0_sync, scope iop_sap_in, type rw */ 88 typedef struct { 89 unsigned int byte0_sel : 2; 90 unsigned int byte0_ext_src : 3; 91 unsigned int byte0_edge : 2; 92 unsigned int byte0_delay : 1; 93 unsigned int byte1_sel : 2; 94 unsigned int byte1_ext_src : 3; 95 unsigned int byte1_edge : 2; 96 unsigned int byte1_delay : 1; 97 unsigned int byte2_sel : 2; 98 unsigned int byte2_ext_src : 3; 99 unsigned int byte2_edge : 2; 100 unsigned int byte2_delay : 1; 101 unsigned int byte3_sel : 2; 102 unsigned int byte3_ext_src : 3; 103 unsigned int byte3_edge : 2; 104 unsigned int byte3_delay : 1; 105 } reg_iop_sap_in_rw_bus0_sync; 106 #define REG_RD_ADDR_iop_sap_in_rw_bus0_sync 0 107 #define REG_WR_ADDR_iop_sap_in_rw_bus0_sync 0 108 109 /* Register rw_bus1_sync, scope iop_sap_in, type rw */ 110 typedef struct { 111 unsigned int byte0_sel : 2; 112 unsigned int byte0_ext_src : 3; 113 unsigned int byte0_edge : 2; 114 unsigned int byte0_delay : 1; 115 unsigned int byte1_sel : 2; 116 unsigned int byte1_ext_src : 3; 117 unsigned int byte1_edge : 2; 118 unsigned int byte1_delay : 1; 119 unsigned int byte2_sel : 2; 120 unsigned int byte2_ext_src : 3; 121 unsigned int byte2_edge : 2; 122 unsigned int byte2_delay : 1; 123 unsigned int byte3_sel : 2; 124 unsigned int byte3_ext_src : 3; 125 unsigned int byte3_edge : 2; 126 unsigned int byte3_delay : 1; 127 } reg_iop_sap_in_rw_bus1_sync; 128 #define REG_RD_ADDR_iop_sap_in_rw_bus1_sync 4 129 #define REG_WR_ADDR_iop_sap_in_rw_bus1_sync 4 130 131 #define STRIDE_iop_sap_in_rw_gio 4 132 /* Register rw_gio, scope iop_sap_in, type rw */ 133 typedef struct { 134 unsigned int sync_sel : 2; 135 unsigned int sync_ext_src : 3; 136 unsigned int sync_edge : 2; 137 unsigned int delay : 1; 138 unsigned int logic : 2; 139 unsigned int dummy1 : 22; 140 } reg_iop_sap_in_rw_gio; 141 #define REG_RD_ADDR_iop_sap_in_rw_gio 8 142 #define REG_WR_ADDR_iop_sap_in_rw_gio 8 143 144 145 /* Constants */ 146 enum { 147 regk_iop_sap_in_and = 0x00000002, 148 regk_iop_sap_in_ext_clk200 = 0x00000003, 149 regk_iop_sap_in_gio1 = 0x00000000, 150 regk_iop_sap_in_gio13 = 0x00000005, 151 regk_iop_sap_in_gio18 = 0x00000003, 152 regk_iop_sap_in_gio19 = 0x00000004, 153 regk_iop_sap_in_gio21 = 0x00000006, 154 regk_iop_sap_in_gio23 = 0x00000005, 155 regk_iop_sap_in_gio29 = 0x00000007, 156 regk_iop_sap_in_gio5 = 0x00000004, 157 regk_iop_sap_in_gio6 = 0x00000001, 158 regk_iop_sap_in_gio7 = 0x00000002, 159 regk_iop_sap_in_inv = 0x00000001, 160 regk_iop_sap_in_neg = 0x00000002, 161 regk_iop_sap_in_no = 0x00000000, 162 regk_iop_sap_in_no_del_ext_clk200 = 0x00000001, 163 regk_iop_sap_in_none = 0x00000000, 164 regk_iop_sap_in_or = 0x00000003, 165 regk_iop_sap_in_pos = 0x00000001, 166 regk_iop_sap_in_pos_neg = 0x00000003, 167 regk_iop_sap_in_rw_bus0_sync_default = 0x02020202, 168 regk_iop_sap_in_rw_bus1_sync_default = 0x02020202, 169 regk_iop_sap_in_rw_gio_default = 0x00000002, 170 regk_iop_sap_in_rw_gio_size = 0x00000020, 171 regk_iop_sap_in_timer_grp0_tmr3 = 0x00000006, 172 regk_iop_sap_in_timer_grp1_tmr3 = 0x00000004, 173 regk_iop_sap_in_timer_grp2_tmr3 = 0x00000005, 174 regk_iop_sap_in_timer_grp3_tmr3 = 0x00000007, 175 regk_iop_sap_in_tmr_clk200 = 0x00000000, 176 regk_iop_sap_in_two_clk200 = 0x00000002, 177 regk_iop_sap_in_yes = 0x00000001 178 }; 179 #endif /* __iop_sap_in_defs_h */ 180