Home
last modified time | relevance | path

Searched refs:active_mask (Results 1 – 14 of 14) sorted by relevance

/arch/x86/kernel/cpu/
Dperf_event_amd_uncore.c39 cpumask_t *active_mask; member
223 cpumask_t *active_mask; in amd_uncore_attr_show_cpumask() local
227 active_mask = &amd_nb_active_mask; in amd_uncore_attr_show_cpumask()
229 active_mask = &amd_l2_active_mask; in amd_uncore_attr_show_cpumask()
233 n = cpulist_scnprintf(buf, PAGE_SIZE - 2, active_mask); in amd_uncore_attr_show_cpumask()
309 uncore_nb->active_mask = &amd_nb_active_mask; in amd_uncore_cpu_up_prepare()
322 uncore_l2->active_mask = &amd_l2_active_mask; in amd_uncore_cpu_up_prepare()
398 cpumask_set_cpu(cpu, uncore->active_mask); in uncore_online()
428 cpumask_clear_cpu(cpu, that->active_mask); in uncore_down_prepare()
429 cpumask_set_cpu(i, that->active_mask); in uncore_down_prepare()
[all …]
Dperf_event_knc.c246 if (!test_bit(bit, cpuc->active_mask)) in knc_pmu_handle_irq()
Dperf_event.c500 if (!test_bit(idx, cpuc->active_mask)) in x86_pmu_disable_all()
535 if (!test_bit(idx, cpuc->active_mask)) in x86_pmu_enable_all()
1095 __set_bit(idx, cpuc->active_mask); in x86_pmu_start()
1131 pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); in perf_event_print_debug()
1160 if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { in x86_pmu_stop()
1247 if (!test_bit(idx, cpuc->active_mask)) { in x86_pmu_handle_irq()
Dperf_event_intel_uncore.h100 unsigned long active_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)]; member
Dperf_event_intel_uncore.c225 for_each_set_bit(bit, box->active_mask, UNCORE_PMC_IDX_MAX) in uncore_pmu_hrtimer()
422 __set_bit(idx, box->active_mask); in uncore_pmu_event_start()
438 if (__test_and_clear_bit(hwc->idx, box->active_mask)) { in uncore_pmu_event_stop()
Dperf_event_p4.c923 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_disable_all()
992 if (!test_bit(idx, cpuc->active_mask)) in p4_pmu_enable_all()
1012 if (!test_bit(idx, cpuc->active_mask)) { in p4_pmu_handle_irq()
Dperf_event_intel.c1052 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) in intel_pmu_disable_all()
1068 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) { in intel_pmu_enable_all()
1413 if (!test_bit(bit, cpuc->active_mask)) in intel_pmu_handle_irq()
1815 if (!test_bit(idx, cpuc->active_mask)) in core_guest_get_msrs()
1845 if (!test_bit(idx, cpuc->active_mask) || in core_pmu_enable_all()
Dperf_event_intel_ds.c936 if (!test_bit(0, cpuc->active_mask)) in intel_pmu_drain_pebs_core()
992 if (!test_bit(bit, cpuc->active_mask)) in intel_pmu_drain_pebs_nhm()
Dperf_event.h131 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; member
/arch/sh/include/asm/
Dhw_breakpoint.h37 unsigned long (*active_mask)(void); member
/arch/sh/kernel/cpu/sh4a/
Dubc.c96 .active_mask = sh4a_ubc_active_mask,
/arch/tile/kernel/
Dperf_event.c56 unsigned long active_mask[BITS_TO_LONGS(TILE_MAX_COUNTERS)]; member
597 if (__test_and_clear_bit(idx, cpuc->active_mask)) { in tile_pmu_stop()
636 __set_bit(idx, cpuc->active_mask); in tile_pmu_start()
905 if (!test_bit(bit, cpuc->active_mask)) in tile_pmu_handle_irq()
/arch/sh/kernel/
Dhw_breakpoint.c297 resume_mask = sh_ubc->active_mask(); in hw_breakpoint_handler()
Dperf_event.c34 unsigned long active_mask[BITS_TO_LONGS(MAX_HWEVENTS)]; member