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Searched refs:operation (Results 1 – 25 of 54) sorted by relevance

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/arch/x86/lib/
Dcmpxchg16b_emu.S30 # Note that this is only useful for a cpuops operation. Meaning that we
31 # do *not* have a fully atomic operation but just an operation that is
/arch/cris/include/arch-v32/arch/
Dcryptocop.h152 int cryptocop_job_queue_insert_csum(struct cryptocop_operation *operation);
154 int cryptocop_job_queue_insert_crypto(struct cryptocop_operation *operation);
156 int cryptocop_job_queue_insert_user_job(struct cryptocop_operation *operation);
/arch/cris/arch-v32/drivers/
Dcryptocop.c224 …t cryptocop_job_queue_insert(cryptocop_queue_priority prio, struct cryptocop_operation *operation);
225 …tic int cryptocop_job_setup(struct cryptocop_prio_job **pj, struct cryptocop_operation *operation);
529 static int create_input_descriptors(struct cryptocop_operation *operation, struct cryptocop_tfrm_ct… in create_input_descriptors() argument
544 …if (((tc->produced + tc->tcfg->inject_ix) > operation->tfrm_op.outlen) || (tc->produced && (operat… in create_input_descriptors()
549 …while ((outiov_ix < operation->tfrm_op.outcount) && ((out_ix + operation->tfrm_op.outdata[outiov_i… in create_input_descriptors()
550 out_ix += operation->tfrm_op.outdata[outiov_ix].iov_len; in create_input_descriptors()
553 if (outiov_ix >= operation->tfrm_op.outcount){ in create_input_descriptors()
561 while ((out_length > 0) && (outiov_ix < operation->tfrm_op.outcount)) { in create_input_descriptors()
569 rem_length = operation->tfrm_op.outdata[outiov_ix].iov_len - iov_offset; in create_input_descriptors()
576 …outiov_ix, rem_length, dlength, iov_offset, operation->tfrm_op.outdata[outiov_ix].iov_len, operati… in create_input_descriptors()
[all …]
/arch/avr32/mm/
Dcache.c127 asmlinkage int sys_cacheflush(int operation, void __user *addr, size_t len) in sys_cacheflush() argument
141 switch (operation) { in sys_cacheflush()
/arch/arm/mach-omap2/
Dsram243x.S52 mov r3, #0x1 @ value for 1x operation
53 str r3, [r2] @ go to L1-freq operation
80 mov r3, #0x2 @ value for 2x operation
81 str r3, [r2] @ go to L0-freq operation
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
Dsram242x.S52 mov r3, #0x1 @ value for 1x operation
53 str r3, [r2] @ go to L1-freq operation
80 mov r3, #0x2 @ value for 2x operation
81 str r3, [r2] @ go to L0-freq operation
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
/arch/m68k/fpsp040/
Dslog2.S32 | Step 0. If X < 0, create a NaN and raise the invalid operation
47 | Step 0. If X < 0, create a NaN and raise the invalid operation
61 | Step 0. If X < 0, create a NaN and raise the invalid operation
76 | Step 0. If X < 0, create a NaN and raise the invalid operation
Dsacos.S34 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
Dbindec.S37 | The operation in A3 above may have set INEX2.
62 | The operation in A3 above may have set INEX2.
63 | RZ mode is forced for the scaling operation to insure
78 | Perform FINT operation in the user's rounding mode.
86 | If the int operation results in more than LEN digits,
263 | The operation in A3 above may have set INEX2.
607 | If the int operation results in more than LEN digits,
Dsasin.S34 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
Dsatanh.S41 | 5. (|X| > 1) Generate an invalid operation by 0 * infinity.
/arch/m68k/hp300/
DREADME.hp30013 every packet. This doesn't make for very speedy operation.
/arch/tile/
DKconfig.debug12 early before the console code is initialized. For normal operation
/arch/arc/
DKconfig.debug13 early before the console code is initialized. For normal operation
/arch/xtensa/
DKconfig.debug31 Correct operation of this instruction requires some cooperation from hardware
/arch/arm/kvm/
Dinterrupts_head.S590 .macro set_hstr operation argument
593 .if \operation == vmentry
617 .if \operation != vmentry
618 .if \operation == vmexit
632 .macro set_hdcr operation argument
635 .if \operation == vmentry
/arch/arm/mm/
DKconfig857 so that the cache operation has the desired effect.
927 clean operation followed immediately by an invalidate operation,
933 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
936 operation (offset 0x7FC). This operation runs in background so that
940 Invalidate by Way operation. Revisions prior to r3p1 are affected by
944 bool "PL310 errata: cache sync operation may be faulty"
948 Under some condition the effect of cache sync operation on
949 the store buffer still remains when the operation completes.
952 is to replace the normal offset of cache sync operation (0x730)
954 This has the same effect as the cache sync operation: store buffer
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/arch/s390/include/uapi/asm/
Ddasd.h197 unsigned char operation:3; /* cache operation mode */ member
/arch/unicore32/
DKconfig.debug25 early before the console code is initialized. For normal operation
/arch/arm/boot/dts/
Dimx27-phytec-phycore-som.dtsi101 /* SW1A and SW1B joined operation */
109 /* SW2A and SW2B joined operation */
/arch/ia64/kvm/
Dkvm_fw.c99 u64 operation; member
112 status = ia64_pal_cache_flush(args->cache_type, args->operation, in remote_pal_cache_flush()
134 args.operation = gr30; in pal_cache_flush()
/arch/x86/crypto/
Daesni-intel_asm.S215 XMM2 XMM3 XMM4 XMMDst TMP6 TMP7 i i_seq operation argument
220 _get_AAD_loop\num_initial_blocks\operation:
227 jne _get_AAD_loop\num_initial_blocks\operation
229 je _get_AAD_loop2_done\num_initial_blocks\operation
231 _get_AAD_loop2\num_initial_blocks\operation:
235 jne _get_AAD_loop2\num_initial_blocks\operation
236 _get_AAD_loop2_done\num_initial_blocks\operation:
334 jl _initial_blocks_done\num_initial_blocks\operation
435 _initial_blocks_done\num_initial_blocks\operation:
453 XMM2 XMM3 XMM4 XMMDst TMP6 TMP7 i i_seq operation argument
[all …]
/arch/ia64/include/asm/sn/
Dsn_sal.h652 sn_register_xp_addr_region(u64 paddr, u64 len, int operation) in sn_register_xp_addr_region() argument
656 (u64)operation, 0, 0, 0, 0); in sn_register_xp_addr_region()
671 int virtual, int operation) in sn_register_nofault_code() argument
/arch/alpha/kernel/
Dsmp.c511 send_ipi_message(const struct cpumask *to_whom, enum ipi_message_type operation) in send_ipi_message() argument
517 set_bit(operation, &ipi_data[i].bits); in send_ipi_message()
/arch/mn10300/kernel/
Dswitch_to.S3 # MN10300 Context switch operation

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