| /arch/arm/mach-shmobile/ |
| D | clock-r8a7790.c | 109 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
111 SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
112 SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
118 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
119 SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
120 SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
121 SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
122 SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
123 SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
124 SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
[all …]
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| D | clock-r8a7791.c | 101 SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
103 SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
109 SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
110 SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
111 SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
112 SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
114 SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
115 SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
116 SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
122 &pll1_clk,
[all …]
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| D | clock-r8a73a4.c | 184 PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
189 SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
354 &pll1_clk,
390 [DIV4_I] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 20, 0x0dff, CLK_ENABLE_ON_INIT),
391 [DIV4_M3] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
392 [DIV4_B] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 8, 0x0dff, CLK_ENABLE_ON_INIT),
393 [DIV4_M1] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 4, 0x1dff, 0),
394 [DIV4_M2] = SH_CLK_DIV4(&pll1_clk, FRQCRA, 0, 0x1dff, 0),
395 [DIV4_ZX] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 12, 0x0dff, 0),
396 [DIV4_ZS] = SH_CLK_DIV4(&pll1_clk, FRQCRB, 8, 0x0dff, 0),
[all …]
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| D | clock-sh73a0.c | 128 static struct clk pll1_clk = { variable
160 SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
161 SH_FIXED_RATIO_CLK(pll1_div7_clk, pll1_clk, div7);
162 SH_FIXED_RATIO_CLK(pll1_div13_clk, pll1_clk, div13);
180 &pll1_clk,
227 SH_CLK_DIV4(&pll1_clk, _reg, _bit, _mask, _flags)
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| /arch/arm/mach-davinci/ |
| D | dm646x.c | 75 static struct clk pll1_clk = { variable
84 .parent = &pll1_clk,
91 .parent = &pll1_clk,
98 .parent = &pll1_clk,
105 .parent = &pll1_clk,
112 .parent = &pll1_clk,
119 .parent = &pll1_clk,
126 .parent = &pll1_clk,
133 .parent = &pll1_clk,
140 .parent = &pll1_clk,
[all …]
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| D | dm365.c | 73 static struct clk pll1_clk = { variable
82 .parent = &pll1_clk,
88 .parent = &pll1_clk,
95 .parent = &pll1_clk,
101 .parent = &pll1_clk,
108 .parent = &pll1_clk,
115 .parent = &pll1_clk,
122 .parent = &pll1_clk,
129 .parent = &pll1_clk,
136 .parent = &pll1_clk,
[all …]
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| D | dm644x.c | 60 static struct clk pll1_clk = { variable
69 .parent = &pll1_clk,
76 .parent = &pll1_clk,
83 .parent = &pll1_clk,
90 .parent = &pll1_clk,
97 .parent = &pll1_clk,
103 .parent = &pll1_clk,
289 CLK(NULL, "pll1", &pll1_clk),
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| D | dm355.c | 63 static struct clk pll1_clk = { variable
72 .parent = &pll1_clk,
78 .parent = &pll1_clk,
85 .parent = &pll1_clk,
92 .parent = &pll1_clk,
99 .parent = &pll1_clk,
106 .parent = &pll1_clk,
341 CLK(NULL, "pll1", &pll1_clk),
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| D | da850.c | 136 static struct clk pll1_clk = { variable
145 .parent = &pll1_clk,
151 .parent = &pll1_clk,
158 .parent = &pll1_clk,
440 CLK(NULL, "pll1", &pll1_clk),
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