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/arch/microblaze/lib/
Dfastcopy.S87 lwi r12, r6, 12 /* t4 = *(s + 12) */
91 swi r12, r5, 12 /* *(d + 12) = t4 */
95 lwi r12, r6, 28 /* t4 = *(s + 28) */
99 swi r12, r5, 28 /* *(d + 28) = t4 */
119 lwi r12, r8, 4 /* v = *(as + 4) */
120 bsrli r9, r12, 8 /* t1 = v >> 8 */
123 bslli r11, r12, 24 /* h = v << 24 */
124 lwi r12, r8, 8 /* v = *(as + 8) */
125 bsrli r9, r12, 8 /* t1 = v >> 8 */
128 bslli r11, r12, 24 /* h = v << 24 */
[all …]
/arch/arm/mach-omap2/
Dsram34xx.S122 stmfd sp!, {r1-r12, lr} @ store regs to stack
169 mov r12, r2
182 ldmfd sp!, {r1-r12, pc} @ restore regs and return
185 ldr r12, [r11]
186 bic r12, r12, #FIXEDDELAY_MASK
187 orr r12, r12, #FIXEDDELAY_DEFAULT
188 orr r12, r12, #DLLIDLE_MASK
189 str r12, [r11] @ (no OCP barrier needed)
193 ldr r12, [r11]
194 bic r12, r12, #DLLIDLE_MASK
[all …]
Domap-smc.S28 stmfd sp!, {r2-r12, lr}
29 mov r12, r0
33 ldmfd sp!, {r2-r12, pc}
45 stmfd sp!, {r4-r12, lr}
50 mov r12, #0x00 @ Secure Service ID
56 ldmfd sp!, {r4-r12, pc}
69 mov r12, r0 @ Copy the secure service ID
77 stmfd sp!, {r1-r12, lr}
78 ldr r12, =0x104
81 ldmfd sp!, {r1-r12, pc}
[all …]
/arch/powerpc/include/asm/
Dexception-64e.h98 mtspr SPRN_SPRG_TLB_SCRATCH,r12; \
99 mfspr r12,SPRN_SPRG_TLB_EXFRAME; \
100 std r10,EX_TLB_R10(r12); \
102 std r11,EX_TLB_R11(r12); \
104 std r13,EX_TLB_R13(r12); \
106 std r14,EX_TLB_R14(r12); \
107 addi r14,r12,EX_TLB_SIZE; \
108 std r15,EX_TLB_R15(r12); \
110 std r16,EX_TLB_R16(r12); \
112 std r10,EX_TLB_CR(r12); \
[all …]
/arch/arc/lib/
Dstrchr-700.S34 sub r12,r2,r7
35 bic_s r12,r12,r2
36 and r12,r12,r4
37 brne.d r12,0,.Lfound0_ua
40 sub r12,r6,r7
41 bic r12,r12,r6
43 and r7,r12,r4
47 and r12,r12,r4
48 breq r12,0,.Loop ; For speed, we want this branch to be unaligned.
49 lsr_s r12,r12,7
[all …]
Dstrlen.S25 sub r12,r6,r7
26 bic r12,r12,r6
27 or.eq r12,r12,r1
28 and r12,r12,r5
29 brne r12,0,.Learly_end
38 sub r12,r6,r4
39 bic r12,r12,r6
40 bmsk.ne r12,r12,r7
41 or.eq r12,r12,r1
42 and r12,r12,r5
[all …]
Dmemcpy-700.S17 ld_s r12,[r1,0]
21 st.ab r12,[r5,4]
22 ld.a r12,[r1,4]
26 st.ab r12,[r5,4]
27 ld.a r12,[r1,8]
35 xor_s r12,r12,r3
36 bmsk r12,r12,r2
37 xor_s r12,r12,r3
41 xor_s r3,r3,r12
43 xor_s r12,r12,r3
[all …]
Dmemcmp.S20 or r12,r0,r1
21 asl_s r12,r12,30
23 brls r2,r12,.Lbytewise
29 ld_s r12,[r1,4]
33 brne WORD2,r12,.Lodd
60 asl r12,r5,r1
62 lsr_s r12,r12,1
64 sub r0,r2,r12
67 xor r0,WORD2,r12
74 asl_s r12,r12,r1
[all …]
/arch/powerpc/platforms/pseries/
DhvCall.S94 ld r12,hcall_tracepoint_refcount@toc(r2); \
95 std r12,32(r1); \
96 cmpdi r12,0; \
149 ld r12,STK_PARAM(R4)(r1)
150 std r4, 0(r12)
151 std r5, 8(r12)
152 std r6, 16(r12)
153 std r7, 24(r12)
176 ld r12,STK_PARAM(R4)(r1)
177 std r4,0(r12)
[all …]
/arch/powerpc/kvm/
Dbook3s_rmhandlers.S65 mtspr SPRN_SPRG_SCRATCH1, r12 /* Save r12 */
66 mfcr r12
69 2: mtcr r12
70 mfspr r12, SPRN_SPRG_SCRATCH1
75 stw r12, HSTATE_SCRATCH1(r13)
76 mfspr r12, SPRN_SPRG_SCRATCH1
77 stw r12, HSTATE_SCRATCH0(r13)
78 lbz r12, HSTATE_IN_GUEST(r13)
79 cmpwi r12, KVM_GUEST_MODE_NONE
82 lwz r12, HSTATE_SCRATCH1(r13)
[all …]
/arch/avr32/lib/
Dfindbit.S19 1: ld.w r8, r12[0]
22 sub r12, -4
38 add r12, r8
43 ld.w r8, r12[0]
45 sub r12, -4
55 1: ld.w r8, r12[0]
58 sub r12, -4
72 min r12, r11, r10
73 retal r12
83 1: ld.w r8, r12[0]
[all …]
Dio-readsb.S11 1: ld.ub r8, r12[0]
14 reteq r12
25 reteq r12
33 1: ldins.b r8:t, r12[0]
34 ldins.b r8:u, r12[0]
35 ldins.b r8:l, r12[0]
36 ldins.b r8:b, r12[0]
42 reteq r12
44 3: ld.ub r8, r12[0]
49 retal r12
Dstrnlen_user.S22 add r8, r12
29 mov r10, r12
31 10: ld.ub r8, r12++
37 sub r12, -1
38 2: sub r12, r10
39 retal r12
44 cp.w r12, 0 /* addr must always be < TASK_SIZE */
49 sub r11, lr, r12
52 cp.w r12, r9
55 1: popm pc, r12=0
Dio-writesb.S13 st.b r12[0], r8
14 reteq r12
25 reteq r12
35 st.b r12[0], r9
37 st.b r12[0], r9
39 st.b r12[0], r9
40 st.b r12[0], r8
45 reteq r12
49 st.b r12[0], r8
52 retal r12
D__avr32_asr64.S16 cp.w r12, 0
17 reteq r12
19 rsub r9, r12, 32
23 lsr r10, r10, r12
24 asr r11, r11, r12
26 retal r12
31 retal r12
D__avr32_lsl64.S16 cp.w r12, 0
17 reteq r12
19 rsub r9, r12, 32
23 lsl r10, r10, r12
24 lsl r11, r11, r12
26 retal r12
31 retal r12
D__avr32_lsr64.S16 cp.w r12, 0
17 reteq r12
19 rsub r9, r12, 32
23 lsr r11, r11, r12
24 lsr r10, r10, r12
26 retal r12
31 retal r12
/arch/cris/arch-v32/lib/
Dchecksum.S14 ;; r12 - checksum
32 addc $r0,$r12
33 addc $r1,$r12
34 addc $r2,$r12
35 addc $r3,$r12
36 addc $r4,$r12
37 addc $r5,$r12
38 addc $r6,$r12
39 addc $r7,$r12
40 addc $r8,$r12
[all …]
/arch/powerpc/platforms/cell/
Dbeat_hvCall.S109 ld r12,STK_PARAM(R4)(r1)
110 std r4, 0(r12)
140 ld r12,STK_PARAM(R4)(r1)
141 std r4, 0(r12)
142 std r5, 8(r12)
172 ld r12,STK_PARAM(R4)(r1)
173 std r4, 0(r12)
174 std r5, 8(r12)
175 std r6, 16(r12)
205 ld r12,STK_PARAM(R4)(r1)
[all …]
/arch/arm/mach-imx/
Dssi-fiq.S45 ldr r12, .L_imx_ssi_fiq_base
51 ldr r11, [r12, #SSI_SIER]
56 ldr r11, [r12, #SSI_SISR]
67 strh r11, [r12, #SSI_STX0]
70 strh r11, [r12, #SSI_STX0]
73 strh r11, [r12, #SSI_STX0]
76 strh r11, [r12, #SSI_STX0]
87 ldr r11, [r12, #SSI_SIER]
92 ldr r11, [r12, #SSI_SISR]
104 ldr r11, [r12, #SSI_SACNT]
[all …]
/arch/powerpc/kernel/
Dhead_40x.S121 stw r12,GPR12(r11); \
125 mfspr r12,SPRN_SPRG_SCRATCH1; \
126 stw r12,GPR11(r11); \
130 mfspr r12,SPRN_SRR0; \
163 stw r12,GPR12(r11); \
167 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
168 stw r12,_DEAR(r11); /* since they may have had stuff */\
171 mfspr r12,SPRN_SRR2; \
266 stw r12, 0(r0)
269 mfspr r12, SPRN_PID
[all …]
/arch/cris/arch-v10/lib/
Dchecksum.S13 ;; r12 - checksum
39 add.d $r0,$r12
41 add.d $r1,$r12
43 add.d $r2,$r12
45 add.d $r3,$r12
47 add.d $r4,$r12
49 add.d $r5,$r12
51 add.d $r6,$r12
53 add.d $r7,$r12
55 add.d $r8,$r12
[all …]
/arch/arm/crypto/
Daes-armv4.S153 stmdb sp!,{r1,r4-r12,lr}
154 mov r12,r0 @ inp
158 ldrb r0,[r12,#3] @ load input data in endian-neutral
159 ldrb r4,[r12,#2] @ manner...
160 ldrb r5,[r12,#1]
161 ldrb r6,[r12,#0]
163 ldrb r1,[r12,#7]
165 ldrb r4,[r12,#6]
167 ldrb r5,[r12,#5]
168 ldrb r6,[r12,#4]
[all …]
/arch/powerpc/lib/
Dcrtsavres.S445 li r12,-192
446 stvx vr20,r12,r0
449 li r12,-176
450 stvx vr21,r12,r0
453 li r12,-160
454 stvx vr22,r12,r0
457 li r12,-144
458 stvx vr23,r12,r0
461 li r12,-128
462 stvx vr24,r12,r0
[all …]
/arch/arm/lib/
Dfloppydma.S17 ldrgtb r12, [r11, #-4]
18 ldrleb r12, [r11], #0
19 strb r12, [r10], #1
26 ldrgeb r12, [r10], #1
27 movlt r12, #0
28 strleb r12, [r11], #0
30 strb r12, [r11, #-4]

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