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Searched refs:regval (Results 1 – 16 of 16) sorted by relevance

/arch/arm/mach-w90x900/
Dgpio.c58 unsigned int regval; in nuc900_gpio_get() local
60 regval = __raw_readl(pio); in nuc900_gpio_get()
61 regval &= GPIO_GPIO(offset); in nuc900_gpio_get()
63 return (regval != 0); in nuc900_gpio_get()
70 unsigned int regval; in nuc900_gpio_set() local
75 regval = __raw_readl(pio); in nuc900_gpio_set()
78 regval |= GPIO_GPIO(offset); in nuc900_gpio_set()
80 regval &= ~GPIO_GPIO(offset); in nuc900_gpio_set()
82 __raw_writel(regval, pio); in nuc900_gpio_set()
91 unsigned int regval; in nuc900_dir_input() local
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Dirq.c85 unsigned long regval; in nuc900_group_enable() local
87 regval = __raw_readl(REG_AIC_GEN); in nuc900_group_enable()
90 regval |= groupen; in nuc900_group_enable()
92 regval &= ~groupen; in nuc900_group_enable()
94 __raw_writel(regval, REG_AIC_GEN); in nuc900_group_enable()
/arch/arm/mach-omap2/
Domap_phy_internal.c70 u32 regval; in am35x_musb_reset() local
73 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
75 regval |= AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
76 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
78 regval &= ~AM35XX_USBOTGSS_SW_RST; in am35x_musb_reset()
79 omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
81 regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); in am35x_musb_reset()
124 u32 regval; in am35x_musb_clear_irq() local
126 regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); in am35x_musb_clear_irq()
127 regval |= AM35XX_USBOTGSS_INT_CLR; in am35x_musb_clear_irq()
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Dsdram-nokia.c158 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval() argument
161 static int set_sdrc_timing_regval(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval()
171 *regval &= ~(mask << st_bit); in set_sdrc_timing_regval()
172 *regval |= ticks << st_bit; in set_sdrc_timing_regval()
195 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval_ps() argument
198 static int set_sdrc_timing_regval_ps(u32 *regval, int st_bit, int end_bit, in set_sdrc_timing_regval_ps()
211 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks, in set_sdrc_timing_regval_ps()
214 ret = set_sdrc_timing_regval(regval, st_bit, end_bit, ticks); in set_sdrc_timing_regval_ps()
Dgpmc.c625 u32 regval; in gpmc_configure() local
637 regval = gpmc_read_reg(GPMC_CONFIG); in gpmc_configure()
639 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ in gpmc_configure()
641 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ in gpmc_configure()
642 gpmc_write_reg(GPMC_CONFIG, regval); in gpmc_configure()
709 u32 regval; in gpmc_irq_endis() local
713 regval = gpmc_read_reg(GPMC_IRQENABLE); in gpmc_irq_endis()
715 regval |= gpmc_client_irq[i].bitmask; in gpmc_irq_endis()
717 regval &= ~gpmc_client_irq[i].bitmask; in gpmc_irq_endis()
718 gpmc_write_reg(GPMC_IRQENABLE, regval); in gpmc_irq_endis()
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/arch/sparc/include/asm/
Dturbosparc.h105 static inline void turbosparc_set_ccreg(unsigned long regval) in turbosparc_set_ccreg() argument
109 : "r" (regval), "r" (0x600), "i" (ASI_M_MMUREGS) in turbosparc_set_ccreg()
115 unsigned long regval; in turbosparc_get_ccreg() local
118 : "=r" (regval) in turbosparc_get_ccreg()
120 return regval; in turbosparc_get_ccreg()
Dviking.h145 static inline void viking_set_bpreg(unsigned long regval) in viking_set_bpreg() argument
149 : "r" (regval), "i" (ASI_M_ACTION) in viking_set_bpreg()
155 unsigned long regval; in viking_get_bpreg() local
158 : "=r" (regval) in viking_get_bpreg()
160 return regval; in viking_get_bpreg()
Dpgtsrmmu.h153 void srmmu_set_mmureg(unsigned long regval);
/arch/mips/loongson/lemote-2f/
Dclock.c97 int regval; in clk_set_rate() local
118 regval = LOONGSON_CHIPCFG(0); in clk_set_rate()
119 regval = (regval & ~0x7) | (pos->driver_data - 1); in clk_set_rate()
120 LOONGSON_CHIPCFG(0) = regval; in clk_set_rate()
/arch/sparc/kernel/
Dauxio_32.c87 unsigned char regval; in set_auxio() local
94 regval = sbus_readb(auxio_register); in set_auxio()
95 sbus_writeb(((regval | bits_on) & ~bits_off) | AUXIO_ORMEIN4M, in set_auxio()
Dauxio_64.c34 u8 regval, newval; in __auxio_rmw() local
38 regval = (ebus ? in __auxio_rmw()
41 newval = regval | bits_on; in __auxio_rmw()
/arch/ia64/sn/kernel/
Dirq.c422 u64 regval; in sn_check_intr() local
441 regval = pcireg_intr_status_get(pcibus_info); in sn_check_intr()
445 regval &= 0xff; in sn_check_intr()
446 if (sn_irq_info->irq_int_bit & regval & in sn_check_intr()
448 regval &= ~(sn_irq_info->irq_int_bit & regval); in sn_check_intr()
453 sn_irq_info->irq_last_intr = regval; in sn_check_intr()
/arch/arm/mach-omap1/
Dclock.c232 u16 regval; in omap1_clk_set_rate_dsp_domain() local
240 regval = __raw_readw(DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
241 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_dsp_domain()
242 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_dsp_domain()
243 __raw_writew(regval, DSP_CKCTL); in omap1_clk_set_rate_dsp_domain()
262 u16 regval; in omap1_clk_set_rate_ckctl_arm() local
270 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
271 regval &= ~(3 << clk->rate_offset); in omap1_clk_set_rate_ckctl_arm()
272 regval |= dsor_exp << clk->rate_offset; in omap1_clk_set_rate_ckctl_arm()
273 regval = verify_ckctl_value(regval); in omap1_clk_set_rate_ckctl_arm()
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/arch/arm/mach-lpc32xx/
Dcommon.h51 extern u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval);
Dclock.c208 u32 clk_get_pllrate_from_reg(u32 inputclk, u32 regval) in clk_get_pllrate_from_reg() argument
215 if ((regval & LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS) != 0) in clk_get_pllrate_from_reg()
217 if ((regval & LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS) != 0) in clk_get_pllrate_from_reg()
219 if ((regval & LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK) != 0) in clk_get_pllrate_from_reg()
221 pllcfg.pll_m = 1 + ((regval >> 1) & 0xFF); in clk_get_pllrate_from_reg()
222 pllcfg.pll_n = 1 + ((regval >> 9) & 0x3); in clk_get_pllrate_from_reg()
223 pllcfg.pll_p = pll_postdivs[((regval >> 11) & 0x3)]; in clk_get_pllrate_from_reg()
/arch/arm/mach-at91/
Dclock.c221 u32 regval = 0; in pmc_periph_mode() local
229 regval |= AT91_PMC_PCR_CMD; /* write command */ in pmc_periph_mode()
230 regval |= clk->pid & AT91_PMC_PCR_PID; /* peripheral selection */ in pmc_periph_mode()
231 regval |= AT91_PMC_PCR_DIV(clk->div); in pmc_periph_mode()
233 regval |= AT91_PMC_PCR_EN; /* enable clock */ in pmc_periph_mode()
234 at91_pmc_write(AT91_PMC_PCR, regval); in pmc_periph_mode()