/arch/x86/kvm/ |
D | mmutrace.h | 13 __field(__u32, role) \ 20 __entry->role = sp->role.word; \ 29 union kvm_mmu_page_role role; \ 31 role.word = __entry->role; \ 35 __entry->gfn, role.level, \ 36 role.cr4_pae ? " pae" : "", \ 37 role.quadrant, \ 38 role.direct ? " direct" : "", \ 39 access_str[role.access], \ 40 role.invalid ? " invalid" : "", \ [all …]
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D | mmu_audit.c | 149 rmapp = gfn_to_rmap(kvm, gfn, rev_sp->role.level); in inspect_spte_has_rmap() 178 if (sp->role.level != PT_PAGE_TABLE_LEVEL) in check_mappings_rmap() 195 if (sp->role.direct || sp->unsync || sp->role.invalid) in audit_write_protection() 205 sp->gfn, sp->role.word); in audit_write_protection()
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D | mmu.c | 758 if (!sp->role.direct) in kvm_mmu_page_get_gfn() 761 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); in kvm_mmu_page_get_gfn() 766 if (sp->role.direct) in kvm_mmu_page_set_gfn() 1047 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); in rmap_add() 1059 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level); in rmap_remove() 1134 WARN_ON(page_header(__pa(sptep))->role.level == in __drop_large_spte() 1451 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level); in rmap_recycle() 1453 kvm_unmap_rmapp(vcpu->kvm, rmapp, NULL, gfn, sp->role.level, 0); in rmap_recycle() 1521 if (!sp->role.direct) in kvm_mmu_free_page() 1723 if ((_sp)->role.direct || (_sp)->role.invalid) {} else [all …]
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D | paging_tmpl.h | 476 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte); in FNAME() 534 if (sp->role.level > PT_PAGE_TABLE_LEVEL) in FNAME() 537 if (sp->role.direct) in FNAME() 822 WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); in FNAME() 825 offset = sp->role.quadrant << PT64_LEVEL_BITS; in FNAME() 944 BUG_ON(sp->role.direct); in FNAME() 969 pte_access = sp->role.access; in FNAME()
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/arch/arm/mach-omap2/ |
D | omap_hwmod_54xx_data.c | 354 { .role = "32khz_clk", .clk = "dss_32khz_clk" }, 355 { .role = "sys_clk", .clk = "dss_sys_clk" }, 356 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 401 { .role = "sys_clk", .clk = "dss_sys_clk" }, 449 { .role = "sys_clk", .clk = "dss_sys_clk" }, 469 { .role = "sys_clk", .clk = "dss_sys_clk" }, 508 { .role = "sys_clk", .clk = "dss_sys_clk" }, 548 { .role = "ick", .clk = "l3_iclk_div" }, 642 { .role = "dbclk", .clk = "gpio1_dbclk" }, 664 { .role = "dbclk", .clk = "gpio2_dbclk" }, [all …]
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D | omap_hwmod_44xx_data.c | 577 { .role = "sys_clk", .clk = "dss_sys_clk" }, 578 { .role = "tv_clk", .clk = "dss_tv_clk" }, 579 { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, 686 { .role = "sys_clk", .clk = "dss_sys_clk" }, 718 { .role = "sys_clk", .clk = "dss_sys_clk" }, 770 { .role = "sys_clk", .clk = "dss_sys_clk" }, 822 { .role = "ick", .clk = "dss_fck" }, 1019 { .role = "dbclk", .clk = "gpio1_dbclk" }, 1041 { .role = "dbclk", .clk = "gpio2_dbclk" }, 1064 { .role = "dbclk", .clk = "gpio3_dbclk" }, [all …]
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D | omap_hwmod_7xx_data.c | 435 { .role = "dss_clk", .clk = "dss_dss_clk" }, 436 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, 437 { .role = "32khz_clk", .clk = "dss_32khz_clk" }, 438 { .role = "video2_clk", .clk = "dss_video2_clk" }, 439 { .role = "video1_clk", .clk = "dss_video1_clk" }, 440 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, 528 { .role = "sys_clk", .clk = "dss_hdmi_clk" }, 614 { .role = "dbclk", .clk = "gpio1_dbclk" }, 636 { .role = "dbclk", .clk = "gpio2_dbclk" }, 659 { .role = "dbclk", .clk = "gpio3_dbclk" }, [all …]
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D | omap_hwmod_2430_data.c | 259 { .role = "pad_fck", .clk = "mcbsp_clks" }, 260 { .role = "prcm_fck", .clk = "func_96m_ck" }, 372 { .role = "dbck", .clk = "mmchsdb1_fck" }, 400 { .role = "dbck", .clk = "mmchsdb2_fck" },
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D | omap_hwmod_3xxx_data.c | 597 { .role = "softreset_uart1_fck", .clk = "uart1_fck" }, 639 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 640 { .role = "tv_clk", .clk = "dss_tv_fck" }, 642 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 750 { .role = "sys_clk", .clk = "dss2_alwon_fck" }, 771 { .role = "ick", .clk = "dss_ick" }, 792 { .role = "tv_dac_clk", .clk = "dss_96m_fck" }, 927 { .role = "dbclk", .clk = "gpio1_dbck", }, 952 { .role = "dbclk", .clk = "gpio2_dbck", }, 977 { .role = "dbclk", .clk = "gpio3_dbck", }, [all …]
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D | omap_hwmod_33xx_data.c | 213 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, 214 { .role = "dbg_clka", .clk = "dbg_clka_ck" }, 252 { .role = "dbclk", .clk = "gpio0_dbclk" },
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D | omap_hwmod_2420_data.c | 190 { .role = "pad_fck", .clk = "mcbsp_clks" }, 191 { .role = "prcm_fck", .clk = "func_96m_ck" },
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D | omap_hwmod_2xxx_ipblock_data.c | 546 { .role = "tv_clk", .clk = "dss_54m_fck" }, 547 { .role = "sys_clk", .clk = "dss2_fck" }, 588 { .role = "ick", .clk = "dss_ick" },
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D | omap_hwmod_43xx_data.c | 78 { .role = "dbclk", .clk = "gpio0_dbclk" }, 280 { .role = "dbclk", .clk = "gpio4_dbclk" }, 301 { .role = "dbclk", .clk = "gpio5_dbclk" },
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D | omap_hwmod_33xx_43xx_ipblock_data.c | 590 { .role = "dbclk", .clk = "gpio1_dbclk" }, 611 { .role = "dbclk", .clk = "gpio2_dbclk" }, 632 { .role = "dbclk", .clk = "gpio3_dbclk" },
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D | omap_hwmod.h | 216 const char *role; member
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D | omap_device.c | 109 _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk); in _add_hwmod_clocks_clkdev()
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D | omap_hwmod.c | 946 pr_debug("omap_hwmod: enable %s:%s\n", oc->role, in _enable_optional_clocks() 961 pr_debug("omap_hwmod: disable %s:%s\n", oc->role, in _disable_optional_clocks()
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/arch/arm/kvm/ |
D | interrupts.S | 180 @ Reset Hyp-role
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/arch/arm/boot/dts/ |
D | imx51-digi-connectcore-som.dtsi | 204 /* Device role is not known, keep status disabled */
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/arch/x86/include/asm/ |
D | kvm_host.h | 217 union kvm_mmu_page_role role; member
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