| /arch/powerpc/lib/ |
| D | xor_vmx.c | 60 DEFINE(v1); in xor_altivec_2()
68 LOAD(v1); in xor_altivec_2()
70 XOR(v1, v2); in xor_altivec_2()
71 STORE(v1); in xor_altivec_2()
73 v1 += 4; in xor_altivec_2()
84 DEFINE(v1); in xor_altivec_3()
93 LOAD(v1); in xor_altivec_3()
96 XOR(v1, v2); in xor_altivec_3()
97 XOR(v1, v3); in xor_altivec_3()
98 STORE(v1); in xor_altivec_3()
[all …]
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| /arch/arm64/crypto/ |
| D | aes-ce-ccm-core.S | 25 eor v1.16b, v1.16b, v1.16b
29 ins v1.b[0], w7
30 ext v1.16b, v1.16b, v1.16b, #1 /* rotate in the input bytes */
33 eor v0.16b, v0.16b, v1.16b
60 ld1 {v1.16b}, [x1], #16 /* load next input block */
61 eor v0.16b, v0.16b, v1.16b /* xor with mac */
78 9: ext v1.16b, v1.16b, v1.16b, #1
81 eor v0.16b, v0.16b, v1.16b
96 ld1 {v1.2d}, [x1] /* load 1st ctriv */
104 aese v1.16b, v4.16b
[all …]
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| D | aes-modes.S | 43 encrypt_block2x v0, v1, w3, x2, x6, w7
48 decrypt_block2x v0, v1, w3, x2, x6, w7
55 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
60 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
89 encrypt_block2x v0, v1, w3, x2, x6, w7
93 decrypt_block2x v0, v1, w3, x2, x6, w7
97 encrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
101 decrypt_block4x v0, v1, v2, v3, w3, x2, x6, w7
124 ld1 {v0.16b-v1.16b}, [x1], #32 /* get 2 pt blocks */
126 st1 {v0.16b-v1.16b}, [x0], #32
[all …]
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| /arch/x86/lib/ |
| D | x86-opcode-map.txt | 23 # (v1): this opcode only supports 128bit VEX.
337 # Many AVX instructions lack v1 superscript, according to Intel AVX-Prgramming
339 10: vmovups Vps,Wps | vmovupd Vpd,Wpd (66) | vmovss Vx,Hx,Wss (F3),(v1) | vmovsd Vx,Hx,Wsd (F2),(v1)
340 … vmovups Wps,Vps | vmovupd Wpd,Vpd (66) | vmovss Wss,Hx,Vss (F3),(v1) | vmovsd Wsd,Hx,Vsd (F2),(v1)
341 12: vmovlps Vq,Hq,Mq (v1) | vmovhlps Vq,Hq,Uq (v1) | vmovlpd Vq,Hq,Mq (66),(v1) | vmovsldup Vx,Wx (…
342 13: vmovlps Mq,Vq (v1) | vmovlpd Mq,Vq (66),(v1)
345 16: vmovhps Vdq,Hq,Mq (v1) | vmovlhps Vdq,Hq,Uq (v1) | vmovhpd Vdq,Hq,Mq (66),(v1) | vmovshdup Vx,W…
346 17: vmovhps Mq,Vq (v1) | vmovhpd Mq,Vq (66),(v1)
366 …s Vps,Qpi | cvtpi2pd Vpd,Qpi (66) | vcvtsi2ss Vss,Hss,Ey (F3),(v1) | vcvtsi2sd Vsd,Hsd,Ey (F2),(v1)
368 …tps2pi Ppi,Wps | cvttpd2pi Ppi,Wpd (66) | vcvttss2si Gy,Wss (F3),(v1) | vcvttsd2si Gy,Wsd (F2),(v1)
[all …]
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| /arch/powerpc/boot/dts/fsl/ |
| D | interlaken-lac-portals.dtsi | 39 compatible = "fsl,interlaken-lac-portal-v1.0";
44 compatible = "fsl,interlaken-lac-portal-v1.0";
49 compatible = "fsl,interlaken-lac-portal-v1.0";
54 compatible = "fsl,interlaken-lac-portal-v1.0";
59 compatible = "fsl,interlaken-lac-portal-v1.0";
64 compatible = "fsl,interlaken-lac-portal-v1.0";
69 compatible = "fsl,interlaken-lac-portal-v1.0";
74 compatible = "fsl,interlaken-lac-portal-v1.0";
79 compatible = "fsl,interlaken-lac-portal-v1.0";
84 compatible = "fsl,interlaken-lac-portal-v1.0";
[all …]
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| D | qoriq-raid1.0-0.dtsi | 36 compatible = "fsl,raideng-v1.0";
43 compatible = "fsl,raideng-v1.0-job-queue";
50 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
57 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
65 compatible = "fsl,raideng-v1.0-job-queue";
72 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-hp-ring";
79 compatible = "fsl,raideng-v1.0-job-ring", "fsl,raideng-v1.0-lp-ring";
|
| /arch/mips/kernel/ |
| D | cpu-bugs64.c | 45 static inline void mult_sh_align_mod(long *v1, long *v2, long *w, in mult_sh_align_mod() argument
115 *v1 = lv1; in mult_sh_align_mod()
122 long v1[8], v2[8], w[8]; in check_mult_sh() local
136 mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0); in check_mult_sh()
137 mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1); in check_mult_sh()
138 mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2); in check_mult_sh()
139 mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3); in check_mult_sh()
140 mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4); in check_mult_sh()
141 mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5); in check_mult_sh()
142 mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6); in check_mult_sh()
[all …]
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| /arch/mips/include/asm/ |
| D | stackframe.h | 37 mflhxu v1
38 LONG_S v1, PT_LO(sp)
39 mflhxu v1
40 LONG_S v1, PT_HI(sp)
41 mflhxu v1
42 LONG_S v1, PT_ACX(sp)
44 mfhi v1
54 LONG_S v1, PT_HI(sp)
55 mflo v1
62 LONG_S v1, PT_LO(sp)
[all …]
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| D | regdef.h | 25 #define v1 $3 macro
68 #define v1 $3 macro
|
| /arch/powerpc/platforms/ps3/ |
| D | repository.c | 66 u64 v1, u64 v2, const char *func, int line) in _dump_node() argument
73 pr_devel("%s:%d: v1: %016llx\n", func, line, v1); in _dump_node()
125 u64 v1; in read_node() local
134 result = lv1_read_repository_node(lpar_id, n1, n2, n3, n4, &v1, in read_node()
144 dump_node(lpar_id, n1, n2, n3, n4, v1, v2); in read_node()
147 *_v1 = v1; in read_node()
151 if (v1 && !_v1) in read_node()
153 __func__, __LINE__, v1); in read_node()
187 u64 v1 = 0; in ps3_repository_read_bus_type() local
193 &v1, NULL); in ps3_repository_read_bus_type()
[all …]
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| /arch/mips/netlogic/common/ |
| D | reset.S | 109 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
110 mtcr v1, t1
112 mfcr v1, t1
113 andi v1, 0x1 /* wait for write_active == 0 */
114 bnez v1, 12b
117 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
118 mtcr v1, t1
120 mfcr v1, t1
121 andi v1, 0x1 /* wait for write_active == 0 */
122 bnez v1, 13b
[all …]
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| D | smpboot.S | 130 lw v1, BOOT_THREAD_MODE(v0) /* v1 - new thread mode */
131 sll v1, 1
132 beq v1, t2, 1f /* same as request value */
136 or t1, t2, v1 /* put in new value */
|
| /arch/arm/boot/dts/ |
| D | qcom-ipq8064.dtsi | 1 /dts-v1/;
18 enable-method = "qcom,kpss-acc-v1";
28 enable-method = "qcom,kpss-acc-v1";
100 compatible = "qcom,kpss-acc-v1";
105 compatible = "qcom,kpss-acc-v1";
122 compatible = "qcom,gsbi-v1.0.0";
132 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
142 compatible = "qcom,i2c-qup-v1.1.1";
157 compatible = "qcom,gsbi-v1.0.0";
167 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
[all …]
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| D | qcom-apq8064.dtsi | 1 /dts-v1/;
20 enable-method = "qcom,kpss-acc-v1";
30 enable-method = "qcom,kpss-acc-v1";
40 enable-method = "qcom,kpss-acc-v1";
50 enable-method = "qcom,kpss-acc-v1";
123 compatible = "qcom,kpss-acc-v1";
128 compatible = "qcom,kpss-acc-v1";
133 compatible = "qcom,kpss-acc-v1";
138 compatible = "qcom,kpss-acc-v1";
168 compatible = "qcom,gsbi-v1.0.0";
[all …]
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| D | qcom-msm8960.dtsi | 1 /dts-v1/;
21 enable-method = "qcom,kpss-acc-v1";
31 enable-method = "qcom,kpss-acc-v1";
102 compatible = "qcom,kpss-acc-v1";
107 compatible = "qcom,kpss-acc-v1";
124 compatible = "qcom,gsbi-v1.0.0";
133 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
| /arch/ia64/include/asm/sn/ |
| D | sn_sal.h | 186 ret_stuff.v1 = 0; in ia64_sn_get_console_nasid()
208 ret_stuff.v1 = 0; in ia64_sn_get_master_baseio_nasid()
226 ret_stuff.v1 = 0; in ia64_sn_get_klconfig_addr()
242 ret_stuff.v1 = 0; in ia64_sn_console_getc()
264 ret_stuff.v1 = 0; in ia64_sn_console_readc()
282 ret_stuff.v1 = 0; in ia64_sn_console_putc()
299 ret_stuff.v1 = 0; in ia64_sn_console_putb()
319 ret_stuff.v1 = 0; in ia64_sn_plat_specific_err_print()
336 ret_stuff.v1 = 0; in ia64_sn_plat_cpei_handler()
353 ret_stuff.v1 = 0; in ia64_sn_plat_set_error_handling_features()
[all …]
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| /arch/mips/lib/ |
| D | strncpy_user.S | 39 move v1, a1
41 1: EX(lbu, v0, (v1), .Lfault\@)
43 1: EX(lbue, v0, (v1), .Lfault\@)
45 PTR_ADDIU v1, 1
|
| D | csum_partial.S | 62 sltu v1, sum, reg; \
63 ADD sum, v1; \
70 sltu v1, sum, reg; \
71 addu sum, v1; \
272 dsll32 v1, sum, 0
273 daddu sum, v1
274 sltu v1, sum, v1
276 addu sum, v1
283 wsbh v1, sum
284 movn sum, v1, t7
[all …]
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| D | strlen_user.S | 33 1: EX(lbu, v1, (v0), .Lfault\@)
35 1: EX(lbue, v1, (v0), .Lfault\@)
38 bnez v1, 1b
|
| /arch/mips/include/asm/mach-cavium-octeon/ |
| D | kernel-entry-init.h | 42 mfc0 v1, CP0_PRID_REG
46 beq v1, CP0_PRID_OCTEON_PASS1, skip
51 srl v1, 8
52 sll v1, 8
54 bne v1, CP0_PRID_OCTEON_CN30XX, skip
63 li v1, ~(7 << 7)
64 and v0, v0, v1
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| /arch/um/drivers/ |
| D | cow_user.c | 112 struct cow_header_v1 v1; member
295 if (n < offsetof(typeof(header->v1), backing_file)) { in read_cow_header()
300 magic = header->v1.magic; in read_cow_header()
302 version = header->v1.version; in read_cow_header()
304 version = be32toh(header->v1.version); in read_cow_header()
311 if (n < sizeof(header->v1)) { in read_cow_header()
316 *mtime_out = header->v1.mtime; in read_cow_header()
317 *size_out = header->v1.size; in read_cow_header()
318 *sectorsize_out = header->v1.sectorsize; in read_cow_header()
319 *bitmap_offset_out = sizeof(header->v1); in read_cow_header()
[all …]
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| /arch/ia64/include/asm/ |
| D | pal.h | 781 u64 v1; member
890 features_status->pal_bus_features_val = iprv.v1; in ia64_pal_bus_get_features()
916 conf->pcci_info_2.pcci2_data = iprv.v1; in ia64_pal_cache_config_info()
935 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff; in ia64_pal_cache_prot_info()
936 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32; in ia64_pal_cache_prot_info()
954 *progress = iprv.v1; in ia64_pal_cache_flush()
1000 *unique_caches = iprv.v1; in ia64_pal_cache_summary()
1025 *buffer_align = iprv.v1; in ia64_pal_copy_info()
1049 *data_regs = iprv.v1; in ia64_pal_debug_info()
1099 *(u64 *)bus_ratio = iprv.v1; in ia64_pal_freq_ratios()
[all …]
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| /arch/ia64/kvm/ |
| D | kvm_fw.c | 43 x.v1 = 0; \
51 x.v1 = 0; \
145 result.status = ia64_pal_cache_flush(gr29, gr30, &result.v1, in pal_cache_flush()
187 &result.v1); in pal_freq_base()
250 result.status = ia64_pal_proc_get_features(&result.v0, &result.v1, in pal_proc_get_features()
263 result.status = ia64_pal_register_info(in1, &result.v1, &result.v2); in pal_register_info()
300 result.v1 = vminfo2.pvi2_val; in pal_vm_summary()
314 (pal_tc_info_u_t *)&result.v1, &result.v2); in pal_vm_info()
509 result.v1 = (1L << 32) | 1L; in kvm_pal_emul()
516 &result.v1); in kvm_pal_emul()
[all …]
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| /arch/mips/kvm/ |
| D | locore.S | 106 mfhi v1
107 LONG_S v1, PT_HI(k1)
114 mfc0 v1, CP0_ENTRYHI
115 andi v1, 0xff
116 LONG_S v1, PT_HOST_ASID(k1)
119 mfc0 v1, CP0_DDATA_LO
120 LONG_S v1, PT_HOST_USERLOCAL(k1)
427 mfc0 v1, CP0_STATUS
429 or k0, v1, ST0_BEV
437 or v1, v1, (ST0_EXL | KSU_USER | ST0_IE)
[all …]
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| /arch/ia64/kernel/ |
| D | patch.c | 47 u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16); in ia64_patch() local
55 v1 = val << (shift - 64); in ia64_patch()
58 v0 = val << shift; v1 = val >> (64 - shift); in ia64_patch()
61 b[1] = (b1 & ~m1) | (v1 & m1); in ia64_patch()
|