1/dts-v1/; 2 3/include/ "skeleton.dtsi" 4 5#include <dt-bindings/interrupt-controller/arm-gic.h> 6#include <dt-bindings/clock/qcom,gcc-msm8960.h> 7#include <dt-bindings/soc/qcom,gsbi.h> 8 9/ { 10 model = "Qualcomm MSM8960"; 11 compatible = "qcom,msm8960"; 12 interrupt-parent = <&intc>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 interrupts = <1 14 0x304>; 18 19 cpu@0 { 20 compatible = "qcom,krait"; 21 enable-method = "qcom,kpss-acc-v1"; 22 device_type = "cpu"; 23 reg = <0>; 24 next-level-cache = <&L2>; 25 qcom,acc = <&acc0>; 26 qcom,saw = <&saw0>; 27 }; 28 29 cpu@1 { 30 compatible = "qcom,krait"; 31 enable-method = "qcom,kpss-acc-v1"; 32 device_type = "cpu"; 33 reg = <1>; 34 next-level-cache = <&L2>; 35 qcom,acc = <&acc1>; 36 qcom,saw = <&saw1>; 37 }; 38 39 L2: l2-cache { 40 compatible = "cache"; 41 cache-level = <2>; 42 }; 43 }; 44 45 cpu-pmu { 46 compatible = "qcom,krait-pmu"; 47 interrupts = <1 10 0x304>; 48 qcom,no-pc-write; 49 }; 50 51 soc: soc { 52 #address-cells = <1>; 53 #size-cells = <1>; 54 ranges; 55 compatible = "simple-bus"; 56 57 intc: interrupt-controller@2000000 { 58 compatible = "qcom,msm-qgic2"; 59 interrupt-controller; 60 #interrupt-cells = <3>; 61 reg = <0x02000000 0x1000>, 62 <0x02002000 0x1000>; 63 }; 64 65 timer@200a000 { 66 compatible = "qcom,kpss-timer", "qcom,msm-timer"; 67 interrupts = <1 1 0x301>, 68 <1 2 0x301>, 69 <1 3 0x301>; 70 reg = <0x0200a000 0x100>; 71 clock-frequency = <27000000>, 72 <32768>; 73 cpu-offset = <0x80000>; 74 }; 75 76 msmgpio: gpio@800000 { 77 compatible = "qcom,msm-gpio"; 78 gpio-controller; 79 #gpio-cells = <2>; 80 ngpio = <150>; 81 interrupts = <0 16 0x4>; 82 interrupt-controller; 83 #interrupt-cells = <2>; 84 reg = <0x800000 0x4000>; 85 }; 86 87 gcc: clock-controller@900000 { 88 compatible = "qcom,gcc-msm8960"; 89 #clock-cells = <1>; 90 #reset-cells = <1>; 91 reg = <0x900000 0x4000>; 92 }; 93 94 clock-controller@4000000 { 95 compatible = "qcom,mmcc-msm8960"; 96 reg = <0x4000000 0x1000>; 97 #clock-cells = <1>; 98 #reset-cells = <1>; 99 }; 100 101 acc0: clock-controller@2088000 { 102 compatible = "qcom,kpss-acc-v1"; 103 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 104 }; 105 106 acc1: clock-controller@2098000 { 107 compatible = "qcom,kpss-acc-v1"; 108 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 109 }; 110 111 saw0: regulator@2089000 { 112 compatible = "qcom,saw2"; 113 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 114 regulator; 115 }; 116 117 saw1: regulator@2099000 { 118 compatible = "qcom,saw2"; 119 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 120 regulator; 121 }; 122 123 gsbi5: gsbi@16400000 { 124 compatible = "qcom,gsbi-v1.0.0"; 125 reg = <0x16400000 0x100>; 126 clocks = <&gcc GSBI5_H_CLK>; 127 clock-names = "iface"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 ranges; 131 132 serial@16440000 { 133 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 134 reg = <0x16440000 0x1000>, 135 <0x16400000 0x1000>; 136 interrupts = <0 154 0x0>; 137 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 138 clock-names = "core", "iface"; 139 status = "disabled"; 140 }; 141 }; 142 143 qcom,ssbi@500000 { 144 compatible = "qcom,ssbi"; 145 reg = <0x500000 0x1000>; 146 qcom,controller-type = "pmic-arbiter"; 147 148 pmicintc: pmic@0 { 149 compatible = "qcom,pm8921"; 150 interrupt-parent = <&msmgpio>; 151 interrupts = <104 8>; 152 #interrupt-cells = <2>; 153 interrupt-controller; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 pwrkey@1c { 158 compatible = "qcom,pm8921-pwrkey"; 159 reg = <0x1c>; 160 interrupt-parent = <&pmicintc>; 161 interrupts = <50 1>, <51 1>; 162 debounce = <15625>; 163 pull-up; 164 }; 165 166 keypad@148 { 167 compatible = "qcom,pm8921-keypad"; 168 reg = <0x148>; 169 interrupt-parent = <&pmicintc>; 170 interrupts = <74 1>, <75 1>; 171 debounce = <15>; 172 scan-delay = <32>; 173 row-hold = <91500>; 174 }; 175 176 rtc@11d { 177 compatible = "qcom,pm8921-rtc"; 178 interrupt-parent = <&pmicintc>; 179 interrupts = <39 1>; 180 reg = <0x11d>; 181 allow-set-time; 182 }; 183 }; 184 }; 185 186 rng@1a500000 { 187 compatible = "qcom,prng"; 188 reg = <0x1a500000 0x200>; 189 clocks = <&gcc PRNG_CLK>; 190 clock-names = "core"; 191 }; 192 193 /* Temporary fixed regulator */ 194 vsdcc_fixed: vsdcc-regulator { 195 compatible = "regulator-fixed"; 196 regulator-name = "SDCC Power"; 197 regulator-min-microvolt = <2700000>; 198 regulator-max-microvolt = <2700000>; 199 regulator-always-on; 200 }; 201 202 amba { 203 compatible = "arm,amba-bus"; 204 #address-cells = <1>; 205 #size-cells = <1>; 206 ranges; 207 sdcc1: sdcc@12400000 { 208 status = "disabled"; 209 compatible = "arm,pl18x", "arm,primecell"; 210 arm,primecell-periphid = <0x00051180>; 211 reg = <0x12400000 0x8000>; 212 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 213 interrupt-names = "cmd_irq"; 214 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 215 clock-names = "mclk", "apb_pclk"; 216 bus-width = <8>; 217 max-frequency = <96000000>; 218 non-removable; 219 cap-sd-highspeed; 220 cap-mmc-highspeed; 221 vmmc-supply = <&vsdcc_fixed>; 222 }; 223 224 sdcc3: sdcc@12180000 { 225 compatible = "arm,pl18x", "arm,primecell"; 226 arm,primecell-periphid = <0x00051180>; 227 status = "disabled"; 228 reg = <0x12180000 0x8000>; 229 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 230 interrupt-names = "cmd_irq"; 231 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 232 clock-names = "mclk", "apb_pclk"; 233 bus-width = <4>; 234 cap-sd-highspeed; 235 cap-mmc-highspeed; 236 max-frequency = <192000000>; 237 no-1-8-v; 238 vmmc-supply = <&vsdcc_fixed>; 239 }; 240 }; 241 }; 242}; 243