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Searched refs:BIT1 (Results 1 – 25 of 52) sorted by relevance

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/drivers/net/wireless/rtlwifi/rtl8821ae/
Dpwrseq.h51 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
79 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
88 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
91 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
192 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
195 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
275 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
281 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
310 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
316 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
[all …]
/drivers/staging/rtl8188eu/include/
Dpwrseq.h68 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \
71 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
108 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
111 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \
143 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
156 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
190 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
203 PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
262 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
292 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
[all …]
Drtl8188e_spec.h27 #define BIT1 0x00000002 macro
541 #define CMD_READ_EFUSE_MAP BIT1
552 #define RRSR_2M BIT1
575 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
579 #define BW_OPMODE_5G BIT1
611 #define WOW_WOMEN BIT1 /* WoW function on or off. */
641 #define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */
704 #define StopVI BIT1
731 #define RCR_APM BIT1 /* Accept physical match pkt */
1201 #define SDIO_HIMR_AVAL_MSK BIT1
[all …]
Dodm.h418 ODM_BB_RA_MASK = BIT1,
464 ODM_RF_TX_B = BIT1,
502 ODM_LINK = BIT1,
516 ODM_WM_G = BIT1,
527 ODM_BAND_5G = BIT1,
Drtw_sreset.h34 #define USB_READ_PORT_FAIL BIT1
Dodm_debug.h61 #define ODM_COMP_RA_MASK BIT1
DHal8188EPhyCfg.h92 WIRELESS_MODE_G = BIT1,
/drivers/scsi/
Dtmscsim.h191 #define BIT1 0x00000002 macro
196 #define UNIT_INFO_CHANGED BIT1
202 #define SCSI_SUPPORT BIT1
208 #define SRB_READY BIT1
225 #define ABORTION BIT1
233 #define RESET_DETECT BIT1
245 #define ABORT_DEV BIT1
280 #define SYNC_NEGO_DONE BIT1
335 #define SYNC_NEGO_ BIT1
342 #define GREATER_1G BIT1
[all …]
Ddc395x.h74 #define BIT1 0x00000002 macro
79 #define UNIT_INFO_CHANGED BIT1
85 #define SCSI_SUPPORT BIT1
121 #define RESET_DETECT BIT1
129 #define ABORTION BIT1
141 #define ABORT_DEV BIT1
174 #define SYNC_NEGO_DONE BIT1
630 #define GREATER_1G BIT1
/drivers/staging/vt6655/
D80211hdr.h38 #define BIT1 0x00000002 macro
158 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n) >> 8) & (BIT0 | BIT1))
171 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
172 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
176 #define WLAN_GET_CAP_INFO_IBSS(n) ((((n) >> 8) & BIT1) >> 1)
191 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
204 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
205 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
209 #define WLAN_GET_CAP_INFO_IBSS(n) (((n) & BIT1) >> 1)
254 #define WLAN_GET_ERP_USE_PROTECTION(n) (((n) & BIT1) >> 1)
Dhostap.h35 #define WLAN_RATE_2M BIT1
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_hw.h144 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \
162 #define RCR_APM BIT1
216 #define SCR_RxUseDK BIT1
241 #define IMR_VODOK BIT1
246 #define TPPoll_BEQ BIT1
286 #define AcmHw_BeqEn BIT1
294 #define AcmFw_ViqStatus BIT1
347 #define BW_OPMODE_5G BIT1
376 #define RRSR_2M BIT1
/drivers/video/fbdev/via/
Ddvi.c59 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
339 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
349 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
352 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
359 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
360 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0()
377 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
384 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
391 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
Dlcd.c359 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
534 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
577 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
622 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
666 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
668 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
688 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
/drivers/staging/rtl8192u/
Dr8192U_hw.h159 #define RCR_APM BIT1 // Accept physical match packet
184 #define SCR_RxUseDK BIT1 //Force Rx Use Default Key
230 #define AcmHw_BeqEn BIT1
285 #define BW_OPMODE_5G BIT1
308 #define RRSR_2M BIT1
/drivers/staging/rtl8192e/
Drtl819x_Qos.h25 #define BIT1 0x00000002 macro
239 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
240 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h5 #define BIT1 0x00000002 macro
381 #define GET_VI_UAPSD(_apsd) ((_apsd) & BIT1)
382 #define SET_VI_UAPSD(_apsd) ((_apsd) |= BIT1)
/drivers/net/wireless/rtlwifi/btcoexist/
Dhalbt_precomp.h49 #define BIT1 0x00000002 macro
Dhalbtcoutsrc.h102 #define ALGO_WIFI_RSSI_STATE BIT1
114 #define WIFI_AP_CONNECTED BIT1
Dhalbtc8821a2ant.h36 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
Dhalbtc8723b2ant.h39 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
Dhalbtc8723b1ant.h36 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
/drivers/staging/rtl8188eu/core/
Drtw_efuse.c410 if (!(word_en&BIT1)) { in Efuse_WordEnableDataWrite()
418 badworden &= (~BIT1); in Efuse_WordEnableDataWrite()
747 if (((pTargetPkt->word_en & BIT1) == 0) && in wordEnMatched()
748 ((pCurPkt->word_en & BIT1) == 0)) in wordEnMatched()
749 match_word_en &= ~BIT1; /* enable word 1 */ in wordEnMatched()
/drivers/tty/
Dsynclink_gt.c221 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1)
382 #define MASK_PARITY BIT1
1882 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1883 if (status & BIT1) in rx_async()
1890 if (status & BIT1) in rx_async()
2068 if (status & BIT1) { in dcd_change()
3907 wr_reg32(info, RDCSR, BIT1); in rdma_reset()
3920 wr_reg32(info, TDCSR, BIT1); in tdma_reset()
3984 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop()
4009 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start()
[all …]
/drivers/staging/rtl8188eu/hal/
Drtl8188e_hal_init.c210 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT1); in hal_notch_filter_8188e()
213 usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); in hal_notch_filter_8188e()
532 …padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true… in Hal_ReadPowerSavingMode88E()

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