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Searched refs:DIV_ROUND_UP (Results 1 – 25 of 422) sorted by relevance

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/drivers/media/i2c/
Dsmiapp-pll.c148 DIV_ROUND_UP(limits->max_pll_multiplier, mul)); in __smiapp_pll_calculate()
153 more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz, in __smiapp_pll_calculate()
160 DIV_ROUND_UP(limits->min_pll_multiplier, mul)); in __smiapp_pll_calculate()
231 min_vt_div = DIV_ROUND_UP(pll->op_pix_clk_div * pll->op_sys_clk_div in __smiapp_pll_calculate()
239 DIV_ROUND_UP(pll->pll_op_clk_freq_hz, in __smiapp_pll_calculate()
251 DIV_ROUND_UP(pll->pll_op_clk_freq_hz, in __smiapp_pll_calculate()
263 DIV_ROUND_UP(min_vt_div, in __smiapp_pll_calculate()
276 DIV_ROUND_UP(max_vt_div, in __smiapp_pll_calculate()
280 DIV_ROUND_UP(pll->pll_op_clk_freq_hz, in __smiapp_pll_calculate()
294 uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div); in __smiapp_pll_calculate()
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Daptina-pll.c69 mf_min = DIV_ROUND_UP(limits->m_min, pll->m); in aptina_pll_calculate()
76 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); in aptina_pll_calculate()
141 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, in aptina_pll_calculate()
151 mf_low = roundup(max(mf_min, DIV_ROUND_UP(pll->ext_clock * p1, in aptina_pll_calculate()
/drivers/gpu/drm/i915/
Dintel_dsi_panel_vbt.c323 burst_mode_ratio = DIV_ROUND_UP( in generic_init()
327 pclk = DIV_ROUND_UP(pclk * burst_mode_ratio, 100); in generic_init()
386 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in generic_init()
397 prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num * 2); in generic_init()
400 exit_zero_cnt = DIV_ROUND_UP( in generic_init()
416 clk_zero_cnt = DIV_ROUND_UP( in generic_init()
422 trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num); in generic_init()
456 tlpx_ui = DIV_ROUND_UP(tlpx_ns * ui_den, ui_num); in generic_init()
461 lp_to_hs_switch = DIV_ROUND_UP(4 * tlpx_ui + prepare_cnt * 2 + in generic_init()
464 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in generic_init()
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Dintel_dsi_pll.c92 hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); in dsi_rr_formula()
93 hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); in dsi_rr_formula()
94 hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); in dsi_rr_formula()
95 hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); in dsi_rr_formula()
/drivers/ssb/
Ddriver_extif.c94 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; in ssb_extif_timing_init()
95 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; in ssb_extif_timing_init()
96 tmp |= DIV_ROUND_UP(120, ns); in ssb_extif_timing_init()
100 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; in ssb_extif_timing_init()
101 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; in ssb_extif_timing_init()
102 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; in ssb_extif_timing_init()
103 tmp |= DIV_ROUND_UP(120, ns); in ssb_extif_timing_init()
Ddriver_chipcommon.c443 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ in ssb_chipco_timing_init()
444 tmp |= DIV_ROUND_UP(40, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 40ns */ in ssb_chipco_timing_init()
445 tmp |= DIV_ROUND_UP(240, ns); /* Waitcount-0 = 240ns */ in ssb_chipco_timing_init()
449 tmp = DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_3_SHIFT; /* Waitcount-3 = 10nS */ in ssb_chipco_timing_init()
450 tmp |= DIV_ROUND_UP(10, ns) << SSB_FLASH_WCNT_1_SHIFT; /* Waitcount-1 = 10nS */ in ssb_chipco_timing_init()
451 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120nS */ in ssb_chipco_timing_init()
462 tmp = DIV_ROUND_UP(10, ns) << SSB_PROG_WCNT_3_SHIFT; /* Waitcount-3 = 10ns */ in ssb_chipco_timing_init()
463 tmp |= DIV_ROUND_UP(20, ns) << SSB_PROG_WCNT_2_SHIFT; /* Waitcount-2 = 20ns */ in ssb_chipco_timing_init()
464 tmp |= DIV_ROUND_UP(100, ns) << SSB_PROG_WCNT_1_SHIFT; /* Waitcount-1 = 100ns */ in ssb_chipco_timing_init()
465 tmp |= DIV_ROUND_UP(120, ns); /* Waitcount-0 = 120ns */ in ssb_chipco_timing_init()
/drivers/ide/
Dpalm_bk3710.c85 t0 = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].cycletime, in palm_bk3710_setudmamode()
87 tenv = DIV_ROUND_UP(20, ideclk_period) - 1; in palm_bk3710_setudmamode()
88 trp = DIV_ROUND_UP(palm_bk3710_udmatimings[mode].rptime, in palm_bk3710_setudmamode()
125 t0 = DIV_ROUND_UP(cycletime, ideclk_period); in palm_bk3710_setdmamode()
126 td = DIV_ROUND_UP(t->active, ideclk_period); in palm_bk3710_setdmamode()
154 t0 = DIV_ROUND_UP(cycletime, ideclk_period); in palm_bk3710_setpiomode()
155 t2 = DIV_ROUND_UP(t->active, ideclk_period); in palm_bk3710_setpiomode()
176 t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); in palm_bk3710_setpiomode()
177 t2 = DIV_ROUND_UP(t->act8b, ideclk_period); in palm_bk3710_setpiomode()
Dtx4938ide.c35 wt = DIV_ROUND_UP(t->act8b, cycle) - 2; in tx4938ide_tune_ebusc()
37 wt = max_t(int, wt, DIV_ROUND_UP(35, cycle)); in tx4938ide_tune_ebusc()
43 shwt = DIV_ROUND_UP(t->setup, cycle); in tx4938ide_tune_ebusc()
Dcmd640.c536 cycle_count = DIV_ROUND_UP(cycle_time, clock_time); in cmd640_set_mode()
538 setup_count = DIV_ROUND_UP(setup_time, clock_time); in cmd640_set_mode()
540 active_count = DIV_ROUND_UP(active_time, clock_time); in cmd640_set_mode()
544 recovery_count = DIV_ROUND_UP(recovery_time, clock_time); in cmd640_set_mode()
/drivers/irqchip/
Dirq-gic.c60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
461 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) in gic_dist_save()
465 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) in gic_dist_save()
469 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) in gic_dist_save()
498 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) in gic_dist_restore()
502 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) in gic_dist_restore()
506 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) in gic_dist_restore()
510 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) in gic_dist_restore()
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/drivers/memory/
Demif.c439 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; in get_sdram_tim_1_shdw()
443 val = DIV_ROUND_UP(timings->tFAW, t_ck*4); in get_sdram_tim_1_shdw()
445 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck)); in get_sdram_tim_1_shdw()
448 val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1; in get_sdram_tim_1_shdw()
451 val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck)); in get_sdram_tim_1_shdw()
454 val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1; in get_sdram_tim_1_shdw()
457 val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1; in get_sdram_tim_1_shdw()
460 val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1; in get_sdram_tim_1_shdw()
472 val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1; in get_sdram_tim_1_shdw_derated()
480 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1; in get_sdram_tim_1_shdw_derated()
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/drivers/media/platform/s5p-mfc/
Dregs-mfc-v8.h112 ((DIV_ROUND_UP((mbw * 16), 64) * DIV_ROUND_UP((mbh * 16), 64) * 256) \
113 + (DIV_ROUND_UP((mbw) * (mbh), 32) * 16))
Ds5p_mfc_opr_v6.h23 #define MB_WIDTH(x_size) DIV_ROUND_UP(x_size, 16)
24 #define MB_HEIGHT(y_size) DIV_ROUND_UP(y_size, 16)
/drivers/clk/
Dclk-divider.c129 return DIV_ROUND_UP(parent_rate, div); in clk_divider_recalc_rate()
191 int div = DIV_ROUND_UP(parent_rate, rate); in _div_round_up()
217 up_rate = DIV_ROUND_UP(parent_rate, up); in _div_round_closest()
218 down_rate = DIV_ROUND_UP(parent_rate, down); in _div_round_closest()
302 now = DIV_ROUND_UP(parent_rate, i); in clk_divider_bestdiv()
324 return DIV_ROUND_UP(*prate, div); in clk_divider_round_rate()
335 div = DIV_ROUND_UP(parent_rate, rate); in clk_divider_set_rate()
Dclk-clps711x.c68 f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2); in _clps711x_clk_init()
82 f_bus = DIV_ROUND_UP(f_cpu, 2); in _clps711x_clk_init()
/drivers/gpu/drm/vmwgfx/
Dsvga3d_surfacedefs.h39 #define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) macro
756 block_size->width = DIV_ROUND_UP(pixel_size->width, in svga3dsurface_get_size_in_blocks()
758 block_size->height = DIV_ROUND_UP(pixel_size->height, in svga3dsurface_get_size_in_blocks()
760 block_size->depth = DIV_ROUND_UP(pixel_size->depth, in svga3dsurface_get_size_in_blocks()
872 const u32 rowstride = DIV_ROUND_UP(width, bw) * desc->bytes_per_block; in svga3dsurface_get_pixel_offset()
873 const u32 imgstride = DIV_ROUND_UP(height, bh) * rowstride; in svga3dsurface_get_pixel_offset()
/drivers/clk/ti/
Ddivider.c115 return DIV_ROUND_UP(parent_rate, div); in ti_clk_divider_recalc_rate()
159 bestdiv = DIV_ROUND_UP(parent_rate, rate); in ti_clk_divider_bestdiv()
185 now = DIV_ROUND_UP(parent_rate, i); in ti_clk_divider_bestdiv()
208 return DIV_ROUND_UP(*prate, div); in ti_clk_divider_round_rate()
224 div = DIV_ROUND_UP(parent_rate, rate); in ti_clk_divider_set_rate()
/drivers/spi/
Dspi-orion.c127 spr = DIV_ROUND_UP(spr, speed); in orion_spi_baudrate_set()
151 rate = DIV_ROUND_UP(tclk_hz, speed); in orion_spi_baudrate_set()
489 DIV_ROUND_UP(tclk_hz, devdata->min_divisor)); in orion_spi_probe()
492 DIV_ROUND_UP(tclk_hz, devdata->min_divisor); in orion_spi_probe()
493 master->min_speed_hz = DIV_ROUND_UP(tclk_hz, devdata->max_divisor); in orion_spi_probe()
/drivers/firewire/
Dcore-card.c248 delayed ? DIV_ROUND_UP(HZ, 100) : 0)) in fw_schedule_bus_reset()
343 card->reset_jiffies + DIV_ROUND_UP(HZ, 8)); in bm_work()
410 fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8)); in bm_work()
434 fw_schedule_bm_work(card, DIV_ROUND_UP(HZ, 8)); in bm_work()
542 DIV_ROUND_UP(DEFAULT_SPLIT_TIMEOUT * HZ, 8000); in fw_card_initialize()
/drivers/gpu/host1x/hw/
Dintr_hw.c50 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) { in syncpt_thresh_isr()
67 for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) { in _host1x_intr_disable_all_syncpt_intrs()
/drivers/net/wireless/ti/wlcore/
Dscan.c180 min_dwell_time_active = DIV_ROUND_UP(min_dwell_time_active, 1000); in wlcore_scan_get_channels()
181 max_dwell_time_active = DIV_ROUND_UP(max_dwell_time_active, 1000); in wlcore_scan_get_channels()
182 dwell_time_passive = DIV_ROUND_UP(dwell_time_passive, 1000); in wlcore_scan_get_channels()
183 dwell_time_dfs = DIV_ROUND_UP(dwell_time_dfs, 1000); in wlcore_scan_get_channels()
/drivers/base/regmap/
Dregcache-lzo.c112 DIV_ROUND_UP(map->cache_size_raw, in regcache_lzo_get_blkindex()
120 (DIV_ROUND_UP(map->cache_size_raw, in regcache_lzo_get_blkpos()
127 return DIV_ROUND_UP(map->cache_size_raw, in regcache_lzo_get_blksize()
/drivers/hwmon/
Dpwm-fan.c56 duty = DIV_ROUND_UP(pwm * (ctx->pwm->period - 1), MAX_PWM); in set_pwm()
170 duty = DIV_ROUND_UP(ctx->pwm_value * (ctx->pwm->period - 1), MAX_PWM); in pwm_fan_resume()
/drivers/i2c/busses/
Di2c-mxs.c702 divider = DIV_ROUND_UP(clk, speed); in mxs_i2c_derive_timing()
744 leadin = DIV_ROUND_UP(600 * (clk / 1000000), 1000); in mxs_i2c_derive_timing()
745 bus_free = DIV_ROUND_UP(1300 * (clk / 1000000), 1000); in mxs_i2c_derive_timing()
750 leadin = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); in mxs_i2c_derive_timing()
751 bus_free = DIV_ROUND_UP(4700 * (clk / 1000000), 1000); in mxs_i2c_derive_timing()
/drivers/infiniband/hw/cxgb4/
Dqp.c277 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16)); in create_qp()
496 *len16 = DIV_ROUND_UP(size, 16); in build_rdma_send()
539 *len16 = DIV_ROUND_UP(size, 16); in build_rdma_write()
569 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16); in build_rdma_read()
583 *len16 = DIV_ROUND_UP(sizeof wqe->recv + in build_rdma_recv()
631 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16); in build_fastreg()
654 *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp) in build_fastreg()
665 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16); in build_inv_stag()
840 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); in c4iw_post_send()
912 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE); in c4iw_post_receive()
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