1 /*
2 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Interrupt architecture for the GIC:
9 *
10 * o There is one Interrupt Distributor, which receives interrupts
11 * from system devices and sends them to the Interrupt Controllers.
12 *
13 * o There is one CPU Interface per CPU, which sends interrupts sent
14 * by the Distributor, and interrupts generated locally, to the
15 * associated CPU. The base address of the CPU interface is usually
16 * aliased so that the same address points to different chips depending
17 * on the CPU it is accessed from.
18 *
19 * Note that IRQs 0-31 are special - they are local to each CPU.
20 * As such, the enable set/clear, pending set/clear and active bit
21 * registers are banked per-cpu for these sources.
22 */
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
32 #include <linux/io.h>
33 #include <linux/of.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/irqdomain.h>
37 #include <linux/interrupt.h>
38 #include <linux/percpu.h>
39 #include <linux/slab.h>
40 #include <linux/irqchip/chained_irq.h>
41 #include <linux/irqchip/arm-gic.h>
42
43 #include <asm/cputype.h>
44 #include <asm/irq.h>
45 #include <asm/exception.h>
46 #include <asm/smp_plat.h>
47
48 #include "irq-gic-common.h"
49 #include "irqchip.h"
50
51 union gic_base {
52 void __iomem *common_base;
53 void __percpu * __iomem *percpu_base;
54 };
55
56 struct gic_chip_data {
57 union gic_base dist_base;
58 union gic_base cpu_base;
59 #ifdef CONFIG_CPU_PM
60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
63 u32 __percpu *saved_ppi_enable;
64 u32 __percpu *saved_ppi_conf;
65 #endif
66 struct irq_domain *domain;
67 unsigned int gic_irqs;
68 #ifdef CONFIG_GIC_NON_BANKED
69 void __iomem *(*get_base)(union gic_base *);
70 #endif
71 };
72
73 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
74
75 /*
76 * The GIC mapping of CPU interfaces does not necessarily match
77 * the logical CPU numbering. Let's use a mapping as returned
78 * by the GIC itself.
79 */
80 #define NR_GIC_CPU_IF 8
81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
82
83 /*
84 * Supported arch specific GIC irq extension.
85 * Default make them NULL.
86 */
87 struct irq_chip gic_arch_extn = {
88 .irq_eoi = NULL,
89 .irq_mask = NULL,
90 .irq_unmask = NULL,
91 .irq_retrigger = NULL,
92 .irq_set_type = NULL,
93 .irq_set_wake = NULL,
94 };
95
96 #ifndef MAX_GIC_NR
97 #define MAX_GIC_NR 1
98 #endif
99
100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
101
102 #ifdef CONFIG_GIC_NON_BANKED
gic_get_percpu_base(union gic_base * base)103 static void __iomem *gic_get_percpu_base(union gic_base *base)
104 {
105 return raw_cpu_read(*base->percpu_base);
106 }
107
gic_get_common_base(union gic_base * base)108 static void __iomem *gic_get_common_base(union gic_base *base)
109 {
110 return base->common_base;
111 }
112
gic_data_dist_base(struct gic_chip_data * data)113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
114 {
115 return data->get_base(&data->dist_base);
116 }
117
gic_data_cpu_base(struct gic_chip_data * data)118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
119 {
120 return data->get_base(&data->cpu_base);
121 }
122
gic_set_base_accessor(struct gic_chip_data * data,void __iomem * (* f)(union gic_base *))123 static inline void gic_set_base_accessor(struct gic_chip_data *data,
124 void __iomem *(*f)(union gic_base *))
125 {
126 data->get_base = f;
127 }
128 #else
129 #define gic_data_dist_base(d) ((d)->dist_base.common_base)
130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base)
131 #define gic_set_base_accessor(d, f)
132 #endif
133
gic_dist_base(struct irq_data * d)134 static inline void __iomem *gic_dist_base(struct irq_data *d)
135 {
136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
137 return gic_data_dist_base(gic_data);
138 }
139
gic_cpu_base(struct irq_data * d)140 static inline void __iomem *gic_cpu_base(struct irq_data *d)
141 {
142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
143 return gic_data_cpu_base(gic_data);
144 }
145
gic_irq(struct irq_data * d)146 static inline unsigned int gic_irq(struct irq_data *d)
147 {
148 return d->hwirq;
149 }
150
151 /*
152 * Routines to acknowledge, disable and enable interrupts
153 */
gic_mask_irq(struct irq_data * d)154 static void gic_mask_irq(struct irq_data *d)
155 {
156 u32 mask = 1 << (gic_irq(d) % 32);
157
158 raw_spin_lock(&irq_controller_lock);
159 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
160 if (gic_arch_extn.irq_mask)
161 gic_arch_extn.irq_mask(d);
162 raw_spin_unlock(&irq_controller_lock);
163 }
164
gic_unmask_irq(struct irq_data * d)165 static void gic_unmask_irq(struct irq_data *d)
166 {
167 u32 mask = 1 << (gic_irq(d) % 32);
168
169 raw_spin_lock(&irq_controller_lock);
170 if (gic_arch_extn.irq_unmask)
171 gic_arch_extn.irq_unmask(d);
172 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
173 raw_spin_unlock(&irq_controller_lock);
174 }
175
gic_eoi_irq(struct irq_data * d)176 static void gic_eoi_irq(struct irq_data *d)
177 {
178 if (gic_arch_extn.irq_eoi) {
179 raw_spin_lock(&irq_controller_lock);
180 gic_arch_extn.irq_eoi(d);
181 raw_spin_unlock(&irq_controller_lock);
182 }
183
184 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
185 }
186
gic_set_type(struct irq_data * d,unsigned int type)187 static int gic_set_type(struct irq_data *d, unsigned int type)
188 {
189 void __iomem *base = gic_dist_base(d);
190 unsigned int gicirq = gic_irq(d);
191
192 /* Interrupt configuration for SGIs can't be changed */
193 if (gicirq < 16)
194 return -EINVAL;
195
196 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
197 return -EINVAL;
198
199 raw_spin_lock(&irq_controller_lock);
200
201 if (gic_arch_extn.irq_set_type)
202 gic_arch_extn.irq_set_type(d, type);
203
204 gic_configure_irq(gicirq, type, base, NULL);
205
206 raw_spin_unlock(&irq_controller_lock);
207
208 return 0;
209 }
210
gic_retrigger(struct irq_data * d)211 static int gic_retrigger(struct irq_data *d)
212 {
213 if (gic_arch_extn.irq_retrigger)
214 return gic_arch_extn.irq_retrigger(d);
215
216 /* the genirq layer expects 0 if we can't retrigger in hardware */
217 return 0;
218 }
219
220 #ifdef CONFIG_SMP
gic_set_affinity(struct irq_data * d,const struct cpumask * mask_val,bool force)221 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
222 bool force)
223 {
224 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
225 unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
226 u32 val, mask, bit;
227
228 if (!force)
229 cpu = cpumask_any_and(mask_val, cpu_online_mask);
230 else
231 cpu = cpumask_first(mask_val);
232
233 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
234 return -EINVAL;
235
236 raw_spin_lock(&irq_controller_lock);
237 mask = 0xff << shift;
238 bit = gic_cpu_map[cpu] << shift;
239 val = readl_relaxed(reg) & ~mask;
240 writel_relaxed(val | bit, reg);
241 raw_spin_unlock(&irq_controller_lock);
242
243 return IRQ_SET_MASK_OK;
244 }
245 #endif
246
247 #ifdef CONFIG_PM
gic_set_wake(struct irq_data * d,unsigned int on)248 static int gic_set_wake(struct irq_data *d, unsigned int on)
249 {
250 int ret = -ENXIO;
251
252 if (gic_arch_extn.irq_set_wake)
253 ret = gic_arch_extn.irq_set_wake(d, on);
254
255 return ret;
256 }
257
258 #else
259 #define gic_set_wake NULL
260 #endif
261
gic_handle_irq(struct pt_regs * regs)262 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
263 {
264 u32 irqstat, irqnr;
265 struct gic_chip_data *gic = &gic_data[0];
266 void __iomem *cpu_base = gic_data_cpu_base(gic);
267
268 do {
269 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
270 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
271
272 if (likely(irqnr > 15 && irqnr < 1021)) {
273 handle_domain_irq(gic->domain, irqnr, regs);
274 continue;
275 }
276 if (irqnr < 16) {
277 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
278 #ifdef CONFIG_SMP
279 /*
280 * Ensure any shared data written by the CPU sending
281 * the IPI is read after we've read the ACK register
282 * on the GIC.
283 *
284 * Pairs with the write barrier in gic_raise_softirq
285 */
286 smp_rmb();
287 handle_IPI(irqnr, regs);
288 #endif
289 continue;
290 }
291 break;
292 } while (1);
293 }
294
gic_handle_cascade_irq(unsigned int irq,struct irq_desc * desc)295 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
296 {
297 struct gic_chip_data *chip_data = irq_get_handler_data(irq);
298 struct irq_chip *chip = irq_get_chip(irq);
299 unsigned int cascade_irq, gic_irq;
300 unsigned long status;
301
302 chained_irq_enter(chip, desc);
303
304 raw_spin_lock(&irq_controller_lock);
305 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
306 raw_spin_unlock(&irq_controller_lock);
307
308 gic_irq = (status & GICC_IAR_INT_ID_MASK);
309 if (gic_irq == GICC_INT_SPURIOUS)
310 goto out;
311
312 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
313 if (unlikely(gic_irq < 32 || gic_irq > 1020))
314 handle_bad_irq(cascade_irq, desc);
315 else
316 generic_handle_irq(cascade_irq);
317
318 out:
319 chained_irq_exit(chip, desc);
320 }
321
322 static struct irq_chip gic_chip = {
323 .name = "GIC",
324 .irq_mask = gic_mask_irq,
325 .irq_unmask = gic_unmask_irq,
326 .irq_eoi = gic_eoi_irq,
327 .irq_set_type = gic_set_type,
328 .irq_retrigger = gic_retrigger,
329 #ifdef CONFIG_SMP
330 .irq_set_affinity = gic_set_affinity,
331 #endif
332 .irq_set_wake = gic_set_wake,
333 };
334
gic_cascade_irq(unsigned int gic_nr,unsigned int irq)335 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
336 {
337 if (gic_nr >= MAX_GIC_NR)
338 BUG();
339 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
340 BUG();
341 irq_set_chained_handler(irq, gic_handle_cascade_irq);
342 }
343
gic_get_cpumask(struct gic_chip_data * gic)344 static u8 gic_get_cpumask(struct gic_chip_data *gic)
345 {
346 void __iomem *base = gic_data_dist_base(gic);
347 u32 mask, i;
348
349 for (i = mask = 0; i < 32; i += 4) {
350 mask = readl_relaxed(base + GIC_DIST_TARGET + i);
351 mask |= mask >> 16;
352 mask |= mask >> 8;
353 if (mask)
354 break;
355 }
356
357 if (!mask)
358 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
359
360 return mask;
361 }
362
gic_cpu_if_up(void)363 static void gic_cpu_if_up(void)
364 {
365 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
366 u32 bypass = 0;
367
368 /*
369 * Preserve bypass disable bits to be written back later
370 */
371 bypass = readl(cpu_base + GIC_CPU_CTRL);
372 bypass &= GICC_DIS_BYPASS_MASK;
373
374 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
375 }
376
377
gic_dist_init(struct gic_chip_data * gic)378 static void __init gic_dist_init(struct gic_chip_data *gic)
379 {
380 unsigned int i;
381 u32 cpumask;
382 unsigned int gic_irqs = gic->gic_irqs;
383 void __iomem *base = gic_data_dist_base(gic);
384
385 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
386
387 /*
388 * Set all global interrupts to this CPU only.
389 */
390 cpumask = gic_get_cpumask(gic);
391 cpumask |= cpumask << 8;
392 cpumask |= cpumask << 16;
393 for (i = 32; i < gic_irqs; i += 4)
394 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
395
396 gic_dist_config(base, gic_irqs, NULL);
397
398 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
399 }
400
gic_cpu_init(struct gic_chip_data * gic)401 static void gic_cpu_init(struct gic_chip_data *gic)
402 {
403 void __iomem *dist_base = gic_data_dist_base(gic);
404 void __iomem *base = gic_data_cpu_base(gic);
405 unsigned int cpu_mask, cpu = smp_processor_id();
406 int i;
407
408 /*
409 * Get what the GIC says our CPU mask is.
410 */
411 BUG_ON(cpu >= NR_GIC_CPU_IF);
412 cpu_mask = gic_get_cpumask(gic);
413 gic_cpu_map[cpu] = cpu_mask;
414
415 /*
416 * Clear our mask from the other map entries in case they're
417 * still undefined.
418 */
419 for (i = 0; i < NR_GIC_CPU_IF; i++)
420 if (i != cpu)
421 gic_cpu_map[i] &= ~cpu_mask;
422
423 gic_cpu_config(dist_base, NULL);
424
425 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
426 gic_cpu_if_up();
427 }
428
gic_cpu_if_down(void)429 void gic_cpu_if_down(void)
430 {
431 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
432 u32 val = 0;
433
434 val = readl(cpu_base + GIC_CPU_CTRL);
435 val &= ~GICC_ENABLE;
436 writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
437 }
438
439 #ifdef CONFIG_CPU_PM
440 /*
441 * Saves the GIC distributor registers during suspend or idle. Must be called
442 * with interrupts disabled but before powering down the GIC. After calling
443 * this function, no interrupts will be delivered by the GIC, and another
444 * platform-specific wakeup source must be enabled.
445 */
gic_dist_save(unsigned int gic_nr)446 static void gic_dist_save(unsigned int gic_nr)
447 {
448 unsigned int gic_irqs;
449 void __iomem *dist_base;
450 int i;
451
452 if (gic_nr >= MAX_GIC_NR)
453 BUG();
454
455 gic_irqs = gic_data[gic_nr].gic_irqs;
456 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
457
458 if (!dist_base)
459 return;
460
461 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
462 gic_data[gic_nr].saved_spi_conf[i] =
463 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
464
465 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
466 gic_data[gic_nr].saved_spi_target[i] =
467 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
468
469 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
470 gic_data[gic_nr].saved_spi_enable[i] =
471 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
472 }
473
474 /*
475 * Restores the GIC distributor registers during resume or when coming out of
476 * idle. Must be called before enabling interrupts. If a level interrupt
477 * that occured while the GIC was suspended is still present, it will be
478 * handled normally, but any edge interrupts that occured will not be seen by
479 * the GIC and need to be handled by the platform-specific wakeup source.
480 */
gic_dist_restore(unsigned int gic_nr)481 static void gic_dist_restore(unsigned int gic_nr)
482 {
483 unsigned int gic_irqs;
484 unsigned int i;
485 void __iomem *dist_base;
486
487 if (gic_nr >= MAX_GIC_NR)
488 BUG();
489
490 gic_irqs = gic_data[gic_nr].gic_irqs;
491 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
492
493 if (!dist_base)
494 return;
495
496 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
497
498 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
499 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
500 dist_base + GIC_DIST_CONFIG + i * 4);
501
502 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
503 writel_relaxed(GICD_INT_DEF_PRI_X4,
504 dist_base + GIC_DIST_PRI + i * 4);
505
506 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
507 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
508 dist_base + GIC_DIST_TARGET + i * 4);
509
510 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
511 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
512 dist_base + GIC_DIST_ENABLE_SET + i * 4);
513
514 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
515 }
516
gic_cpu_save(unsigned int gic_nr)517 static void gic_cpu_save(unsigned int gic_nr)
518 {
519 int i;
520 u32 *ptr;
521 void __iomem *dist_base;
522 void __iomem *cpu_base;
523
524 if (gic_nr >= MAX_GIC_NR)
525 BUG();
526
527 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
528 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
529
530 if (!dist_base || !cpu_base)
531 return;
532
533 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
534 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
535 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
536
537 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
538 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
539 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
540
541 }
542
gic_cpu_restore(unsigned int gic_nr)543 static void gic_cpu_restore(unsigned int gic_nr)
544 {
545 int i;
546 u32 *ptr;
547 void __iomem *dist_base;
548 void __iomem *cpu_base;
549
550 if (gic_nr >= MAX_GIC_NR)
551 BUG();
552
553 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
554 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
555
556 if (!dist_base || !cpu_base)
557 return;
558
559 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
560 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
561 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
562
563 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
564 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
565 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
566
567 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
568 writel_relaxed(GICD_INT_DEF_PRI_X4,
569 dist_base + GIC_DIST_PRI + i * 4);
570
571 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
572 gic_cpu_if_up();
573 }
574
gic_notifier(struct notifier_block * self,unsigned long cmd,void * v)575 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
576 {
577 int i;
578
579 for (i = 0; i < MAX_GIC_NR; i++) {
580 #ifdef CONFIG_GIC_NON_BANKED
581 /* Skip over unused GICs */
582 if (!gic_data[i].get_base)
583 continue;
584 #endif
585 switch (cmd) {
586 case CPU_PM_ENTER:
587 gic_cpu_save(i);
588 break;
589 case CPU_PM_ENTER_FAILED:
590 case CPU_PM_EXIT:
591 gic_cpu_restore(i);
592 break;
593 case CPU_CLUSTER_PM_ENTER:
594 gic_dist_save(i);
595 break;
596 case CPU_CLUSTER_PM_ENTER_FAILED:
597 case CPU_CLUSTER_PM_EXIT:
598 gic_dist_restore(i);
599 break;
600 }
601 }
602
603 return NOTIFY_OK;
604 }
605
606 static struct notifier_block gic_notifier_block = {
607 .notifier_call = gic_notifier,
608 };
609
gic_pm_init(struct gic_chip_data * gic)610 static void __init gic_pm_init(struct gic_chip_data *gic)
611 {
612 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
613 sizeof(u32));
614 BUG_ON(!gic->saved_ppi_enable);
615
616 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
617 sizeof(u32));
618 BUG_ON(!gic->saved_ppi_conf);
619
620 if (gic == &gic_data[0])
621 cpu_pm_register_notifier(&gic_notifier_block);
622 }
623 #else
gic_pm_init(struct gic_chip_data * gic)624 static void __init gic_pm_init(struct gic_chip_data *gic)
625 {
626 }
627 #endif
628
629 #ifdef CONFIG_SMP
gic_raise_softirq(const struct cpumask * mask,unsigned int irq)630 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
631 {
632 int cpu;
633 unsigned long flags, map = 0;
634
635 raw_spin_lock_irqsave(&irq_controller_lock, flags);
636
637 /* Convert our logical CPU mask into a physical one. */
638 for_each_cpu(cpu, mask)
639 map |= gic_cpu_map[cpu];
640
641 /*
642 * Ensure that stores to Normal memory are visible to the
643 * other CPUs before they observe us issuing the IPI.
644 */
645 dmb(ishst);
646
647 /* this always happens on GIC0 */
648 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
649
650 raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
651 }
652 #endif
653
654 #ifdef CONFIG_BL_SWITCHER
655 /*
656 * gic_send_sgi - send a SGI directly to given CPU interface number
657 *
658 * cpu_id: the ID for the destination CPU interface
659 * irq: the IPI number to send a SGI for
660 */
gic_send_sgi(unsigned int cpu_id,unsigned int irq)661 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
662 {
663 BUG_ON(cpu_id >= NR_GIC_CPU_IF);
664 cpu_id = 1 << cpu_id;
665 /* this always happens on GIC0 */
666 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
667 }
668
669 /*
670 * gic_get_cpu_id - get the CPU interface ID for the specified CPU
671 *
672 * @cpu: the logical CPU number to get the GIC ID for.
673 *
674 * Return the CPU interface ID for the given logical CPU number,
675 * or -1 if the CPU number is too large or the interface ID is
676 * unknown (more than one bit set).
677 */
gic_get_cpu_id(unsigned int cpu)678 int gic_get_cpu_id(unsigned int cpu)
679 {
680 unsigned int cpu_bit;
681
682 if (cpu >= NR_GIC_CPU_IF)
683 return -1;
684 cpu_bit = gic_cpu_map[cpu];
685 if (cpu_bit & (cpu_bit - 1))
686 return -1;
687 return __ffs(cpu_bit);
688 }
689
690 /*
691 * gic_migrate_target - migrate IRQs to another CPU interface
692 *
693 * @new_cpu_id: the CPU target ID to migrate IRQs to
694 *
695 * Migrate all peripheral interrupts with a target matching the current CPU
696 * to the interface corresponding to @new_cpu_id. The CPU interface mapping
697 * is also updated. Targets to other CPU interfaces are unchanged.
698 * This must be called with IRQs locally disabled.
699 */
gic_migrate_target(unsigned int new_cpu_id)700 void gic_migrate_target(unsigned int new_cpu_id)
701 {
702 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
703 void __iomem *dist_base;
704 int i, ror_val, cpu = smp_processor_id();
705 u32 val, cur_target_mask, active_mask;
706
707 if (gic_nr >= MAX_GIC_NR)
708 BUG();
709
710 dist_base = gic_data_dist_base(&gic_data[gic_nr]);
711 if (!dist_base)
712 return;
713 gic_irqs = gic_data[gic_nr].gic_irqs;
714
715 cur_cpu_id = __ffs(gic_cpu_map[cpu]);
716 cur_target_mask = 0x01010101 << cur_cpu_id;
717 ror_val = (cur_cpu_id - new_cpu_id) & 31;
718
719 raw_spin_lock(&irq_controller_lock);
720
721 /* Update the target interface for this logical CPU */
722 gic_cpu_map[cpu] = 1 << new_cpu_id;
723
724 /*
725 * Find all the peripheral interrupts targetting the current
726 * CPU interface and migrate them to the new CPU interface.
727 * We skip DIST_TARGET 0 to 7 as they are read-only.
728 */
729 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
730 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
731 active_mask = val & cur_target_mask;
732 if (active_mask) {
733 val &= ~active_mask;
734 val |= ror32(active_mask, ror_val);
735 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
736 }
737 }
738
739 raw_spin_unlock(&irq_controller_lock);
740
741 /*
742 * Now let's migrate and clear any potential SGIs that might be
743 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET
744 * is a banked register, we can only forward the SGI using
745 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux
746 * doesn't use that information anyway.
747 *
748 * For the same reason we do not adjust SGI source information
749 * for previously sent SGIs by us to other CPUs either.
750 */
751 for (i = 0; i < 16; i += 4) {
752 int j;
753 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
754 if (!val)
755 continue;
756 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
757 for (j = i; j < i + 4; j++) {
758 if (val & 0xff)
759 writel_relaxed((1 << (new_cpu_id + 16)) | j,
760 dist_base + GIC_DIST_SOFTINT);
761 val >>= 8;
762 }
763 }
764 }
765
766 /*
767 * gic_get_sgir_physaddr - get the physical address for the SGI register
768 *
769 * REturn the physical address of the SGI register to be used
770 * by some early assembly code when the kernel is not yet available.
771 */
772 static unsigned long gic_dist_physaddr;
773
gic_get_sgir_physaddr(void)774 unsigned long gic_get_sgir_physaddr(void)
775 {
776 if (!gic_dist_physaddr)
777 return 0;
778 return gic_dist_physaddr + GIC_DIST_SOFTINT;
779 }
780
gic_init_physaddr(struct device_node * node)781 void __init gic_init_physaddr(struct device_node *node)
782 {
783 struct resource res;
784 if (of_address_to_resource(node, 0, &res) == 0) {
785 gic_dist_physaddr = res.start;
786 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
787 }
788 }
789
790 #else
791 #define gic_init_physaddr(node) do { } while (0)
792 #endif
793
gic_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)794 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
795 irq_hw_number_t hw)
796 {
797 if (hw < 32) {
798 irq_set_percpu_devid(irq);
799 irq_set_chip_and_handler(irq, &gic_chip,
800 handle_percpu_devid_irq);
801 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
802 } else {
803 irq_set_chip_and_handler(irq, &gic_chip,
804 handle_fasteoi_irq);
805 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
806
807 gic_routable_irq_domain_ops->map(d, irq, hw);
808 }
809 irq_set_chip_data(irq, d->host_data);
810 return 0;
811 }
812
gic_irq_domain_unmap(struct irq_domain * d,unsigned int irq)813 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
814 {
815 gic_routable_irq_domain_ops->unmap(d, irq);
816 }
817
gic_irq_domain_xlate(struct irq_domain * d,struct device_node * controller,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)818 static int gic_irq_domain_xlate(struct irq_domain *d,
819 struct device_node *controller,
820 const u32 *intspec, unsigned int intsize,
821 unsigned long *out_hwirq, unsigned int *out_type)
822 {
823 unsigned long ret = 0;
824
825 if (d->of_node != controller)
826 return -EINVAL;
827 if (intsize < 3)
828 return -EINVAL;
829
830 /* Get the interrupt number and add 16 to skip over SGIs */
831 *out_hwirq = intspec[1] + 16;
832
833 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
834 if (!intspec[0]) {
835 ret = gic_routable_irq_domain_ops->xlate(d, controller,
836 intspec,
837 intsize,
838 out_hwirq,
839 out_type);
840
841 if (IS_ERR_VALUE(ret))
842 return ret;
843 }
844
845 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
846
847 return ret;
848 }
849
850 #ifdef CONFIG_SMP
gic_secondary_init(struct notifier_block * nfb,unsigned long action,void * hcpu)851 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
852 void *hcpu)
853 {
854 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
855 gic_cpu_init(&gic_data[0]);
856 return NOTIFY_OK;
857 }
858
859 /*
860 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
861 * priority because the GIC needs to be up before the ARM generic timers.
862 */
863 static struct notifier_block gic_cpu_notifier = {
864 .notifier_call = gic_secondary_init,
865 .priority = 100,
866 };
867 #endif
868
869 static const struct irq_domain_ops gic_irq_domain_ops = {
870 .map = gic_irq_domain_map,
871 .unmap = gic_irq_domain_unmap,
872 .xlate = gic_irq_domain_xlate,
873 };
874
875 /* Default functions for routable irq domain */
gic_routable_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hw)876 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
877 irq_hw_number_t hw)
878 {
879 return 0;
880 }
881
gic_routable_irq_domain_unmap(struct irq_domain * d,unsigned int irq)882 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
883 unsigned int irq)
884 {
885 }
886
gic_routable_irq_domain_xlate(struct irq_domain * d,struct device_node * controller,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)887 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
888 struct device_node *controller,
889 const u32 *intspec, unsigned int intsize,
890 unsigned long *out_hwirq,
891 unsigned int *out_type)
892 {
893 *out_hwirq += 16;
894 return 0;
895 }
896
897 static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
898 .map = gic_routable_irq_domain_map,
899 .unmap = gic_routable_irq_domain_unmap,
900 .xlate = gic_routable_irq_domain_xlate,
901 };
902
903 const struct irq_domain_ops *gic_routable_irq_domain_ops =
904 &gic_default_routable_irq_domain_ops;
905
gic_init_bases(unsigned int gic_nr,int irq_start,void __iomem * dist_base,void __iomem * cpu_base,u32 percpu_offset,struct device_node * node)906 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
907 void __iomem *dist_base, void __iomem *cpu_base,
908 u32 percpu_offset, struct device_node *node)
909 {
910 irq_hw_number_t hwirq_base;
911 struct gic_chip_data *gic;
912 int gic_irqs, irq_base, i;
913 int nr_routable_irqs;
914
915 BUG_ON(gic_nr >= MAX_GIC_NR);
916
917 gic = &gic_data[gic_nr];
918 #ifdef CONFIG_GIC_NON_BANKED
919 if (percpu_offset) { /* Frankein-GIC without banked registers... */
920 unsigned int cpu;
921
922 gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
923 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
924 if (WARN_ON(!gic->dist_base.percpu_base ||
925 !gic->cpu_base.percpu_base)) {
926 free_percpu(gic->dist_base.percpu_base);
927 free_percpu(gic->cpu_base.percpu_base);
928 return;
929 }
930
931 for_each_possible_cpu(cpu) {
932 u32 mpidr = cpu_logical_map(cpu);
933 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
934 unsigned long offset = percpu_offset * core_id;
935 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
936 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
937 }
938
939 gic_set_base_accessor(gic, gic_get_percpu_base);
940 } else
941 #endif
942 { /* Normal, sane GIC... */
943 WARN(percpu_offset,
944 "GIC_NON_BANKED not enabled, ignoring %08x offset!",
945 percpu_offset);
946 gic->dist_base.common_base = dist_base;
947 gic->cpu_base.common_base = cpu_base;
948 gic_set_base_accessor(gic, gic_get_common_base);
949 }
950
951 /*
952 * Initialize the CPU interface map to all CPUs.
953 * It will be refined as each CPU probes its ID.
954 */
955 for (i = 0; i < NR_GIC_CPU_IF; i++)
956 gic_cpu_map[i] = 0xff;
957
958 /*
959 * For primary GICs, skip over SGIs.
960 * For secondary GICs, skip over PPIs, too.
961 */
962 if (gic_nr == 0 && (irq_start & 31) > 0) {
963 hwirq_base = 16;
964 if (irq_start != -1)
965 irq_start = (irq_start & ~31) + 16;
966 } else {
967 hwirq_base = 32;
968 }
969
970 /*
971 * Find out how many interrupts are supported.
972 * The GIC only supports up to 1020 interrupt sources.
973 */
974 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
975 gic_irqs = (gic_irqs + 1) * 32;
976 if (gic_irqs > 1020)
977 gic_irqs = 1020;
978 gic->gic_irqs = gic_irqs;
979
980 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
981
982 if (of_property_read_u32(node, "arm,routable-irqs",
983 &nr_routable_irqs)) {
984 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
985 numa_node_id());
986 if (IS_ERR_VALUE(irq_base)) {
987 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
988 irq_start);
989 irq_base = irq_start;
990 }
991
992 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
993 hwirq_base, &gic_irq_domain_ops, gic);
994 } else {
995 gic->domain = irq_domain_add_linear(node, nr_routable_irqs,
996 &gic_irq_domain_ops,
997 gic);
998 }
999
1000 if (WARN_ON(!gic->domain))
1001 return;
1002
1003 if (gic_nr == 0) {
1004 #ifdef CONFIG_SMP
1005 set_smp_cross_call(gic_raise_softirq);
1006 register_cpu_notifier(&gic_cpu_notifier);
1007 #endif
1008 set_handle_irq(gic_handle_irq);
1009 }
1010
1011 gic_chip.flags |= gic_arch_extn.flags;
1012 gic_dist_init(gic);
1013 gic_cpu_init(gic);
1014 gic_pm_init(gic);
1015 }
1016
1017 #ifdef CONFIG_OF
1018 static int gic_cnt __initdata;
1019
1020 static int __init
gic_of_init(struct device_node * node,struct device_node * parent)1021 gic_of_init(struct device_node *node, struct device_node *parent)
1022 {
1023 void __iomem *cpu_base;
1024 void __iomem *dist_base;
1025 u32 percpu_offset;
1026 int irq;
1027
1028 if (WARN_ON(!node))
1029 return -ENODEV;
1030
1031 dist_base = of_iomap(node, 0);
1032 WARN(!dist_base, "unable to map gic dist registers\n");
1033
1034 cpu_base = of_iomap(node, 1);
1035 WARN(!cpu_base, "unable to map gic cpu registers\n");
1036
1037 if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1038 percpu_offset = 0;
1039
1040 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1041 if (!gic_cnt)
1042 gic_init_physaddr(node);
1043
1044 if (parent) {
1045 irq = irq_of_parse_and_map(node, 0);
1046 gic_cascade_irq(gic_cnt, irq);
1047 }
1048 gic_cnt++;
1049 return 0;
1050 }
1051 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1052 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1053 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1054 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1055 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1056 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1057
1058 #endif
1059