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Searched refs:MC_SEQ_CAS_TIMING (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h105 #define MC_SEQ_CAS_TIMING 0x28a4 macro
Dnid.h770 #define MC_SEQ_CAS_TIMING 0x28a4 macro
Dbtc_dpm.c1863 case MC_SEQ_CAS_TIMING >> 2: in btc_check_s0_mc_reg_index()
2031 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in btc_initialize_mc_reg_table()
Dsid.h500 #define MC_SEQ_CAS_TIMING 0x28a4 macro
Dcikd.h615 #define MC_SEQ_CAS_TIMING 0x28a4 macro
Devergreend.h287 #define MC_SEQ_CAS_TIMING 0x28a4 macro
Dni_dpm.c2776 case MC_SEQ_CAS_TIMING >> 2: in ni_check_s0_mc_reg_index()
2884 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c976 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2; in cypress_set_mc_reg_address_table()
Dci_dpm.c3944 case MC_SEQ_CAS_TIMING >> 2: in ci_check_s0_mc_reg_index()
4064 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in ci_initialize_mc_reg_table()
Dsi_dpm.c5413 case MC_SEQ_CAS_TIMING >> 2: in si_check_s0_mc_reg_index()
5525 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); in si_initialize_mc_reg_table()