1 /*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include "drmP.h"
26 #include "radeon.h"
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
29 #include "cikd.h"
30 #include "r600_dpm.h"
31 #include "ci_dpm.h"
32 #include "atom.h"
33 #include <linux/seq_file.h>
34
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
39
40 #define SMC_RAM_END 0x40000
41
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
45
46 static const struct ci_pt_defaults defaults_hawaii_xt =
47 {
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
50 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
51 };
52
53 static const struct ci_pt_defaults defaults_hawaii_pro =
54 {
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
57 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
58 };
59
60 static const struct ci_pt_defaults defaults_bonaire_xt =
61 {
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
65 };
66
67 static const struct ci_pt_defaults defaults_bonaire_pro =
68 {
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
72 };
73
74 static const struct ci_pt_defaults defaults_saturn_xt =
75 {
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
79 };
80
81 static const struct ci_pt_defaults defaults_saturn_pro =
82 {
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
86 };
87
88 static const struct ci_pt_config_reg didt_config_ci[] =
89 {
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 { 0xFFFFFFFF }
163 };
164
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
178
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
184 u32 target_tdp);
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
186
ci_get_pi(struct radeon_device * rdev)187 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
188 {
189 struct ci_power_info *pi = rdev->pm.dpm.priv;
190
191 return pi;
192 }
193
ci_get_ps(struct radeon_ps * rps)194 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
195 {
196 struct ci_ps *ps = rps->ps_priv;
197
198 return ps;
199 }
200
ci_initialize_powertune_defaults(struct radeon_device * rdev)201 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
202 {
203 struct ci_power_info *pi = ci_get_pi(rdev);
204
205 switch (rdev->pdev->device) {
206 case 0x6649:
207 case 0x6650:
208 case 0x6651:
209 case 0x6658:
210 case 0x665C:
211 case 0x665D:
212 default:
213 pi->powertune_defaults = &defaults_bonaire_xt;
214 break;
215 case 0x6640:
216 case 0x6641:
217 case 0x6646:
218 case 0x6647:
219 pi->powertune_defaults = &defaults_saturn_xt;
220 break;
221 case 0x67B8:
222 case 0x67B0:
223 pi->powertune_defaults = &defaults_hawaii_xt;
224 break;
225 case 0x67BA:
226 case 0x67B1:
227 pi->powertune_defaults = &defaults_hawaii_pro;
228 break;
229 case 0x67A0:
230 case 0x67A1:
231 case 0x67A2:
232 case 0x67A8:
233 case 0x67A9:
234 case 0x67AA:
235 case 0x67B9:
236 case 0x67BE:
237 pi->powertune_defaults = &defaults_bonaire_xt;
238 break;
239 }
240
241 pi->dte_tj_offset = 0;
242
243 pi->caps_power_containment = true;
244 pi->caps_cac = false;
245 pi->caps_sq_ramping = false;
246 pi->caps_db_ramping = false;
247 pi->caps_td_ramping = false;
248 pi->caps_tcp_ramping = false;
249
250 if (pi->caps_power_containment) {
251 pi->caps_cac = true;
252 pi->enable_bapm_feature = true;
253 pi->enable_tdc_limit_feature = true;
254 pi->enable_pkg_pwr_tracking_feature = true;
255 }
256 }
257
ci_convert_to_vid(u16 vddc)258 static u8 ci_convert_to_vid(u16 vddc)
259 {
260 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
261 }
262
ci_populate_bapm_vddc_vid_sidd(struct radeon_device * rdev)263 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
264 {
265 struct ci_power_info *pi = ci_get_pi(rdev);
266 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
267 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
268 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
269 u32 i;
270
271 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
272 return -EINVAL;
273 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
274 return -EINVAL;
275 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
276 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
277 return -EINVAL;
278
279 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
280 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
281 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
282 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
283 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
284 } else {
285 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
286 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
287 }
288 }
289 return 0;
290 }
291
ci_populate_vddc_vid(struct radeon_device * rdev)292 static int ci_populate_vddc_vid(struct radeon_device *rdev)
293 {
294 struct ci_power_info *pi = ci_get_pi(rdev);
295 u8 *vid = pi->smc_powertune_table.VddCVid;
296 u32 i;
297
298 if (pi->vddc_voltage_table.count > 8)
299 return -EINVAL;
300
301 for (i = 0; i < pi->vddc_voltage_table.count; i++)
302 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
303
304 return 0;
305 }
306
ci_populate_svi_load_line(struct radeon_device * rdev)307 static int ci_populate_svi_load_line(struct radeon_device *rdev)
308 {
309 struct ci_power_info *pi = ci_get_pi(rdev);
310 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
311
312 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
313 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
314 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
315 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
316
317 return 0;
318 }
319
ci_populate_tdc_limit(struct radeon_device * rdev)320 static int ci_populate_tdc_limit(struct radeon_device *rdev)
321 {
322 struct ci_power_info *pi = ci_get_pi(rdev);
323 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
324 u16 tdc_limit;
325
326 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
327 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
328 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
329 pt_defaults->tdc_vddc_throttle_release_limit_perc;
330 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
331
332 return 0;
333 }
334
ci_populate_dw8(struct radeon_device * rdev)335 static int ci_populate_dw8(struct radeon_device *rdev)
336 {
337 struct ci_power_info *pi = ci_get_pi(rdev);
338 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
339 int ret;
340
341 ret = ci_read_smc_sram_dword(rdev,
342 SMU7_FIRMWARE_HEADER_LOCATION +
343 offsetof(SMU7_Firmware_Header, PmFuseTable) +
344 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
345 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
346 pi->sram_end);
347 if (ret)
348 return -EINVAL;
349 else
350 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
351
352 return 0;
353 }
354
ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device * rdev)355 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
356 {
357 struct ci_power_info *pi = ci_get_pi(rdev);
358 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
359 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
360 int i, min, max;
361
362 min = max = hi_vid[0];
363 for (i = 0; i < 8; i++) {
364 if (0 != hi_vid[i]) {
365 if (min > hi_vid[i])
366 min = hi_vid[i];
367 if (max < hi_vid[i])
368 max = hi_vid[i];
369 }
370
371 if (0 != lo_vid[i]) {
372 if (min > lo_vid[i])
373 min = lo_vid[i];
374 if (max < lo_vid[i])
375 max = lo_vid[i];
376 }
377 }
378
379 if ((min == 0) || (max == 0))
380 return -EINVAL;
381 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
382 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
383
384 return 0;
385 }
386
ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device * rdev)387 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
388 {
389 struct ci_power_info *pi = ci_get_pi(rdev);
390 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
391 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
392 struct radeon_cac_tdp_table *cac_tdp_table =
393 rdev->pm.dpm.dyn_state.cac_tdp_table;
394
395 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
396 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
397
398 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
399 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
400
401 return 0;
402 }
403
ci_populate_bapm_parameters_in_dpm_table(struct radeon_device * rdev)404 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
405 {
406 struct ci_power_info *pi = ci_get_pi(rdev);
407 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
408 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
409 struct radeon_cac_tdp_table *cac_tdp_table =
410 rdev->pm.dpm.dyn_state.cac_tdp_table;
411 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
412 int i, j, k;
413 const u16 *def1;
414 const u16 *def2;
415
416 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
417 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
418
419 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
420 dpm_table->GpuTjMax =
421 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
422 dpm_table->GpuTjHyst = 8;
423
424 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
425
426 if (ppm) {
427 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
428 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
429 } else {
430 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
431 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
432 }
433
434 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
435 def1 = pt_defaults->bapmti_r;
436 def2 = pt_defaults->bapmti_rc;
437
438 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
439 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
440 for (k = 0; k < SMU7_DTE_SINKS; k++) {
441 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
442 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
443 def1++;
444 def2++;
445 }
446 }
447 }
448
449 return 0;
450 }
451
ci_populate_pm_base(struct radeon_device * rdev)452 static int ci_populate_pm_base(struct radeon_device *rdev)
453 {
454 struct ci_power_info *pi = ci_get_pi(rdev);
455 u32 pm_fuse_table_offset;
456 int ret;
457
458 if (pi->caps_power_containment) {
459 ret = ci_read_smc_sram_dword(rdev,
460 SMU7_FIRMWARE_HEADER_LOCATION +
461 offsetof(SMU7_Firmware_Header, PmFuseTable),
462 &pm_fuse_table_offset, pi->sram_end);
463 if (ret)
464 return ret;
465 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
466 if (ret)
467 return ret;
468 ret = ci_populate_vddc_vid(rdev);
469 if (ret)
470 return ret;
471 ret = ci_populate_svi_load_line(rdev);
472 if (ret)
473 return ret;
474 ret = ci_populate_tdc_limit(rdev);
475 if (ret)
476 return ret;
477 ret = ci_populate_dw8(rdev);
478 if (ret)
479 return ret;
480 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
481 if (ret)
482 return ret;
483 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
484 if (ret)
485 return ret;
486 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
487 (u8 *)&pi->smc_powertune_table,
488 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
489 if (ret)
490 return ret;
491 }
492
493 return 0;
494 }
495
ci_do_enable_didt(struct radeon_device * rdev,const bool enable)496 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
497 {
498 struct ci_power_info *pi = ci_get_pi(rdev);
499 u32 data;
500
501 if (pi->caps_sq_ramping) {
502 data = RREG32_DIDT(DIDT_SQ_CTRL0);
503 if (enable)
504 data |= DIDT_CTRL_EN;
505 else
506 data &= ~DIDT_CTRL_EN;
507 WREG32_DIDT(DIDT_SQ_CTRL0, data);
508 }
509
510 if (pi->caps_db_ramping) {
511 data = RREG32_DIDT(DIDT_DB_CTRL0);
512 if (enable)
513 data |= DIDT_CTRL_EN;
514 else
515 data &= ~DIDT_CTRL_EN;
516 WREG32_DIDT(DIDT_DB_CTRL0, data);
517 }
518
519 if (pi->caps_td_ramping) {
520 data = RREG32_DIDT(DIDT_TD_CTRL0);
521 if (enable)
522 data |= DIDT_CTRL_EN;
523 else
524 data &= ~DIDT_CTRL_EN;
525 WREG32_DIDT(DIDT_TD_CTRL0, data);
526 }
527
528 if (pi->caps_tcp_ramping) {
529 data = RREG32_DIDT(DIDT_TCP_CTRL0);
530 if (enable)
531 data |= DIDT_CTRL_EN;
532 else
533 data &= ~DIDT_CTRL_EN;
534 WREG32_DIDT(DIDT_TCP_CTRL0, data);
535 }
536 }
537
ci_program_pt_config_registers(struct radeon_device * rdev,const struct ci_pt_config_reg * cac_config_regs)538 static int ci_program_pt_config_registers(struct radeon_device *rdev,
539 const struct ci_pt_config_reg *cac_config_regs)
540 {
541 const struct ci_pt_config_reg *config_regs = cac_config_regs;
542 u32 data;
543 u32 cache = 0;
544
545 if (config_regs == NULL)
546 return -EINVAL;
547
548 while (config_regs->offset != 0xFFFFFFFF) {
549 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
550 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
551 } else {
552 switch (config_regs->type) {
553 case CISLANDS_CONFIGREG_SMC_IND:
554 data = RREG32_SMC(config_regs->offset);
555 break;
556 case CISLANDS_CONFIGREG_DIDT_IND:
557 data = RREG32_DIDT(config_regs->offset);
558 break;
559 default:
560 data = RREG32(config_regs->offset << 2);
561 break;
562 }
563
564 data &= ~config_regs->mask;
565 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
566 data |= cache;
567
568 switch (config_regs->type) {
569 case CISLANDS_CONFIGREG_SMC_IND:
570 WREG32_SMC(config_regs->offset, data);
571 break;
572 case CISLANDS_CONFIGREG_DIDT_IND:
573 WREG32_DIDT(config_regs->offset, data);
574 break;
575 default:
576 WREG32(config_regs->offset << 2, data);
577 break;
578 }
579 cache = 0;
580 }
581 config_regs++;
582 }
583 return 0;
584 }
585
ci_enable_didt(struct radeon_device * rdev,bool enable)586 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
587 {
588 struct ci_power_info *pi = ci_get_pi(rdev);
589 int ret;
590
591 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
592 pi->caps_td_ramping || pi->caps_tcp_ramping) {
593 cik_enter_rlc_safe_mode(rdev);
594
595 if (enable) {
596 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
597 if (ret) {
598 cik_exit_rlc_safe_mode(rdev);
599 return ret;
600 }
601 }
602
603 ci_do_enable_didt(rdev, enable);
604
605 cik_exit_rlc_safe_mode(rdev);
606 }
607
608 return 0;
609 }
610
ci_enable_power_containment(struct radeon_device * rdev,bool enable)611 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
612 {
613 struct ci_power_info *pi = ci_get_pi(rdev);
614 PPSMC_Result smc_result;
615 int ret = 0;
616
617 if (enable) {
618 pi->power_containment_features = 0;
619 if (pi->caps_power_containment) {
620 if (pi->enable_bapm_feature) {
621 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
622 if (smc_result != PPSMC_Result_OK)
623 ret = -EINVAL;
624 else
625 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
626 }
627
628 if (pi->enable_tdc_limit_feature) {
629 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
630 if (smc_result != PPSMC_Result_OK)
631 ret = -EINVAL;
632 else
633 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
634 }
635
636 if (pi->enable_pkg_pwr_tracking_feature) {
637 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
638 if (smc_result != PPSMC_Result_OK) {
639 ret = -EINVAL;
640 } else {
641 struct radeon_cac_tdp_table *cac_tdp_table =
642 rdev->pm.dpm.dyn_state.cac_tdp_table;
643 u32 default_pwr_limit =
644 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
645
646 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
647
648 ci_set_power_limit(rdev, default_pwr_limit);
649 }
650 }
651 }
652 } else {
653 if (pi->caps_power_containment && pi->power_containment_features) {
654 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
655 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
656
657 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
658 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
659
660 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
661 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
662 pi->power_containment_features = 0;
663 }
664 }
665
666 return ret;
667 }
668
ci_enable_smc_cac(struct radeon_device * rdev,bool enable)669 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
670 {
671 struct ci_power_info *pi = ci_get_pi(rdev);
672 PPSMC_Result smc_result;
673 int ret = 0;
674
675 if (pi->caps_cac) {
676 if (enable) {
677 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
678 if (smc_result != PPSMC_Result_OK) {
679 ret = -EINVAL;
680 pi->cac_enabled = false;
681 } else {
682 pi->cac_enabled = true;
683 }
684 } else if (pi->cac_enabled) {
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
686 pi->cac_enabled = false;
687 }
688 }
689
690 return ret;
691 }
692
ci_power_control_set_level(struct radeon_device * rdev)693 static int ci_power_control_set_level(struct radeon_device *rdev)
694 {
695 struct ci_power_info *pi = ci_get_pi(rdev);
696 struct radeon_cac_tdp_table *cac_tdp_table =
697 rdev->pm.dpm.dyn_state.cac_tdp_table;
698 s32 adjust_percent;
699 s32 target_tdp;
700 int ret = 0;
701 bool adjust_polarity = false; /* ??? */
702
703 if (pi->caps_power_containment &&
704 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
705 adjust_percent = adjust_polarity ?
706 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
707 target_tdp = ((100 + adjust_percent) *
708 (s32)cac_tdp_table->configurable_tdp) / 100;
709 target_tdp *= 256;
710
711 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
712 }
713
714 return ret;
715 }
716
ci_dpm_powergate_uvd(struct radeon_device * rdev,bool gate)717 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
718 {
719 struct ci_power_info *pi = ci_get_pi(rdev);
720
721 if (pi->uvd_power_gated == gate)
722 return;
723
724 pi->uvd_power_gated = gate;
725
726 ci_update_uvd_dpm(rdev, gate);
727 }
728
ci_dpm_vblank_too_short(struct radeon_device * rdev)729 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
730 {
731 struct ci_power_info *pi = ci_get_pi(rdev);
732 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
733 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
734
735 /* disable mclk switching if the refresh is >120Hz, even if the
736 * blanking period would allow it
737 */
738 if (r600_dpm_get_vrefresh(rdev) > 120)
739 return true;
740
741 /* disable mclk switching if the refresh is >120Hz, even if the
742 * blanking period would allow it
743 */
744 if (r600_dpm_get_vrefresh(rdev) > 120)
745 return true;
746
747 if (vblank_time < switch_limit)
748 return true;
749 else
750 return false;
751
752 }
753
ci_apply_state_adjust_rules(struct radeon_device * rdev,struct radeon_ps * rps)754 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
755 struct radeon_ps *rps)
756 {
757 struct ci_ps *ps = ci_get_ps(rps);
758 struct ci_power_info *pi = ci_get_pi(rdev);
759 struct radeon_clock_and_voltage_limits *max_limits;
760 bool disable_mclk_switching;
761 u32 sclk, mclk;
762 int i;
763
764 if (rps->vce_active) {
765 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
766 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
767 } else {
768 rps->evclk = 0;
769 rps->ecclk = 0;
770 }
771
772 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
773 ci_dpm_vblank_too_short(rdev))
774 disable_mclk_switching = true;
775 else
776 disable_mclk_switching = false;
777
778 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
779 pi->battery_state = true;
780 else
781 pi->battery_state = false;
782
783 if (rdev->pm.dpm.ac_power)
784 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
785 else
786 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
787
788 if (rdev->pm.dpm.ac_power == false) {
789 for (i = 0; i < ps->performance_level_count; i++) {
790 if (ps->performance_levels[i].mclk > max_limits->mclk)
791 ps->performance_levels[i].mclk = max_limits->mclk;
792 if (ps->performance_levels[i].sclk > max_limits->sclk)
793 ps->performance_levels[i].sclk = max_limits->sclk;
794 }
795 }
796
797 /* XXX validate the min clocks required for display */
798
799 if (disable_mclk_switching) {
800 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
801 sclk = ps->performance_levels[0].sclk;
802 } else {
803 mclk = ps->performance_levels[0].mclk;
804 sclk = ps->performance_levels[0].sclk;
805 }
806
807 if (rps->vce_active) {
808 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
809 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
810 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
811 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
812 }
813
814 ps->performance_levels[0].sclk = sclk;
815 ps->performance_levels[0].mclk = mclk;
816
817 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
818 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
819
820 if (disable_mclk_switching) {
821 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
822 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
823 } else {
824 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
825 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
826 }
827 }
828
ci_set_thermal_temperature_range(struct radeon_device * rdev,int min_temp,int max_temp)829 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
830 int min_temp, int max_temp)
831 {
832 int low_temp = 0 * 1000;
833 int high_temp = 255 * 1000;
834 u32 tmp;
835
836 if (low_temp < min_temp)
837 low_temp = min_temp;
838 if (high_temp > max_temp)
839 high_temp = max_temp;
840 if (high_temp < low_temp) {
841 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
842 return -EINVAL;
843 }
844
845 tmp = RREG32_SMC(CG_THERMAL_INT);
846 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
847 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
848 CI_DIG_THERM_INTL(low_temp / 1000);
849 WREG32_SMC(CG_THERMAL_INT, tmp);
850
851 #if 0
852 /* XXX: need to figure out how to handle this properly */
853 tmp = RREG32_SMC(CG_THERMAL_CTRL);
854 tmp &= DIG_THERM_DPM_MASK;
855 tmp |= DIG_THERM_DPM(high_temp / 1000);
856 WREG32_SMC(CG_THERMAL_CTRL, tmp);
857 #endif
858
859 rdev->pm.dpm.thermal.min_temp = low_temp;
860 rdev->pm.dpm.thermal.max_temp = high_temp;
861
862 return 0;
863 }
864
865 #if 0
866 static int ci_read_smc_soft_register(struct radeon_device *rdev,
867 u16 reg_offset, u32 *value)
868 {
869 struct ci_power_info *pi = ci_get_pi(rdev);
870
871 return ci_read_smc_sram_dword(rdev,
872 pi->soft_regs_start + reg_offset,
873 value, pi->sram_end);
874 }
875 #endif
876
ci_write_smc_soft_register(struct radeon_device * rdev,u16 reg_offset,u32 value)877 static int ci_write_smc_soft_register(struct radeon_device *rdev,
878 u16 reg_offset, u32 value)
879 {
880 struct ci_power_info *pi = ci_get_pi(rdev);
881
882 return ci_write_smc_sram_dword(rdev,
883 pi->soft_regs_start + reg_offset,
884 value, pi->sram_end);
885 }
886
ci_init_fps_limits(struct radeon_device * rdev)887 static void ci_init_fps_limits(struct radeon_device *rdev)
888 {
889 struct ci_power_info *pi = ci_get_pi(rdev);
890 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
891
892 if (pi->caps_fps) {
893 u16 tmp;
894
895 tmp = 45;
896 table->FpsHighT = cpu_to_be16(tmp);
897
898 tmp = 30;
899 table->FpsLowT = cpu_to_be16(tmp);
900 }
901 }
902
ci_update_sclk_t(struct radeon_device * rdev)903 static int ci_update_sclk_t(struct radeon_device *rdev)
904 {
905 struct ci_power_info *pi = ci_get_pi(rdev);
906 int ret = 0;
907 u32 low_sclk_interrupt_t = 0;
908
909 if (pi->caps_sclk_throttle_low_notification) {
910 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
911
912 ret = ci_copy_bytes_to_smc(rdev,
913 pi->dpm_table_start +
914 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
915 (u8 *)&low_sclk_interrupt_t,
916 sizeof(u32), pi->sram_end);
917
918 }
919
920 return ret;
921 }
922
ci_get_leakage_voltages(struct radeon_device * rdev)923 static void ci_get_leakage_voltages(struct radeon_device *rdev)
924 {
925 struct ci_power_info *pi = ci_get_pi(rdev);
926 u16 leakage_id, virtual_voltage_id;
927 u16 vddc, vddci;
928 int i;
929
930 pi->vddc_leakage.count = 0;
931 pi->vddci_leakage.count = 0;
932
933 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
934 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
935 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
936 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
937 continue;
938 if (vddc != 0 && vddc != virtual_voltage_id) {
939 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
940 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
941 pi->vddc_leakage.count++;
942 }
943 }
944 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
945 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
946 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
947 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
948 virtual_voltage_id,
949 leakage_id) == 0) {
950 if (vddc != 0 && vddc != virtual_voltage_id) {
951 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
952 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
953 pi->vddc_leakage.count++;
954 }
955 if (vddci != 0 && vddci != virtual_voltage_id) {
956 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
957 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
958 pi->vddci_leakage.count++;
959 }
960 }
961 }
962 }
963 }
964
ci_set_dpm_event_sources(struct radeon_device * rdev,u32 sources)965 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
966 {
967 struct ci_power_info *pi = ci_get_pi(rdev);
968 bool want_thermal_protection;
969 enum radeon_dpm_event_src dpm_event_src;
970 u32 tmp;
971
972 switch (sources) {
973 case 0:
974 default:
975 want_thermal_protection = false;
976 break;
977 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
978 want_thermal_protection = true;
979 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
980 break;
981 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
982 want_thermal_protection = true;
983 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
984 break;
985 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
986 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
987 want_thermal_protection = true;
988 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
989 break;
990 }
991
992 if (want_thermal_protection) {
993 #if 0
994 /* XXX: need to figure out how to handle this properly */
995 tmp = RREG32_SMC(CG_THERMAL_CTRL);
996 tmp &= DPM_EVENT_SRC_MASK;
997 tmp |= DPM_EVENT_SRC(dpm_event_src);
998 WREG32_SMC(CG_THERMAL_CTRL, tmp);
999 #endif
1000
1001 tmp = RREG32_SMC(GENERAL_PWRMGT);
1002 if (pi->thermal_protection)
1003 tmp &= ~THERMAL_PROTECTION_DIS;
1004 else
1005 tmp |= THERMAL_PROTECTION_DIS;
1006 WREG32_SMC(GENERAL_PWRMGT, tmp);
1007 } else {
1008 tmp = RREG32_SMC(GENERAL_PWRMGT);
1009 tmp |= THERMAL_PROTECTION_DIS;
1010 WREG32_SMC(GENERAL_PWRMGT, tmp);
1011 }
1012 }
1013
ci_enable_auto_throttle_source(struct radeon_device * rdev,enum radeon_dpm_auto_throttle_src source,bool enable)1014 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1015 enum radeon_dpm_auto_throttle_src source,
1016 bool enable)
1017 {
1018 struct ci_power_info *pi = ci_get_pi(rdev);
1019
1020 if (enable) {
1021 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1022 pi->active_auto_throttle_sources |= 1 << source;
1023 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1024 }
1025 } else {
1026 if (pi->active_auto_throttle_sources & (1 << source)) {
1027 pi->active_auto_throttle_sources &= ~(1 << source);
1028 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1029 }
1030 }
1031 }
1032
ci_enable_vr_hot_gpio_interrupt(struct radeon_device * rdev)1033 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1034 {
1035 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1036 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1037 }
1038
ci_unfreeze_sclk_mclk_dpm(struct radeon_device * rdev)1039 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1040 {
1041 struct ci_power_info *pi = ci_get_pi(rdev);
1042 PPSMC_Result smc_result;
1043
1044 if (!pi->need_update_smu7_dpm_table)
1045 return 0;
1046
1047 if ((!pi->sclk_dpm_key_disabled) &&
1048 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1049 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1050 if (smc_result != PPSMC_Result_OK)
1051 return -EINVAL;
1052 }
1053
1054 if ((!pi->mclk_dpm_key_disabled) &&
1055 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1056 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1057 if (smc_result != PPSMC_Result_OK)
1058 return -EINVAL;
1059 }
1060
1061 pi->need_update_smu7_dpm_table = 0;
1062 return 0;
1063 }
1064
ci_enable_sclk_mclk_dpm(struct radeon_device * rdev,bool enable)1065 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1066 {
1067 struct ci_power_info *pi = ci_get_pi(rdev);
1068 PPSMC_Result smc_result;
1069
1070 if (enable) {
1071 if (!pi->sclk_dpm_key_disabled) {
1072 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1073 if (smc_result != PPSMC_Result_OK)
1074 return -EINVAL;
1075 }
1076
1077 if (!pi->mclk_dpm_key_disabled) {
1078 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1079 if (smc_result != PPSMC_Result_OK)
1080 return -EINVAL;
1081
1082 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1083
1084 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1085 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1086 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1087
1088 udelay(10);
1089
1090 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1091 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1092 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1093 }
1094 } else {
1095 if (!pi->sclk_dpm_key_disabled) {
1096 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1097 if (smc_result != PPSMC_Result_OK)
1098 return -EINVAL;
1099 }
1100
1101 if (!pi->mclk_dpm_key_disabled) {
1102 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1103 if (smc_result != PPSMC_Result_OK)
1104 return -EINVAL;
1105 }
1106 }
1107
1108 return 0;
1109 }
1110
ci_start_dpm(struct radeon_device * rdev)1111 static int ci_start_dpm(struct radeon_device *rdev)
1112 {
1113 struct ci_power_info *pi = ci_get_pi(rdev);
1114 PPSMC_Result smc_result;
1115 int ret;
1116 u32 tmp;
1117
1118 tmp = RREG32_SMC(GENERAL_PWRMGT);
1119 tmp |= GLOBAL_PWRMGT_EN;
1120 WREG32_SMC(GENERAL_PWRMGT, tmp);
1121
1122 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1123 tmp |= DYNAMIC_PM_EN;
1124 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1125
1126 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1127
1128 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1129
1130 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1131 if (smc_result != PPSMC_Result_OK)
1132 return -EINVAL;
1133
1134 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1135 if (ret)
1136 return ret;
1137
1138 if (!pi->pcie_dpm_key_disabled) {
1139 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1140 if (smc_result != PPSMC_Result_OK)
1141 return -EINVAL;
1142 }
1143
1144 return 0;
1145 }
1146
ci_freeze_sclk_mclk_dpm(struct radeon_device * rdev)1147 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1148 {
1149 struct ci_power_info *pi = ci_get_pi(rdev);
1150 PPSMC_Result smc_result;
1151
1152 if (!pi->need_update_smu7_dpm_table)
1153 return 0;
1154
1155 if ((!pi->sclk_dpm_key_disabled) &&
1156 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1157 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1158 if (smc_result != PPSMC_Result_OK)
1159 return -EINVAL;
1160 }
1161
1162 if ((!pi->mclk_dpm_key_disabled) &&
1163 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1164 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1165 if (smc_result != PPSMC_Result_OK)
1166 return -EINVAL;
1167 }
1168
1169 return 0;
1170 }
1171
ci_stop_dpm(struct radeon_device * rdev)1172 static int ci_stop_dpm(struct radeon_device *rdev)
1173 {
1174 struct ci_power_info *pi = ci_get_pi(rdev);
1175 PPSMC_Result smc_result;
1176 int ret;
1177 u32 tmp;
1178
1179 tmp = RREG32_SMC(GENERAL_PWRMGT);
1180 tmp &= ~GLOBAL_PWRMGT_EN;
1181 WREG32_SMC(GENERAL_PWRMGT, tmp);
1182
1183 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1184 tmp &= ~DYNAMIC_PM_EN;
1185 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1186
1187 if (!pi->pcie_dpm_key_disabled) {
1188 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1189 if (smc_result != PPSMC_Result_OK)
1190 return -EINVAL;
1191 }
1192
1193 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1194 if (ret)
1195 return ret;
1196
1197 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1198 if (smc_result != PPSMC_Result_OK)
1199 return -EINVAL;
1200
1201 return 0;
1202 }
1203
ci_enable_sclk_control(struct radeon_device * rdev,bool enable)1204 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1205 {
1206 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1207
1208 if (enable)
1209 tmp &= ~SCLK_PWRMGT_OFF;
1210 else
1211 tmp |= SCLK_PWRMGT_OFF;
1212 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1213 }
1214
1215 #if 0
1216 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1217 bool ac_power)
1218 {
1219 struct ci_power_info *pi = ci_get_pi(rdev);
1220 struct radeon_cac_tdp_table *cac_tdp_table =
1221 rdev->pm.dpm.dyn_state.cac_tdp_table;
1222 u32 power_limit;
1223
1224 if (ac_power)
1225 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1226 else
1227 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1228
1229 ci_set_power_limit(rdev, power_limit);
1230
1231 if (pi->caps_automatic_dc_transition) {
1232 if (ac_power)
1233 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1234 else
1235 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1236 }
1237
1238 return 0;
1239 }
1240 #endif
1241
ci_send_msg_to_smc_with_parameter(struct radeon_device * rdev,PPSMC_Msg msg,u32 parameter)1242 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1243 PPSMC_Msg msg, u32 parameter)
1244 {
1245 WREG32(SMC_MSG_ARG_0, parameter);
1246 return ci_send_msg_to_smc(rdev, msg);
1247 }
1248
ci_send_msg_to_smc_return_parameter(struct radeon_device * rdev,PPSMC_Msg msg,u32 * parameter)1249 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1250 PPSMC_Msg msg, u32 *parameter)
1251 {
1252 PPSMC_Result smc_result;
1253
1254 smc_result = ci_send_msg_to_smc(rdev, msg);
1255
1256 if ((smc_result == PPSMC_Result_OK) && parameter)
1257 *parameter = RREG32(SMC_MSG_ARG_0);
1258
1259 return smc_result;
1260 }
1261
ci_dpm_force_state_sclk(struct radeon_device * rdev,u32 n)1262 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1263 {
1264 struct ci_power_info *pi = ci_get_pi(rdev);
1265
1266 if (!pi->sclk_dpm_key_disabled) {
1267 PPSMC_Result smc_result =
1268 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1269 if (smc_result != PPSMC_Result_OK)
1270 return -EINVAL;
1271 }
1272
1273 return 0;
1274 }
1275
ci_dpm_force_state_mclk(struct radeon_device * rdev,u32 n)1276 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1277 {
1278 struct ci_power_info *pi = ci_get_pi(rdev);
1279
1280 if (!pi->mclk_dpm_key_disabled) {
1281 PPSMC_Result smc_result =
1282 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1283 if (smc_result != PPSMC_Result_OK)
1284 return -EINVAL;
1285 }
1286
1287 return 0;
1288 }
1289
ci_dpm_force_state_pcie(struct radeon_device * rdev,u32 n)1290 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1291 {
1292 struct ci_power_info *pi = ci_get_pi(rdev);
1293
1294 if (!pi->pcie_dpm_key_disabled) {
1295 PPSMC_Result smc_result =
1296 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1297 if (smc_result != PPSMC_Result_OK)
1298 return -EINVAL;
1299 }
1300
1301 return 0;
1302 }
1303
ci_set_power_limit(struct radeon_device * rdev,u32 n)1304 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1305 {
1306 struct ci_power_info *pi = ci_get_pi(rdev);
1307
1308 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1309 PPSMC_Result smc_result =
1310 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1311 if (smc_result != PPSMC_Result_OK)
1312 return -EINVAL;
1313 }
1314
1315 return 0;
1316 }
1317
ci_set_overdrive_target_tdp(struct radeon_device * rdev,u32 target_tdp)1318 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1319 u32 target_tdp)
1320 {
1321 PPSMC_Result smc_result =
1322 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1323 if (smc_result != PPSMC_Result_OK)
1324 return -EINVAL;
1325 return 0;
1326 }
1327
ci_set_boot_state(struct radeon_device * rdev)1328 static int ci_set_boot_state(struct radeon_device *rdev)
1329 {
1330 return ci_enable_sclk_mclk_dpm(rdev, false);
1331 }
1332
ci_get_average_sclk_freq(struct radeon_device * rdev)1333 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1334 {
1335 u32 sclk_freq;
1336 PPSMC_Result smc_result =
1337 ci_send_msg_to_smc_return_parameter(rdev,
1338 PPSMC_MSG_API_GetSclkFrequency,
1339 &sclk_freq);
1340 if (smc_result != PPSMC_Result_OK)
1341 sclk_freq = 0;
1342
1343 return sclk_freq;
1344 }
1345
ci_get_average_mclk_freq(struct radeon_device * rdev)1346 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1347 {
1348 u32 mclk_freq;
1349 PPSMC_Result smc_result =
1350 ci_send_msg_to_smc_return_parameter(rdev,
1351 PPSMC_MSG_API_GetMclkFrequency,
1352 &mclk_freq);
1353 if (smc_result != PPSMC_Result_OK)
1354 mclk_freq = 0;
1355
1356 return mclk_freq;
1357 }
1358
ci_dpm_start_smc(struct radeon_device * rdev)1359 static void ci_dpm_start_smc(struct radeon_device *rdev)
1360 {
1361 int i;
1362
1363 ci_program_jump_on_start(rdev);
1364 ci_start_smc_clock(rdev);
1365 ci_start_smc(rdev);
1366 for (i = 0; i < rdev->usec_timeout; i++) {
1367 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1368 break;
1369 }
1370 }
1371
ci_dpm_stop_smc(struct radeon_device * rdev)1372 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1373 {
1374 ci_reset_smc(rdev);
1375 ci_stop_smc_clock(rdev);
1376 }
1377
ci_process_firmware_header(struct radeon_device * rdev)1378 static int ci_process_firmware_header(struct radeon_device *rdev)
1379 {
1380 struct ci_power_info *pi = ci_get_pi(rdev);
1381 u32 tmp;
1382 int ret;
1383
1384 ret = ci_read_smc_sram_dword(rdev,
1385 SMU7_FIRMWARE_HEADER_LOCATION +
1386 offsetof(SMU7_Firmware_Header, DpmTable),
1387 &tmp, pi->sram_end);
1388 if (ret)
1389 return ret;
1390
1391 pi->dpm_table_start = tmp;
1392
1393 ret = ci_read_smc_sram_dword(rdev,
1394 SMU7_FIRMWARE_HEADER_LOCATION +
1395 offsetof(SMU7_Firmware_Header, SoftRegisters),
1396 &tmp, pi->sram_end);
1397 if (ret)
1398 return ret;
1399
1400 pi->soft_regs_start = tmp;
1401
1402 ret = ci_read_smc_sram_dword(rdev,
1403 SMU7_FIRMWARE_HEADER_LOCATION +
1404 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1405 &tmp, pi->sram_end);
1406 if (ret)
1407 return ret;
1408
1409 pi->mc_reg_table_start = tmp;
1410
1411 ret = ci_read_smc_sram_dword(rdev,
1412 SMU7_FIRMWARE_HEADER_LOCATION +
1413 offsetof(SMU7_Firmware_Header, FanTable),
1414 &tmp, pi->sram_end);
1415 if (ret)
1416 return ret;
1417
1418 pi->fan_table_start = tmp;
1419
1420 ret = ci_read_smc_sram_dword(rdev,
1421 SMU7_FIRMWARE_HEADER_LOCATION +
1422 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1423 &tmp, pi->sram_end);
1424 if (ret)
1425 return ret;
1426
1427 pi->arb_table_start = tmp;
1428
1429 return 0;
1430 }
1431
ci_read_clock_registers(struct radeon_device * rdev)1432 static void ci_read_clock_registers(struct radeon_device *rdev)
1433 {
1434 struct ci_power_info *pi = ci_get_pi(rdev);
1435
1436 pi->clock_registers.cg_spll_func_cntl =
1437 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1438 pi->clock_registers.cg_spll_func_cntl_2 =
1439 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1440 pi->clock_registers.cg_spll_func_cntl_3 =
1441 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1442 pi->clock_registers.cg_spll_func_cntl_4 =
1443 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1444 pi->clock_registers.cg_spll_spread_spectrum =
1445 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1446 pi->clock_registers.cg_spll_spread_spectrum_2 =
1447 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1448 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1449 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1450 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1451 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1452 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1453 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1454 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1455 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1456 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1457 }
1458
ci_init_sclk_t(struct radeon_device * rdev)1459 static void ci_init_sclk_t(struct radeon_device *rdev)
1460 {
1461 struct ci_power_info *pi = ci_get_pi(rdev);
1462
1463 pi->low_sclk_interrupt_t = 0;
1464 }
1465
ci_enable_thermal_protection(struct radeon_device * rdev,bool enable)1466 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1467 bool enable)
1468 {
1469 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1470
1471 if (enable)
1472 tmp &= ~THERMAL_PROTECTION_DIS;
1473 else
1474 tmp |= THERMAL_PROTECTION_DIS;
1475 WREG32_SMC(GENERAL_PWRMGT, tmp);
1476 }
1477
ci_enable_acpi_power_management(struct radeon_device * rdev)1478 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1479 {
1480 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1481
1482 tmp |= STATIC_PM_EN;
1483
1484 WREG32_SMC(GENERAL_PWRMGT, tmp);
1485 }
1486
1487 #if 0
1488 static int ci_enter_ulp_state(struct radeon_device *rdev)
1489 {
1490
1491 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1492
1493 udelay(25000);
1494
1495 return 0;
1496 }
1497
1498 static int ci_exit_ulp_state(struct radeon_device *rdev)
1499 {
1500 int i;
1501
1502 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1503
1504 udelay(7000);
1505
1506 for (i = 0; i < rdev->usec_timeout; i++) {
1507 if (RREG32(SMC_RESP_0) == 1)
1508 break;
1509 udelay(1000);
1510 }
1511
1512 return 0;
1513 }
1514 #endif
1515
ci_notify_smc_display_change(struct radeon_device * rdev,bool has_display)1516 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1517 bool has_display)
1518 {
1519 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1520
1521 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1522 }
1523
ci_enable_ds_master_switch(struct radeon_device * rdev,bool enable)1524 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1525 bool enable)
1526 {
1527 struct ci_power_info *pi = ci_get_pi(rdev);
1528
1529 if (enable) {
1530 if (pi->caps_sclk_ds) {
1531 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1532 return -EINVAL;
1533 } else {
1534 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1535 return -EINVAL;
1536 }
1537 } else {
1538 if (pi->caps_sclk_ds) {
1539 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1540 return -EINVAL;
1541 }
1542 }
1543
1544 return 0;
1545 }
1546
ci_program_display_gap(struct radeon_device * rdev)1547 static void ci_program_display_gap(struct radeon_device *rdev)
1548 {
1549 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1550 u32 pre_vbi_time_in_us;
1551 u32 frame_time_in_us;
1552 u32 ref_clock = rdev->clock.spll.reference_freq;
1553 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1554 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1555
1556 tmp &= ~DISP_GAP_MASK;
1557 if (rdev->pm.dpm.new_active_crtc_count > 0)
1558 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1559 else
1560 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1561 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1562
1563 if (refresh_rate == 0)
1564 refresh_rate = 60;
1565 if (vblank_time == 0xffffffff)
1566 vblank_time = 500;
1567 frame_time_in_us = 1000000 / refresh_rate;
1568 pre_vbi_time_in_us =
1569 frame_time_in_us - 200 - vblank_time;
1570 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1571
1572 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1573 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1574 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1575
1576
1577 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1578
1579 }
1580
ci_enable_spread_spectrum(struct radeon_device * rdev,bool enable)1581 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1582 {
1583 struct ci_power_info *pi = ci_get_pi(rdev);
1584 u32 tmp;
1585
1586 if (enable) {
1587 if (pi->caps_sclk_ss_support) {
1588 tmp = RREG32_SMC(GENERAL_PWRMGT);
1589 tmp |= DYN_SPREAD_SPECTRUM_EN;
1590 WREG32_SMC(GENERAL_PWRMGT, tmp);
1591 }
1592 } else {
1593 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1594 tmp &= ~SSEN;
1595 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1596
1597 tmp = RREG32_SMC(GENERAL_PWRMGT);
1598 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1599 WREG32_SMC(GENERAL_PWRMGT, tmp);
1600 }
1601 }
1602
ci_program_sstp(struct radeon_device * rdev)1603 static void ci_program_sstp(struct radeon_device *rdev)
1604 {
1605 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1606 }
1607
ci_enable_display_gap(struct radeon_device * rdev)1608 static void ci_enable_display_gap(struct radeon_device *rdev)
1609 {
1610 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1611
1612 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1613 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1614 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1615
1616 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1617 }
1618
ci_program_vc(struct radeon_device * rdev)1619 static void ci_program_vc(struct radeon_device *rdev)
1620 {
1621 u32 tmp;
1622
1623 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1624 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1625 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1626
1627 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1628 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1629 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1630 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1631 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1632 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1633 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1634 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1635 }
1636
ci_clear_vc(struct radeon_device * rdev)1637 static void ci_clear_vc(struct radeon_device *rdev)
1638 {
1639 u32 tmp;
1640
1641 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1642 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1643 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1644
1645 WREG32_SMC(CG_FTV_0, 0);
1646 WREG32_SMC(CG_FTV_1, 0);
1647 WREG32_SMC(CG_FTV_2, 0);
1648 WREG32_SMC(CG_FTV_3, 0);
1649 WREG32_SMC(CG_FTV_4, 0);
1650 WREG32_SMC(CG_FTV_5, 0);
1651 WREG32_SMC(CG_FTV_6, 0);
1652 WREG32_SMC(CG_FTV_7, 0);
1653 }
1654
ci_upload_firmware(struct radeon_device * rdev)1655 static int ci_upload_firmware(struct radeon_device *rdev)
1656 {
1657 struct ci_power_info *pi = ci_get_pi(rdev);
1658 int i, ret;
1659
1660 for (i = 0; i < rdev->usec_timeout; i++) {
1661 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1662 break;
1663 }
1664 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1665
1666 ci_stop_smc_clock(rdev);
1667 ci_reset_smc(rdev);
1668
1669 ret = ci_load_smc_ucode(rdev, pi->sram_end);
1670
1671 return ret;
1672
1673 }
1674
ci_get_svi2_voltage_table(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * voltage_dependency_table,struct atom_voltage_table * voltage_table)1675 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1676 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1677 struct atom_voltage_table *voltage_table)
1678 {
1679 u32 i;
1680
1681 if (voltage_dependency_table == NULL)
1682 return -EINVAL;
1683
1684 voltage_table->mask_low = 0;
1685 voltage_table->phase_delay = 0;
1686
1687 voltage_table->count = voltage_dependency_table->count;
1688 for (i = 0; i < voltage_table->count; i++) {
1689 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1690 voltage_table->entries[i].smio_low = 0;
1691 }
1692
1693 return 0;
1694 }
1695
ci_construct_voltage_tables(struct radeon_device * rdev)1696 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1697 {
1698 struct ci_power_info *pi = ci_get_pi(rdev);
1699 int ret;
1700
1701 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1702 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1703 VOLTAGE_OBJ_GPIO_LUT,
1704 &pi->vddc_voltage_table);
1705 if (ret)
1706 return ret;
1707 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1708 ret = ci_get_svi2_voltage_table(rdev,
1709 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1710 &pi->vddc_voltage_table);
1711 if (ret)
1712 return ret;
1713 }
1714
1715 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1716 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1717 &pi->vddc_voltage_table);
1718
1719 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1720 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1721 VOLTAGE_OBJ_GPIO_LUT,
1722 &pi->vddci_voltage_table);
1723 if (ret)
1724 return ret;
1725 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1726 ret = ci_get_svi2_voltage_table(rdev,
1727 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1728 &pi->vddci_voltage_table);
1729 if (ret)
1730 return ret;
1731 }
1732
1733 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1734 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1735 &pi->vddci_voltage_table);
1736
1737 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1738 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1739 VOLTAGE_OBJ_GPIO_LUT,
1740 &pi->mvdd_voltage_table);
1741 if (ret)
1742 return ret;
1743 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1744 ret = ci_get_svi2_voltage_table(rdev,
1745 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1746 &pi->mvdd_voltage_table);
1747 if (ret)
1748 return ret;
1749 }
1750
1751 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1752 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1753 &pi->mvdd_voltage_table);
1754
1755 return 0;
1756 }
1757
ci_populate_smc_voltage_table(struct radeon_device * rdev,struct atom_voltage_table_entry * voltage_table,SMU7_Discrete_VoltageLevel * smc_voltage_table)1758 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1759 struct atom_voltage_table_entry *voltage_table,
1760 SMU7_Discrete_VoltageLevel *smc_voltage_table)
1761 {
1762 int ret;
1763
1764 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1765 &smc_voltage_table->StdVoltageHiSidd,
1766 &smc_voltage_table->StdVoltageLoSidd);
1767
1768 if (ret) {
1769 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1770 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1771 }
1772
1773 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1774 smc_voltage_table->StdVoltageHiSidd =
1775 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1776 smc_voltage_table->StdVoltageLoSidd =
1777 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1778 }
1779
ci_populate_smc_vddc_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)1780 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1781 SMU7_Discrete_DpmTable *table)
1782 {
1783 struct ci_power_info *pi = ci_get_pi(rdev);
1784 unsigned int count;
1785
1786 table->VddcLevelCount = pi->vddc_voltage_table.count;
1787 for (count = 0; count < table->VddcLevelCount; count++) {
1788 ci_populate_smc_voltage_table(rdev,
1789 &pi->vddc_voltage_table.entries[count],
1790 &table->VddcLevel[count]);
1791
1792 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1793 table->VddcLevel[count].Smio |=
1794 pi->vddc_voltage_table.entries[count].smio_low;
1795 else
1796 table->VddcLevel[count].Smio = 0;
1797 }
1798 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1799
1800 return 0;
1801 }
1802
ci_populate_smc_vddci_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)1803 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1804 SMU7_Discrete_DpmTable *table)
1805 {
1806 unsigned int count;
1807 struct ci_power_info *pi = ci_get_pi(rdev);
1808
1809 table->VddciLevelCount = pi->vddci_voltage_table.count;
1810 for (count = 0; count < table->VddciLevelCount; count++) {
1811 ci_populate_smc_voltage_table(rdev,
1812 &pi->vddci_voltage_table.entries[count],
1813 &table->VddciLevel[count]);
1814
1815 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1816 table->VddciLevel[count].Smio |=
1817 pi->vddci_voltage_table.entries[count].smio_low;
1818 else
1819 table->VddciLevel[count].Smio = 0;
1820 }
1821 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1822
1823 return 0;
1824 }
1825
ci_populate_smc_mvdd_table(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)1826 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1827 SMU7_Discrete_DpmTable *table)
1828 {
1829 struct ci_power_info *pi = ci_get_pi(rdev);
1830 unsigned int count;
1831
1832 table->MvddLevelCount = pi->mvdd_voltage_table.count;
1833 for (count = 0; count < table->MvddLevelCount; count++) {
1834 ci_populate_smc_voltage_table(rdev,
1835 &pi->mvdd_voltage_table.entries[count],
1836 &table->MvddLevel[count]);
1837
1838 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1839 table->MvddLevel[count].Smio |=
1840 pi->mvdd_voltage_table.entries[count].smio_low;
1841 else
1842 table->MvddLevel[count].Smio = 0;
1843 }
1844 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1845
1846 return 0;
1847 }
1848
ci_populate_smc_voltage_tables(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)1849 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1850 SMU7_Discrete_DpmTable *table)
1851 {
1852 int ret;
1853
1854 ret = ci_populate_smc_vddc_table(rdev, table);
1855 if (ret)
1856 return ret;
1857
1858 ret = ci_populate_smc_vddci_table(rdev, table);
1859 if (ret)
1860 return ret;
1861
1862 ret = ci_populate_smc_mvdd_table(rdev, table);
1863 if (ret)
1864 return ret;
1865
1866 return 0;
1867 }
1868
ci_populate_mvdd_value(struct radeon_device * rdev,u32 mclk,SMU7_Discrete_VoltageLevel * voltage)1869 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1870 SMU7_Discrete_VoltageLevel *voltage)
1871 {
1872 struct ci_power_info *pi = ci_get_pi(rdev);
1873 u32 i = 0;
1874
1875 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1876 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1877 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1878 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1879 break;
1880 }
1881 }
1882
1883 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1884 return -EINVAL;
1885 }
1886
1887 return -EINVAL;
1888 }
1889
ci_get_std_voltage_value_sidd(struct radeon_device * rdev,struct atom_voltage_table_entry * voltage_table,u16 * std_voltage_hi_sidd,u16 * std_voltage_lo_sidd)1890 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1891 struct atom_voltage_table_entry *voltage_table,
1892 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1893 {
1894 u16 v_index, idx;
1895 bool voltage_found = false;
1896 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1897 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1898
1899 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1900 return -EINVAL;
1901
1902 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1903 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1904 if (voltage_table->value ==
1905 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1906 voltage_found = true;
1907 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1908 idx = v_index;
1909 else
1910 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1911 *std_voltage_lo_sidd =
1912 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1913 *std_voltage_hi_sidd =
1914 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1915 break;
1916 }
1917 }
1918
1919 if (!voltage_found) {
1920 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1921 if (voltage_table->value <=
1922 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1923 voltage_found = true;
1924 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1925 idx = v_index;
1926 else
1927 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1928 *std_voltage_lo_sidd =
1929 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1930 *std_voltage_hi_sidd =
1931 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1932 break;
1933 }
1934 }
1935 }
1936 }
1937
1938 return 0;
1939 }
1940
ci_populate_phase_value_based_on_sclk(struct radeon_device * rdev,const struct radeon_phase_shedding_limits_table * limits,u32 sclk,u32 * phase_shedding)1941 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1942 const struct radeon_phase_shedding_limits_table *limits,
1943 u32 sclk,
1944 u32 *phase_shedding)
1945 {
1946 unsigned int i;
1947
1948 *phase_shedding = 1;
1949
1950 for (i = 0; i < limits->count; i++) {
1951 if (sclk < limits->entries[i].sclk) {
1952 *phase_shedding = i;
1953 break;
1954 }
1955 }
1956 }
1957
ci_populate_phase_value_based_on_mclk(struct radeon_device * rdev,const struct radeon_phase_shedding_limits_table * limits,u32 mclk,u32 * phase_shedding)1958 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1959 const struct radeon_phase_shedding_limits_table *limits,
1960 u32 mclk,
1961 u32 *phase_shedding)
1962 {
1963 unsigned int i;
1964
1965 *phase_shedding = 1;
1966
1967 for (i = 0; i < limits->count; i++) {
1968 if (mclk < limits->entries[i].mclk) {
1969 *phase_shedding = i;
1970 break;
1971 }
1972 }
1973 }
1974
ci_init_arb_table_index(struct radeon_device * rdev)1975 static int ci_init_arb_table_index(struct radeon_device *rdev)
1976 {
1977 struct ci_power_info *pi = ci_get_pi(rdev);
1978 u32 tmp;
1979 int ret;
1980
1981 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1982 &tmp, pi->sram_end);
1983 if (ret)
1984 return ret;
1985
1986 tmp &= 0x00FFFFFF;
1987 tmp |= MC_CG_ARB_FREQ_F1 << 24;
1988
1989 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
1990 tmp, pi->sram_end);
1991 }
1992
ci_get_dependency_volt_by_clk(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * allowed_clock_voltage_table,u32 clock,u32 * voltage)1993 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
1994 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
1995 u32 clock, u32 *voltage)
1996 {
1997 u32 i = 0;
1998
1999 if (allowed_clock_voltage_table->count == 0)
2000 return -EINVAL;
2001
2002 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2003 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2004 *voltage = allowed_clock_voltage_table->entries[i].v;
2005 return 0;
2006 }
2007 }
2008
2009 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2010
2011 return 0;
2012 }
2013
ci_get_sleep_divider_id_from_clock(struct radeon_device * rdev,u32 sclk,u32 min_sclk_in_sr)2014 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2015 u32 sclk, u32 min_sclk_in_sr)
2016 {
2017 u32 i;
2018 u32 tmp;
2019 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2020 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2021
2022 if (sclk < min)
2023 return 0;
2024
2025 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2026 tmp = sclk / (1 << i);
2027 if (tmp >= min || i == 0)
2028 break;
2029 }
2030
2031 return (u8)i;
2032 }
2033
ci_initial_switch_from_arb_f0_to_f1(struct radeon_device * rdev)2034 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2035 {
2036 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2037 }
2038
ci_reset_to_default(struct radeon_device * rdev)2039 static int ci_reset_to_default(struct radeon_device *rdev)
2040 {
2041 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2042 0 : -EINVAL;
2043 }
2044
ci_force_switch_to_arb_f0(struct radeon_device * rdev)2045 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2046 {
2047 u32 tmp;
2048
2049 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2050
2051 if (tmp == MC_CG_ARB_FREQ_F0)
2052 return 0;
2053
2054 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2055 }
2056
ci_populate_memory_timing_parameters(struct radeon_device * rdev,u32 sclk,u32 mclk,SMU7_Discrete_MCArbDramTimingTableEntry * arb_regs)2057 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2058 u32 sclk,
2059 u32 mclk,
2060 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2061 {
2062 u32 dram_timing;
2063 u32 dram_timing2;
2064 u32 burst_time;
2065
2066 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2067
2068 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2069 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2070 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2071
2072 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2073 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2074 arb_regs->McArbBurstTime = (u8)burst_time;
2075
2076 return 0;
2077 }
2078
ci_do_program_memory_timing_parameters(struct radeon_device * rdev)2079 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2080 {
2081 struct ci_power_info *pi = ci_get_pi(rdev);
2082 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2083 u32 i, j;
2084 int ret = 0;
2085
2086 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2087
2088 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2089 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2090 ret = ci_populate_memory_timing_parameters(rdev,
2091 pi->dpm_table.sclk_table.dpm_levels[i].value,
2092 pi->dpm_table.mclk_table.dpm_levels[j].value,
2093 &arb_regs.entries[i][j]);
2094 if (ret)
2095 break;
2096 }
2097 }
2098
2099 if (ret == 0)
2100 ret = ci_copy_bytes_to_smc(rdev,
2101 pi->arb_table_start,
2102 (u8 *)&arb_regs,
2103 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2104 pi->sram_end);
2105
2106 return ret;
2107 }
2108
ci_program_memory_timing_parameters(struct radeon_device * rdev)2109 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2110 {
2111 struct ci_power_info *pi = ci_get_pi(rdev);
2112
2113 if (pi->need_update_smu7_dpm_table == 0)
2114 return 0;
2115
2116 return ci_do_program_memory_timing_parameters(rdev);
2117 }
2118
ci_populate_smc_initial_state(struct radeon_device * rdev,struct radeon_ps * radeon_boot_state)2119 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2120 struct radeon_ps *radeon_boot_state)
2121 {
2122 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2123 struct ci_power_info *pi = ci_get_pi(rdev);
2124 u32 level = 0;
2125
2126 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2127 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2128 boot_state->performance_levels[0].sclk) {
2129 pi->smc_state_table.GraphicsBootLevel = level;
2130 break;
2131 }
2132 }
2133
2134 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2135 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2136 boot_state->performance_levels[0].mclk) {
2137 pi->smc_state_table.MemoryBootLevel = level;
2138 break;
2139 }
2140 }
2141 }
2142
ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table * dpm_table)2143 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2144 {
2145 u32 i;
2146 u32 mask_value = 0;
2147
2148 for (i = dpm_table->count; i > 0; i--) {
2149 mask_value = mask_value << 1;
2150 if (dpm_table->dpm_levels[i-1].enabled)
2151 mask_value |= 0x1;
2152 else
2153 mask_value &= 0xFFFFFFFE;
2154 }
2155
2156 return mask_value;
2157 }
2158
ci_populate_smc_link_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2159 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2160 SMU7_Discrete_DpmTable *table)
2161 {
2162 struct ci_power_info *pi = ci_get_pi(rdev);
2163 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2164 u32 i;
2165
2166 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2167 table->LinkLevel[i].PcieGenSpeed =
2168 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2169 table->LinkLevel[i].PcieLaneCount =
2170 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2171 table->LinkLevel[i].EnabledForActivity = 1;
2172 table->LinkLevel[i].DownT = cpu_to_be32(5);
2173 table->LinkLevel[i].UpT = cpu_to_be32(30);
2174 }
2175
2176 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2177 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2178 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2179 }
2180
ci_populate_smc_uvd_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2181 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2182 SMU7_Discrete_DpmTable *table)
2183 {
2184 u32 count;
2185 struct atom_clock_dividers dividers;
2186 int ret = -EINVAL;
2187
2188 table->UvdLevelCount =
2189 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2190
2191 for (count = 0; count < table->UvdLevelCount; count++) {
2192 table->UvdLevel[count].VclkFrequency =
2193 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2194 table->UvdLevel[count].DclkFrequency =
2195 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2196 table->UvdLevel[count].MinVddc =
2197 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2198 table->UvdLevel[count].MinVddcPhases = 1;
2199
2200 ret = radeon_atom_get_clock_dividers(rdev,
2201 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2202 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2203 if (ret)
2204 return ret;
2205
2206 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2207
2208 ret = radeon_atom_get_clock_dividers(rdev,
2209 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2210 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2211 if (ret)
2212 return ret;
2213
2214 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2215
2216 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2217 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2218 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2219 }
2220
2221 return ret;
2222 }
2223
ci_populate_smc_vce_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2224 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2225 SMU7_Discrete_DpmTable *table)
2226 {
2227 u32 count;
2228 struct atom_clock_dividers dividers;
2229 int ret = -EINVAL;
2230
2231 table->VceLevelCount =
2232 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2233
2234 for (count = 0; count < table->VceLevelCount; count++) {
2235 table->VceLevel[count].Frequency =
2236 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2237 table->VceLevel[count].MinVoltage =
2238 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2239 table->VceLevel[count].MinPhases = 1;
2240
2241 ret = radeon_atom_get_clock_dividers(rdev,
2242 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2243 table->VceLevel[count].Frequency, false, ÷rs);
2244 if (ret)
2245 return ret;
2246
2247 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2248
2249 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2250 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2251 }
2252
2253 return ret;
2254
2255 }
2256
ci_populate_smc_acp_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2257 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2258 SMU7_Discrete_DpmTable *table)
2259 {
2260 u32 count;
2261 struct atom_clock_dividers dividers;
2262 int ret = -EINVAL;
2263
2264 table->AcpLevelCount = (u8)
2265 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2266
2267 for (count = 0; count < table->AcpLevelCount; count++) {
2268 table->AcpLevel[count].Frequency =
2269 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2270 table->AcpLevel[count].MinVoltage =
2271 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2272 table->AcpLevel[count].MinPhases = 1;
2273
2274 ret = radeon_atom_get_clock_dividers(rdev,
2275 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2276 table->AcpLevel[count].Frequency, false, ÷rs);
2277 if (ret)
2278 return ret;
2279
2280 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2281
2282 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2283 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2284 }
2285
2286 return ret;
2287 }
2288
ci_populate_smc_samu_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2289 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2290 SMU7_Discrete_DpmTable *table)
2291 {
2292 u32 count;
2293 struct atom_clock_dividers dividers;
2294 int ret = -EINVAL;
2295
2296 table->SamuLevelCount =
2297 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2298
2299 for (count = 0; count < table->SamuLevelCount; count++) {
2300 table->SamuLevel[count].Frequency =
2301 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2302 table->SamuLevel[count].MinVoltage =
2303 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2304 table->SamuLevel[count].MinPhases = 1;
2305
2306 ret = radeon_atom_get_clock_dividers(rdev,
2307 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2308 table->SamuLevel[count].Frequency, false, ÷rs);
2309 if (ret)
2310 return ret;
2311
2312 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2313
2314 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2315 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2316 }
2317
2318 return ret;
2319 }
2320
ci_calculate_mclk_params(struct radeon_device * rdev,u32 memory_clock,SMU7_Discrete_MemoryLevel * mclk,bool strobe_mode,bool dll_state_on)2321 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2322 u32 memory_clock,
2323 SMU7_Discrete_MemoryLevel *mclk,
2324 bool strobe_mode,
2325 bool dll_state_on)
2326 {
2327 struct ci_power_info *pi = ci_get_pi(rdev);
2328 u32 dll_cntl = pi->clock_registers.dll_cntl;
2329 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2330 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2331 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2332 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2333 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2334 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2335 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2336 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2337 struct atom_mpll_param mpll_param;
2338 int ret;
2339
2340 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2341 if (ret)
2342 return ret;
2343
2344 mpll_func_cntl &= ~BWCTRL_MASK;
2345 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2346
2347 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2348 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2349 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2350
2351 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2352 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2353
2354 if (pi->mem_gddr5) {
2355 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2356 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2357 YCLK_POST_DIV(mpll_param.post_div);
2358 }
2359
2360 if (pi->caps_mclk_ss_support) {
2361 struct radeon_atom_ss ss;
2362 u32 freq_nom;
2363 u32 tmp;
2364 u32 reference_clock = rdev->clock.mpll.reference_freq;
2365
2366 if (pi->mem_gddr5)
2367 freq_nom = memory_clock * 4;
2368 else
2369 freq_nom = memory_clock * 2;
2370
2371 tmp = (freq_nom / reference_clock);
2372 tmp = tmp * tmp;
2373 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2374 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2375 u32 clks = reference_clock * 5 / ss.rate;
2376 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2377
2378 mpll_ss1 &= ~CLKV_MASK;
2379 mpll_ss1 |= CLKV(clkv);
2380
2381 mpll_ss2 &= ~CLKS_MASK;
2382 mpll_ss2 |= CLKS(clks);
2383 }
2384 }
2385
2386 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2387 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2388
2389 if (dll_state_on)
2390 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2391 else
2392 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2393
2394 mclk->MclkFrequency = memory_clock;
2395 mclk->MpllFuncCntl = mpll_func_cntl;
2396 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2397 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2398 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2399 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2400 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2401 mclk->DllCntl = dll_cntl;
2402 mclk->MpllSs1 = mpll_ss1;
2403 mclk->MpllSs2 = mpll_ss2;
2404
2405 return 0;
2406 }
2407
ci_populate_single_memory_level(struct radeon_device * rdev,u32 memory_clock,SMU7_Discrete_MemoryLevel * memory_level)2408 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2409 u32 memory_clock,
2410 SMU7_Discrete_MemoryLevel *memory_level)
2411 {
2412 struct ci_power_info *pi = ci_get_pi(rdev);
2413 int ret;
2414 bool dll_state_on;
2415
2416 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2417 ret = ci_get_dependency_volt_by_clk(rdev,
2418 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2419 memory_clock, &memory_level->MinVddc);
2420 if (ret)
2421 return ret;
2422 }
2423
2424 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2425 ret = ci_get_dependency_volt_by_clk(rdev,
2426 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2427 memory_clock, &memory_level->MinVddci);
2428 if (ret)
2429 return ret;
2430 }
2431
2432 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2433 ret = ci_get_dependency_volt_by_clk(rdev,
2434 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2435 memory_clock, &memory_level->MinMvdd);
2436 if (ret)
2437 return ret;
2438 }
2439
2440 memory_level->MinVddcPhases = 1;
2441
2442 if (pi->vddc_phase_shed_control)
2443 ci_populate_phase_value_based_on_mclk(rdev,
2444 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2445 memory_clock,
2446 &memory_level->MinVddcPhases);
2447
2448 memory_level->EnabledForThrottle = 1;
2449 memory_level->EnabledForActivity = 1;
2450 memory_level->UpH = 0;
2451 memory_level->DownH = 100;
2452 memory_level->VoltageDownH = 0;
2453 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2454
2455 memory_level->StutterEnable = false;
2456 memory_level->StrobeEnable = false;
2457 memory_level->EdcReadEnable = false;
2458 memory_level->EdcWriteEnable = false;
2459 memory_level->RttEnable = false;
2460
2461 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2462
2463 if (pi->mclk_stutter_mode_threshold &&
2464 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2465 (pi->uvd_enabled == false) &&
2466 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2467 (rdev->pm.dpm.new_active_crtc_count <= 2))
2468 memory_level->StutterEnable = true;
2469
2470 if (pi->mclk_strobe_mode_threshold &&
2471 (memory_clock <= pi->mclk_strobe_mode_threshold))
2472 memory_level->StrobeEnable = 1;
2473
2474 if (pi->mem_gddr5) {
2475 memory_level->StrobeRatio =
2476 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2477 if (pi->mclk_edc_enable_threshold &&
2478 (memory_clock > pi->mclk_edc_enable_threshold))
2479 memory_level->EdcReadEnable = true;
2480
2481 if (pi->mclk_edc_wr_enable_threshold &&
2482 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2483 memory_level->EdcWriteEnable = true;
2484
2485 if (memory_level->StrobeEnable) {
2486 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2487 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2488 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2489 else
2490 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2491 } else {
2492 dll_state_on = pi->dll_default_on;
2493 }
2494 } else {
2495 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2496 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2497 }
2498
2499 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2500 if (ret)
2501 return ret;
2502
2503 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2504 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2505 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2506 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2507
2508 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2509 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2510 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2511 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2512 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2513 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2514 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2515 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2516 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2517 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2518 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2519
2520 return 0;
2521 }
2522
ci_populate_smc_acpi_level(struct radeon_device * rdev,SMU7_Discrete_DpmTable * table)2523 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2524 SMU7_Discrete_DpmTable *table)
2525 {
2526 struct ci_power_info *pi = ci_get_pi(rdev);
2527 struct atom_clock_dividers dividers;
2528 SMU7_Discrete_VoltageLevel voltage_level;
2529 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2530 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2531 u32 dll_cntl = pi->clock_registers.dll_cntl;
2532 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2533 int ret;
2534
2535 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2536
2537 if (pi->acpi_vddc)
2538 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2539 else
2540 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2541
2542 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2543
2544 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2545
2546 ret = radeon_atom_get_clock_dividers(rdev,
2547 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2548 table->ACPILevel.SclkFrequency, false, ÷rs);
2549 if (ret)
2550 return ret;
2551
2552 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2553 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2554 table->ACPILevel.DeepSleepDivId = 0;
2555
2556 spll_func_cntl &= ~SPLL_PWRON;
2557 spll_func_cntl |= SPLL_RESET;
2558
2559 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2560 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2561
2562 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2563 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2564 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2565 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2566 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2567 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2568 table->ACPILevel.CcPwrDynRm = 0;
2569 table->ACPILevel.CcPwrDynRm1 = 0;
2570
2571 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2572 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2573 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2574 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2575 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2576 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2577 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2578 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2579 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2580 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2581 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2582
2583 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2584 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2585
2586 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2587 if (pi->acpi_vddci)
2588 table->MemoryACPILevel.MinVddci =
2589 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2590 else
2591 table->MemoryACPILevel.MinVddci =
2592 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2593 }
2594
2595 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2596 table->MemoryACPILevel.MinMvdd = 0;
2597 else
2598 table->MemoryACPILevel.MinMvdd =
2599 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2600
2601 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2602 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2603
2604 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2605
2606 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2607 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2608 table->MemoryACPILevel.MpllAdFuncCntl =
2609 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2610 table->MemoryACPILevel.MpllDqFuncCntl =
2611 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2612 table->MemoryACPILevel.MpllFuncCntl =
2613 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2614 table->MemoryACPILevel.MpllFuncCntl_1 =
2615 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2616 table->MemoryACPILevel.MpllFuncCntl_2 =
2617 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2618 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2619 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2620
2621 table->MemoryACPILevel.EnabledForThrottle = 0;
2622 table->MemoryACPILevel.EnabledForActivity = 0;
2623 table->MemoryACPILevel.UpH = 0;
2624 table->MemoryACPILevel.DownH = 100;
2625 table->MemoryACPILevel.VoltageDownH = 0;
2626 table->MemoryACPILevel.ActivityLevel =
2627 cpu_to_be16((u16)pi->mclk_activity_target);
2628
2629 table->MemoryACPILevel.StutterEnable = false;
2630 table->MemoryACPILevel.StrobeEnable = false;
2631 table->MemoryACPILevel.EdcReadEnable = false;
2632 table->MemoryACPILevel.EdcWriteEnable = false;
2633 table->MemoryACPILevel.RttEnable = false;
2634
2635 return 0;
2636 }
2637
2638
ci_enable_ulv(struct radeon_device * rdev,bool enable)2639 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2640 {
2641 struct ci_power_info *pi = ci_get_pi(rdev);
2642 struct ci_ulv_parm *ulv = &pi->ulv;
2643
2644 if (ulv->supported) {
2645 if (enable)
2646 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2647 0 : -EINVAL;
2648 else
2649 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2650 0 : -EINVAL;
2651 }
2652
2653 return 0;
2654 }
2655
ci_populate_ulv_level(struct radeon_device * rdev,SMU7_Discrete_Ulv * state)2656 static int ci_populate_ulv_level(struct radeon_device *rdev,
2657 SMU7_Discrete_Ulv *state)
2658 {
2659 struct ci_power_info *pi = ci_get_pi(rdev);
2660 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2661
2662 state->CcPwrDynRm = 0;
2663 state->CcPwrDynRm1 = 0;
2664
2665 if (ulv_voltage == 0) {
2666 pi->ulv.supported = false;
2667 return 0;
2668 }
2669
2670 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2671 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2672 state->VddcOffset = 0;
2673 else
2674 state->VddcOffset =
2675 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2676 } else {
2677 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2678 state->VddcOffsetVid = 0;
2679 else
2680 state->VddcOffsetVid = (u8)
2681 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2682 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2683 }
2684 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2685
2686 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2687 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2688 state->VddcOffset = cpu_to_be16(state->VddcOffset);
2689
2690 return 0;
2691 }
2692
ci_calculate_sclk_params(struct radeon_device * rdev,u32 engine_clock,SMU7_Discrete_GraphicsLevel * sclk)2693 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2694 u32 engine_clock,
2695 SMU7_Discrete_GraphicsLevel *sclk)
2696 {
2697 struct ci_power_info *pi = ci_get_pi(rdev);
2698 struct atom_clock_dividers dividers;
2699 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2700 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2701 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2702 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2703 u32 reference_clock = rdev->clock.spll.reference_freq;
2704 u32 reference_divider;
2705 u32 fbdiv;
2706 int ret;
2707
2708 ret = radeon_atom_get_clock_dividers(rdev,
2709 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2710 engine_clock, false, ÷rs);
2711 if (ret)
2712 return ret;
2713
2714 reference_divider = 1 + dividers.ref_div;
2715 fbdiv = dividers.fb_div & 0x3FFFFFF;
2716
2717 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2718 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2719 spll_func_cntl_3 |= SPLL_DITHEN;
2720
2721 if (pi->caps_sclk_ss_support) {
2722 struct radeon_atom_ss ss;
2723 u32 vco_freq = engine_clock * dividers.post_div;
2724
2725 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2726 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2727 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2728 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2729
2730 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2731 cg_spll_spread_spectrum |= CLK_S(clk_s);
2732 cg_spll_spread_spectrum |= SSEN;
2733
2734 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2735 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2736 }
2737 }
2738
2739 sclk->SclkFrequency = engine_clock;
2740 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2741 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2742 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2743 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2744 sclk->SclkDid = (u8)dividers.post_divider;
2745
2746 return 0;
2747 }
2748
ci_populate_single_graphic_level(struct radeon_device * rdev,u32 engine_clock,u16 sclk_activity_level_t,SMU7_Discrete_GraphicsLevel * graphic_level)2749 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2750 u32 engine_clock,
2751 u16 sclk_activity_level_t,
2752 SMU7_Discrete_GraphicsLevel *graphic_level)
2753 {
2754 struct ci_power_info *pi = ci_get_pi(rdev);
2755 int ret;
2756
2757 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2758 if (ret)
2759 return ret;
2760
2761 ret = ci_get_dependency_volt_by_clk(rdev,
2762 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2763 engine_clock, &graphic_level->MinVddc);
2764 if (ret)
2765 return ret;
2766
2767 graphic_level->SclkFrequency = engine_clock;
2768
2769 graphic_level->Flags = 0;
2770 graphic_level->MinVddcPhases = 1;
2771
2772 if (pi->vddc_phase_shed_control)
2773 ci_populate_phase_value_based_on_sclk(rdev,
2774 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2775 engine_clock,
2776 &graphic_level->MinVddcPhases);
2777
2778 graphic_level->ActivityLevel = sclk_activity_level_t;
2779
2780 graphic_level->CcPwrDynRm = 0;
2781 graphic_level->CcPwrDynRm1 = 0;
2782 graphic_level->EnabledForActivity = 1;
2783 graphic_level->EnabledForThrottle = 1;
2784 graphic_level->UpH = 0;
2785 graphic_level->DownH = 0;
2786 graphic_level->VoltageDownH = 0;
2787 graphic_level->PowerThrottle = 0;
2788
2789 if (pi->caps_sclk_ds)
2790 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2791 engine_clock,
2792 CISLAND_MINIMUM_ENGINE_CLOCK);
2793
2794 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2795
2796 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2797 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2798 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2799 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2800 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2801 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2802 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2803 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2804 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2805 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2806 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2807
2808 return 0;
2809 }
2810
ci_populate_all_graphic_levels(struct radeon_device * rdev)2811 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2812 {
2813 struct ci_power_info *pi = ci_get_pi(rdev);
2814 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2815 u32 level_array_address = pi->dpm_table_start +
2816 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2817 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2818 SMU7_MAX_LEVELS_GRAPHICS;
2819 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2820 u32 i, ret;
2821
2822 memset(levels, 0, level_array_size);
2823
2824 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2825 ret = ci_populate_single_graphic_level(rdev,
2826 dpm_table->sclk_table.dpm_levels[i].value,
2827 (u16)pi->activity_target[i],
2828 &pi->smc_state_table.GraphicsLevel[i]);
2829 if (ret)
2830 return ret;
2831 if (i == (dpm_table->sclk_table.count - 1))
2832 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2833 PPSMC_DISPLAY_WATERMARK_HIGH;
2834 }
2835
2836 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2837 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2838 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2839
2840 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2841 (u8 *)levels, level_array_size,
2842 pi->sram_end);
2843 if (ret)
2844 return ret;
2845
2846 return 0;
2847 }
2848
ci_populate_ulv_state(struct radeon_device * rdev,SMU7_Discrete_Ulv * ulv_level)2849 static int ci_populate_ulv_state(struct radeon_device *rdev,
2850 SMU7_Discrete_Ulv *ulv_level)
2851 {
2852 return ci_populate_ulv_level(rdev, ulv_level);
2853 }
2854
ci_populate_all_memory_levels(struct radeon_device * rdev)2855 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2856 {
2857 struct ci_power_info *pi = ci_get_pi(rdev);
2858 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2859 u32 level_array_address = pi->dpm_table_start +
2860 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2861 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2862 SMU7_MAX_LEVELS_MEMORY;
2863 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2864 u32 i, ret;
2865
2866 memset(levels, 0, level_array_size);
2867
2868 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2869 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2870 return -EINVAL;
2871 ret = ci_populate_single_memory_level(rdev,
2872 dpm_table->mclk_table.dpm_levels[i].value,
2873 &pi->smc_state_table.MemoryLevel[i]);
2874 if (ret)
2875 return ret;
2876 }
2877
2878 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2879
2880 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2881 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2882 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2883
2884 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2885 PPSMC_DISPLAY_WATERMARK_HIGH;
2886
2887 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2888 (u8 *)levels, level_array_size,
2889 pi->sram_end);
2890 if (ret)
2891 return ret;
2892
2893 return 0;
2894 }
2895
ci_reset_single_dpm_table(struct radeon_device * rdev,struct ci_single_dpm_table * dpm_table,u32 count)2896 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2897 struct ci_single_dpm_table* dpm_table,
2898 u32 count)
2899 {
2900 u32 i;
2901
2902 dpm_table->count = count;
2903 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2904 dpm_table->dpm_levels[i].enabled = false;
2905 }
2906
ci_setup_pcie_table_entry(struct ci_single_dpm_table * dpm_table,u32 index,u32 pcie_gen,u32 pcie_lanes)2907 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2908 u32 index, u32 pcie_gen, u32 pcie_lanes)
2909 {
2910 dpm_table->dpm_levels[index].value = pcie_gen;
2911 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2912 dpm_table->dpm_levels[index].enabled = true;
2913 }
2914
ci_setup_default_pcie_tables(struct radeon_device * rdev)2915 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2916 {
2917 struct ci_power_info *pi = ci_get_pi(rdev);
2918
2919 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2920 return -EINVAL;
2921
2922 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2923 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2924 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2925 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2926 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2927 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2928 }
2929
2930 ci_reset_single_dpm_table(rdev,
2931 &pi->dpm_table.pcie_speed_table,
2932 SMU7_MAX_LEVELS_LINK);
2933
2934 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2935 pi->pcie_gen_powersaving.min,
2936 pi->pcie_lane_powersaving.min);
2937 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2938 pi->pcie_gen_performance.min,
2939 pi->pcie_lane_performance.min);
2940 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2941 pi->pcie_gen_powersaving.min,
2942 pi->pcie_lane_powersaving.max);
2943 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2944 pi->pcie_gen_performance.min,
2945 pi->pcie_lane_performance.max);
2946 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2947 pi->pcie_gen_powersaving.max,
2948 pi->pcie_lane_powersaving.max);
2949 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2950 pi->pcie_gen_performance.max,
2951 pi->pcie_lane_performance.max);
2952
2953 pi->dpm_table.pcie_speed_table.count = 6;
2954
2955 return 0;
2956 }
2957
ci_setup_default_dpm_tables(struct radeon_device * rdev)2958 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2959 {
2960 struct ci_power_info *pi = ci_get_pi(rdev);
2961 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2962 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2963 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2964 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2965 struct radeon_cac_leakage_table *std_voltage_table =
2966 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2967 u32 i;
2968
2969 if (allowed_sclk_vddc_table == NULL)
2970 return -EINVAL;
2971 if (allowed_sclk_vddc_table->count < 1)
2972 return -EINVAL;
2973 if (allowed_mclk_table == NULL)
2974 return -EINVAL;
2975 if (allowed_mclk_table->count < 1)
2976 return -EINVAL;
2977
2978 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2979
2980 ci_reset_single_dpm_table(rdev,
2981 &pi->dpm_table.sclk_table,
2982 SMU7_MAX_LEVELS_GRAPHICS);
2983 ci_reset_single_dpm_table(rdev,
2984 &pi->dpm_table.mclk_table,
2985 SMU7_MAX_LEVELS_MEMORY);
2986 ci_reset_single_dpm_table(rdev,
2987 &pi->dpm_table.vddc_table,
2988 SMU7_MAX_LEVELS_VDDC);
2989 ci_reset_single_dpm_table(rdev,
2990 &pi->dpm_table.vddci_table,
2991 SMU7_MAX_LEVELS_VDDCI);
2992 ci_reset_single_dpm_table(rdev,
2993 &pi->dpm_table.mvdd_table,
2994 SMU7_MAX_LEVELS_MVDD);
2995
2996 pi->dpm_table.sclk_table.count = 0;
2997 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2998 if ((i == 0) ||
2999 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3000 allowed_sclk_vddc_table->entries[i].clk)) {
3001 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3002 allowed_sclk_vddc_table->entries[i].clk;
3003 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3004 pi->dpm_table.sclk_table.count++;
3005 }
3006 }
3007
3008 pi->dpm_table.mclk_table.count = 0;
3009 for (i = 0; i < allowed_mclk_table->count; i++) {
3010 if ((i==0) ||
3011 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3012 allowed_mclk_table->entries[i].clk)) {
3013 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3014 allowed_mclk_table->entries[i].clk;
3015 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3016 pi->dpm_table.mclk_table.count++;
3017 }
3018 }
3019
3020 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3021 pi->dpm_table.vddc_table.dpm_levels[i].value =
3022 allowed_sclk_vddc_table->entries[i].v;
3023 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3024 std_voltage_table->entries[i].leakage;
3025 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3026 }
3027 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3028
3029 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3030 if (allowed_mclk_table) {
3031 for (i = 0; i < allowed_mclk_table->count; i++) {
3032 pi->dpm_table.vddci_table.dpm_levels[i].value =
3033 allowed_mclk_table->entries[i].v;
3034 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3035 }
3036 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3037 }
3038
3039 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3040 if (allowed_mclk_table) {
3041 for (i = 0; i < allowed_mclk_table->count; i++) {
3042 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3043 allowed_mclk_table->entries[i].v;
3044 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3045 }
3046 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3047 }
3048
3049 ci_setup_default_pcie_tables(rdev);
3050
3051 return 0;
3052 }
3053
ci_find_boot_level(struct ci_single_dpm_table * table,u32 value,u32 * boot_level)3054 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3055 u32 value, u32 *boot_level)
3056 {
3057 u32 i;
3058 int ret = -EINVAL;
3059
3060 for(i = 0; i < table->count; i++) {
3061 if (value == table->dpm_levels[i].value) {
3062 *boot_level = i;
3063 ret = 0;
3064 }
3065 }
3066
3067 return ret;
3068 }
3069
ci_init_smc_table(struct radeon_device * rdev)3070 static int ci_init_smc_table(struct radeon_device *rdev)
3071 {
3072 struct ci_power_info *pi = ci_get_pi(rdev);
3073 struct ci_ulv_parm *ulv = &pi->ulv;
3074 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3075 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3076 int ret;
3077
3078 ret = ci_setup_default_dpm_tables(rdev);
3079 if (ret)
3080 return ret;
3081
3082 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3083 ci_populate_smc_voltage_tables(rdev, table);
3084
3085 ci_init_fps_limits(rdev);
3086
3087 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3088 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3089
3090 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3091 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3092
3093 if (pi->mem_gddr5)
3094 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3095
3096 if (ulv->supported) {
3097 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3098 if (ret)
3099 return ret;
3100 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3101 }
3102
3103 ret = ci_populate_all_graphic_levels(rdev);
3104 if (ret)
3105 return ret;
3106
3107 ret = ci_populate_all_memory_levels(rdev);
3108 if (ret)
3109 return ret;
3110
3111 ci_populate_smc_link_level(rdev, table);
3112
3113 ret = ci_populate_smc_acpi_level(rdev, table);
3114 if (ret)
3115 return ret;
3116
3117 ret = ci_populate_smc_vce_level(rdev, table);
3118 if (ret)
3119 return ret;
3120
3121 ret = ci_populate_smc_acp_level(rdev, table);
3122 if (ret)
3123 return ret;
3124
3125 ret = ci_populate_smc_samu_level(rdev, table);
3126 if (ret)
3127 return ret;
3128
3129 ret = ci_do_program_memory_timing_parameters(rdev);
3130 if (ret)
3131 return ret;
3132
3133 ret = ci_populate_smc_uvd_level(rdev, table);
3134 if (ret)
3135 return ret;
3136
3137 table->UvdBootLevel = 0;
3138 table->VceBootLevel = 0;
3139 table->AcpBootLevel = 0;
3140 table->SamuBootLevel = 0;
3141 table->GraphicsBootLevel = 0;
3142 table->MemoryBootLevel = 0;
3143
3144 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3145 pi->vbios_boot_state.sclk_bootup_value,
3146 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3147
3148 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3149 pi->vbios_boot_state.mclk_bootup_value,
3150 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3151
3152 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3153 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3154 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3155
3156 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3157
3158 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3159 if (ret)
3160 return ret;
3161
3162 table->UVDInterval = 1;
3163 table->VCEInterval = 1;
3164 table->ACPInterval = 1;
3165 table->SAMUInterval = 1;
3166 table->GraphicsVoltageChangeEnable = 1;
3167 table->GraphicsThermThrottleEnable = 1;
3168 table->GraphicsInterval = 1;
3169 table->VoltageInterval = 1;
3170 table->ThermalInterval = 1;
3171 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3172 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3173 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3174 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3175 table->MemoryVoltageChangeEnable = 1;
3176 table->MemoryInterval = 1;
3177 table->VoltageResponseTime = 0;
3178 table->VddcVddciDelta = 4000;
3179 table->PhaseResponseTime = 0;
3180 table->MemoryThermThrottleEnable = 1;
3181 table->PCIeBootLinkLevel = 0;
3182 table->PCIeGenInterval = 1;
3183 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3184 table->SVI2Enable = 1;
3185 else
3186 table->SVI2Enable = 0;
3187
3188 table->ThermGpio = 17;
3189 table->SclkStepSize = 0x4000;
3190
3191 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3192 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3193 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3194 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3195 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3196 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3197 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3198 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3199 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3200 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3201 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3202 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3203 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3204 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3205
3206 ret = ci_copy_bytes_to_smc(rdev,
3207 pi->dpm_table_start +
3208 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3209 (u8 *)&table->SystemFlags,
3210 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3211 pi->sram_end);
3212 if (ret)
3213 return ret;
3214
3215 return 0;
3216 }
3217
ci_trim_single_dpm_states(struct radeon_device * rdev,struct ci_single_dpm_table * dpm_table,u32 low_limit,u32 high_limit)3218 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3219 struct ci_single_dpm_table *dpm_table,
3220 u32 low_limit, u32 high_limit)
3221 {
3222 u32 i;
3223
3224 for (i = 0; i < dpm_table->count; i++) {
3225 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3226 (dpm_table->dpm_levels[i].value > high_limit))
3227 dpm_table->dpm_levels[i].enabled = false;
3228 else
3229 dpm_table->dpm_levels[i].enabled = true;
3230 }
3231 }
3232
ci_trim_pcie_dpm_states(struct radeon_device * rdev,u32 speed_low,u32 lanes_low,u32 speed_high,u32 lanes_high)3233 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3234 u32 speed_low, u32 lanes_low,
3235 u32 speed_high, u32 lanes_high)
3236 {
3237 struct ci_power_info *pi = ci_get_pi(rdev);
3238 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3239 u32 i, j;
3240
3241 for (i = 0; i < pcie_table->count; i++) {
3242 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3243 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3244 (pcie_table->dpm_levels[i].value > speed_high) ||
3245 (pcie_table->dpm_levels[i].param1 > lanes_high))
3246 pcie_table->dpm_levels[i].enabled = false;
3247 else
3248 pcie_table->dpm_levels[i].enabled = true;
3249 }
3250
3251 for (i = 0; i < pcie_table->count; i++) {
3252 if (pcie_table->dpm_levels[i].enabled) {
3253 for (j = i + 1; j < pcie_table->count; j++) {
3254 if (pcie_table->dpm_levels[j].enabled) {
3255 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3256 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3257 pcie_table->dpm_levels[j].enabled = false;
3258 }
3259 }
3260 }
3261 }
3262 }
3263
ci_trim_dpm_states(struct radeon_device * rdev,struct radeon_ps * radeon_state)3264 static int ci_trim_dpm_states(struct radeon_device *rdev,
3265 struct radeon_ps *radeon_state)
3266 {
3267 struct ci_ps *state = ci_get_ps(radeon_state);
3268 struct ci_power_info *pi = ci_get_pi(rdev);
3269 u32 high_limit_count;
3270
3271 if (state->performance_level_count < 1)
3272 return -EINVAL;
3273
3274 if (state->performance_level_count == 1)
3275 high_limit_count = 0;
3276 else
3277 high_limit_count = 1;
3278
3279 ci_trim_single_dpm_states(rdev,
3280 &pi->dpm_table.sclk_table,
3281 state->performance_levels[0].sclk,
3282 state->performance_levels[high_limit_count].sclk);
3283
3284 ci_trim_single_dpm_states(rdev,
3285 &pi->dpm_table.mclk_table,
3286 state->performance_levels[0].mclk,
3287 state->performance_levels[high_limit_count].mclk);
3288
3289 ci_trim_pcie_dpm_states(rdev,
3290 state->performance_levels[0].pcie_gen,
3291 state->performance_levels[0].pcie_lane,
3292 state->performance_levels[high_limit_count].pcie_gen,
3293 state->performance_levels[high_limit_count].pcie_lane);
3294
3295 return 0;
3296 }
3297
ci_apply_disp_minimum_voltage_request(struct radeon_device * rdev)3298 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3299 {
3300 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3301 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3302 struct radeon_clock_voltage_dependency_table *vddc_table =
3303 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3304 u32 requested_voltage = 0;
3305 u32 i;
3306
3307 if (disp_voltage_table == NULL)
3308 return -EINVAL;
3309 if (!disp_voltage_table->count)
3310 return -EINVAL;
3311
3312 for (i = 0; i < disp_voltage_table->count; i++) {
3313 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3314 requested_voltage = disp_voltage_table->entries[i].v;
3315 }
3316
3317 for (i = 0; i < vddc_table->count; i++) {
3318 if (requested_voltage <= vddc_table->entries[i].v) {
3319 requested_voltage = vddc_table->entries[i].v;
3320 return (ci_send_msg_to_smc_with_parameter(rdev,
3321 PPSMC_MSG_VddC_Request,
3322 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3323 0 : -EINVAL;
3324 }
3325 }
3326
3327 return -EINVAL;
3328 }
3329
ci_upload_dpm_level_enable_mask(struct radeon_device * rdev)3330 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3331 {
3332 struct ci_power_info *pi = ci_get_pi(rdev);
3333 PPSMC_Result result;
3334
3335 if (!pi->sclk_dpm_key_disabled) {
3336 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3337 result = ci_send_msg_to_smc_with_parameter(rdev,
3338 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3339 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3340 if (result != PPSMC_Result_OK)
3341 return -EINVAL;
3342 }
3343 }
3344
3345 if (!pi->mclk_dpm_key_disabled) {
3346 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3347 result = ci_send_msg_to_smc_with_parameter(rdev,
3348 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3349 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3350 if (result != PPSMC_Result_OK)
3351 return -EINVAL;
3352 }
3353 }
3354
3355 if (!pi->pcie_dpm_key_disabled) {
3356 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3357 result = ci_send_msg_to_smc_with_parameter(rdev,
3358 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3359 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3360 if (result != PPSMC_Result_OK)
3361 return -EINVAL;
3362 }
3363 }
3364
3365 ci_apply_disp_minimum_voltage_request(rdev);
3366
3367 return 0;
3368 }
3369
ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device * rdev,struct radeon_ps * radeon_state)3370 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3371 struct radeon_ps *radeon_state)
3372 {
3373 struct ci_power_info *pi = ci_get_pi(rdev);
3374 struct ci_ps *state = ci_get_ps(radeon_state);
3375 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3376 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3377 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3378 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3379 u32 i;
3380
3381 pi->need_update_smu7_dpm_table = 0;
3382
3383 for (i = 0; i < sclk_table->count; i++) {
3384 if (sclk == sclk_table->dpm_levels[i].value)
3385 break;
3386 }
3387
3388 if (i >= sclk_table->count) {
3389 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3390 } else {
3391 /* XXX check display min clock requirements */
3392 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3393 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3394 }
3395
3396 for (i = 0; i < mclk_table->count; i++) {
3397 if (mclk == mclk_table->dpm_levels[i].value)
3398 break;
3399 }
3400
3401 if (i >= mclk_table->count)
3402 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3403
3404 if (rdev->pm.dpm.current_active_crtc_count !=
3405 rdev->pm.dpm.new_active_crtc_count)
3406 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3407 }
3408
ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device * rdev,struct radeon_ps * radeon_state)3409 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3410 struct radeon_ps *radeon_state)
3411 {
3412 struct ci_power_info *pi = ci_get_pi(rdev);
3413 struct ci_ps *state = ci_get_ps(radeon_state);
3414 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3415 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3416 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3417 int ret;
3418
3419 if (!pi->need_update_smu7_dpm_table)
3420 return 0;
3421
3422 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3423 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3424
3425 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3426 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3427
3428 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3429 ret = ci_populate_all_graphic_levels(rdev);
3430 if (ret)
3431 return ret;
3432 }
3433
3434 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3435 ret = ci_populate_all_memory_levels(rdev);
3436 if (ret)
3437 return ret;
3438 }
3439
3440 return 0;
3441 }
3442
ci_enable_uvd_dpm(struct radeon_device * rdev,bool enable)3443 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3444 {
3445 struct ci_power_info *pi = ci_get_pi(rdev);
3446 const struct radeon_clock_and_voltage_limits *max_limits;
3447 int i;
3448
3449 if (rdev->pm.dpm.ac_power)
3450 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3451 else
3452 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3453
3454 if (enable) {
3455 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3456
3457 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3458 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3459 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3460
3461 if (!pi->caps_uvd_dpm)
3462 break;
3463 }
3464 }
3465
3466 ci_send_msg_to_smc_with_parameter(rdev,
3467 PPSMC_MSG_UVDDPM_SetEnabledMask,
3468 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3469
3470 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3471 pi->uvd_enabled = true;
3472 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3473 ci_send_msg_to_smc_with_parameter(rdev,
3474 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3475 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3476 }
3477 } else {
3478 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3479 pi->uvd_enabled = false;
3480 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3481 ci_send_msg_to_smc_with_parameter(rdev,
3482 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3483 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3484 }
3485 }
3486
3487 return (ci_send_msg_to_smc(rdev, enable ?
3488 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3489 0 : -EINVAL;
3490 }
3491
ci_enable_vce_dpm(struct radeon_device * rdev,bool enable)3492 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3493 {
3494 struct ci_power_info *pi = ci_get_pi(rdev);
3495 const struct radeon_clock_and_voltage_limits *max_limits;
3496 int i;
3497
3498 if (rdev->pm.dpm.ac_power)
3499 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3500 else
3501 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3502
3503 if (enable) {
3504 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3505 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3506 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3507 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3508
3509 if (!pi->caps_vce_dpm)
3510 break;
3511 }
3512 }
3513
3514 ci_send_msg_to_smc_with_parameter(rdev,
3515 PPSMC_MSG_VCEDPM_SetEnabledMask,
3516 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3517 }
3518
3519 return (ci_send_msg_to_smc(rdev, enable ?
3520 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3521 0 : -EINVAL;
3522 }
3523
3524 #if 0
3525 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3526 {
3527 struct ci_power_info *pi = ci_get_pi(rdev);
3528 const struct radeon_clock_and_voltage_limits *max_limits;
3529 int i;
3530
3531 if (rdev->pm.dpm.ac_power)
3532 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3533 else
3534 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3535
3536 if (enable) {
3537 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3538 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3539 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3540 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3541
3542 if (!pi->caps_samu_dpm)
3543 break;
3544 }
3545 }
3546
3547 ci_send_msg_to_smc_with_parameter(rdev,
3548 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3549 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3550 }
3551 return (ci_send_msg_to_smc(rdev, enable ?
3552 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3553 0 : -EINVAL;
3554 }
3555
3556 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3557 {
3558 struct ci_power_info *pi = ci_get_pi(rdev);
3559 const struct radeon_clock_and_voltage_limits *max_limits;
3560 int i;
3561
3562 if (rdev->pm.dpm.ac_power)
3563 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3564 else
3565 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3566
3567 if (enable) {
3568 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3569 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3570 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3571 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3572
3573 if (!pi->caps_acp_dpm)
3574 break;
3575 }
3576 }
3577
3578 ci_send_msg_to_smc_with_parameter(rdev,
3579 PPSMC_MSG_ACPDPM_SetEnabledMask,
3580 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3581 }
3582
3583 return (ci_send_msg_to_smc(rdev, enable ?
3584 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3585 0 : -EINVAL;
3586 }
3587 #endif
3588
ci_update_uvd_dpm(struct radeon_device * rdev,bool gate)3589 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3590 {
3591 struct ci_power_info *pi = ci_get_pi(rdev);
3592 u32 tmp;
3593
3594 if (!gate) {
3595 if (pi->caps_uvd_dpm ||
3596 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3597 pi->smc_state_table.UvdBootLevel = 0;
3598 else
3599 pi->smc_state_table.UvdBootLevel =
3600 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3601
3602 tmp = RREG32_SMC(DPM_TABLE_475);
3603 tmp &= ~UvdBootLevel_MASK;
3604 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3605 WREG32_SMC(DPM_TABLE_475, tmp);
3606 }
3607
3608 return ci_enable_uvd_dpm(rdev, !gate);
3609 }
3610
ci_get_vce_boot_level(struct radeon_device * rdev)3611 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3612 {
3613 u8 i;
3614 u32 min_evclk = 30000; /* ??? */
3615 struct radeon_vce_clock_voltage_dependency_table *table =
3616 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3617
3618 for (i = 0; i < table->count; i++) {
3619 if (table->entries[i].evclk >= min_evclk)
3620 return i;
3621 }
3622
3623 return table->count - 1;
3624 }
3625
ci_update_vce_dpm(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)3626 static int ci_update_vce_dpm(struct radeon_device *rdev,
3627 struct radeon_ps *radeon_new_state,
3628 struct radeon_ps *radeon_current_state)
3629 {
3630 struct ci_power_info *pi = ci_get_pi(rdev);
3631 int ret = 0;
3632 u32 tmp;
3633
3634 if (radeon_current_state->evclk != radeon_new_state->evclk) {
3635 if (radeon_new_state->evclk) {
3636 /* turn the clocks on when encoding */
3637 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3638
3639 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3640 tmp = RREG32_SMC(DPM_TABLE_475);
3641 tmp &= ~VceBootLevel_MASK;
3642 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3643 WREG32_SMC(DPM_TABLE_475, tmp);
3644
3645 ret = ci_enable_vce_dpm(rdev, true);
3646 } else {
3647 /* turn the clocks off when not encoding */
3648 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3649
3650 ret = ci_enable_vce_dpm(rdev, false);
3651 }
3652 }
3653 return ret;
3654 }
3655
3656 #if 0
3657 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3658 {
3659 return ci_enable_samu_dpm(rdev, gate);
3660 }
3661
3662 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3663 {
3664 struct ci_power_info *pi = ci_get_pi(rdev);
3665 u32 tmp;
3666
3667 if (!gate) {
3668 pi->smc_state_table.AcpBootLevel = 0;
3669
3670 tmp = RREG32_SMC(DPM_TABLE_475);
3671 tmp &= ~AcpBootLevel_MASK;
3672 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3673 WREG32_SMC(DPM_TABLE_475, tmp);
3674 }
3675
3676 return ci_enable_acp_dpm(rdev, !gate);
3677 }
3678 #endif
3679
ci_generate_dpm_level_enable_mask(struct radeon_device * rdev,struct radeon_ps * radeon_state)3680 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3681 struct radeon_ps *radeon_state)
3682 {
3683 struct ci_power_info *pi = ci_get_pi(rdev);
3684 int ret;
3685
3686 ret = ci_trim_dpm_states(rdev, radeon_state);
3687 if (ret)
3688 return ret;
3689
3690 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3691 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3692 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3693 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3694 pi->last_mclk_dpm_enable_mask =
3695 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3696 if (pi->uvd_enabled) {
3697 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3698 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3699 }
3700 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3701 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3702
3703 return 0;
3704 }
3705
ci_get_lowest_enabled_level(struct radeon_device * rdev,u32 level_mask)3706 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3707 u32 level_mask)
3708 {
3709 u32 level = 0;
3710
3711 while ((level_mask & (1 << level)) == 0)
3712 level++;
3713
3714 return level;
3715 }
3716
3717
ci_dpm_force_performance_level(struct radeon_device * rdev,enum radeon_dpm_forced_level level)3718 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3719 enum radeon_dpm_forced_level level)
3720 {
3721 struct ci_power_info *pi = ci_get_pi(rdev);
3722 PPSMC_Result smc_result;
3723 u32 tmp, levels, i;
3724 int ret;
3725
3726 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3727 if ((!pi->sclk_dpm_key_disabled) &&
3728 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3729 levels = 0;
3730 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3731 while (tmp >>= 1)
3732 levels++;
3733 if (levels) {
3734 ret = ci_dpm_force_state_sclk(rdev, levels);
3735 if (ret)
3736 return ret;
3737 for (i = 0; i < rdev->usec_timeout; i++) {
3738 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3739 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3740 if (tmp == levels)
3741 break;
3742 udelay(1);
3743 }
3744 }
3745 }
3746 if ((!pi->mclk_dpm_key_disabled) &&
3747 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3748 levels = 0;
3749 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3750 while (tmp >>= 1)
3751 levels++;
3752 if (levels) {
3753 ret = ci_dpm_force_state_mclk(rdev, levels);
3754 if (ret)
3755 return ret;
3756 for (i = 0; i < rdev->usec_timeout; i++) {
3757 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3758 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3759 if (tmp == levels)
3760 break;
3761 udelay(1);
3762 }
3763 }
3764 }
3765 if ((!pi->pcie_dpm_key_disabled) &&
3766 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3767 levels = 0;
3768 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3769 while (tmp >>= 1)
3770 levels++;
3771 if (levels) {
3772 ret = ci_dpm_force_state_pcie(rdev, level);
3773 if (ret)
3774 return ret;
3775 for (i = 0; i < rdev->usec_timeout; i++) {
3776 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3777 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3778 if (tmp == levels)
3779 break;
3780 udelay(1);
3781 }
3782 }
3783 }
3784 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3785 if ((!pi->sclk_dpm_key_disabled) &&
3786 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3787 levels = ci_get_lowest_enabled_level(rdev,
3788 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3789 ret = ci_dpm_force_state_sclk(rdev, levels);
3790 if (ret)
3791 return ret;
3792 for (i = 0; i < rdev->usec_timeout; i++) {
3793 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3794 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3795 if (tmp == levels)
3796 break;
3797 udelay(1);
3798 }
3799 }
3800 if ((!pi->mclk_dpm_key_disabled) &&
3801 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3802 levels = ci_get_lowest_enabled_level(rdev,
3803 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3804 ret = ci_dpm_force_state_mclk(rdev, levels);
3805 if (ret)
3806 return ret;
3807 for (i = 0; i < rdev->usec_timeout; i++) {
3808 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3809 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3810 if (tmp == levels)
3811 break;
3812 udelay(1);
3813 }
3814 }
3815 if ((!pi->pcie_dpm_key_disabled) &&
3816 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3817 levels = ci_get_lowest_enabled_level(rdev,
3818 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3819 ret = ci_dpm_force_state_pcie(rdev, levels);
3820 if (ret)
3821 return ret;
3822 for (i = 0; i < rdev->usec_timeout; i++) {
3823 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3824 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3825 if (tmp == levels)
3826 break;
3827 udelay(1);
3828 }
3829 }
3830 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3831 if (!pi->sclk_dpm_key_disabled) {
3832 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3833 if (smc_result != PPSMC_Result_OK)
3834 return -EINVAL;
3835 }
3836 if (!pi->mclk_dpm_key_disabled) {
3837 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3838 if (smc_result != PPSMC_Result_OK)
3839 return -EINVAL;
3840 }
3841 if (!pi->pcie_dpm_key_disabled) {
3842 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3843 if (smc_result != PPSMC_Result_OK)
3844 return -EINVAL;
3845 }
3846 }
3847
3848 rdev->pm.dpm.forced_level = level;
3849
3850 return 0;
3851 }
3852
ci_set_mc_special_registers(struct radeon_device * rdev,struct ci_mc_reg_table * table)3853 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3854 struct ci_mc_reg_table *table)
3855 {
3856 struct ci_power_info *pi = ci_get_pi(rdev);
3857 u8 i, j, k;
3858 u32 temp_reg;
3859
3860 for (i = 0, j = table->last; i < table->last; i++) {
3861 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3862 return -EINVAL;
3863 switch(table->mc_reg_address[i].s1 << 2) {
3864 case MC_SEQ_MISC1:
3865 temp_reg = RREG32(MC_PMG_CMD_EMRS);
3866 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3867 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3868 for (k = 0; k < table->num_entries; k++) {
3869 table->mc_reg_table_entry[k].mc_data[j] =
3870 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3871 }
3872 j++;
3873 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3874 return -EINVAL;
3875
3876 temp_reg = RREG32(MC_PMG_CMD_MRS);
3877 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3878 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3879 for (k = 0; k < table->num_entries; k++) {
3880 table->mc_reg_table_entry[k].mc_data[j] =
3881 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3882 if (!pi->mem_gddr5)
3883 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3884 }
3885 j++;
3886 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3887 return -EINVAL;
3888
3889 if (!pi->mem_gddr5) {
3890 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3891 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3892 for (k = 0; k < table->num_entries; k++) {
3893 table->mc_reg_table_entry[k].mc_data[j] =
3894 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3895 }
3896 j++;
3897 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3898 return -EINVAL;
3899 }
3900 break;
3901 case MC_SEQ_RESERVE_M:
3902 temp_reg = RREG32(MC_PMG_CMD_MRS1);
3903 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3904 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3905 for (k = 0; k < table->num_entries; k++) {
3906 table->mc_reg_table_entry[k].mc_data[j] =
3907 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3908 }
3909 j++;
3910 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3911 return -EINVAL;
3912 break;
3913 default:
3914 break;
3915 }
3916
3917 }
3918
3919 table->last = j;
3920
3921 return 0;
3922 }
3923
ci_check_s0_mc_reg_index(u16 in_reg,u16 * out_reg)3924 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3925 {
3926 bool result = true;
3927
3928 switch(in_reg) {
3929 case MC_SEQ_RAS_TIMING >> 2:
3930 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3931 break;
3932 case MC_SEQ_DLL_STBY >> 2:
3933 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3934 break;
3935 case MC_SEQ_G5PDX_CMD0 >> 2:
3936 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3937 break;
3938 case MC_SEQ_G5PDX_CMD1 >> 2:
3939 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3940 break;
3941 case MC_SEQ_G5PDX_CTRL >> 2:
3942 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3943 break;
3944 case MC_SEQ_CAS_TIMING >> 2:
3945 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3946 break;
3947 case MC_SEQ_MISC_TIMING >> 2:
3948 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3949 break;
3950 case MC_SEQ_MISC_TIMING2 >> 2:
3951 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3952 break;
3953 case MC_SEQ_PMG_DVS_CMD >> 2:
3954 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3955 break;
3956 case MC_SEQ_PMG_DVS_CTL >> 2:
3957 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3958 break;
3959 case MC_SEQ_RD_CTL_D0 >> 2:
3960 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3961 break;
3962 case MC_SEQ_RD_CTL_D1 >> 2:
3963 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3964 break;
3965 case MC_SEQ_WR_CTL_D0 >> 2:
3966 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3967 break;
3968 case MC_SEQ_WR_CTL_D1 >> 2:
3969 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3970 break;
3971 case MC_PMG_CMD_EMRS >> 2:
3972 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3973 break;
3974 case MC_PMG_CMD_MRS >> 2:
3975 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3976 break;
3977 case MC_PMG_CMD_MRS1 >> 2:
3978 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3979 break;
3980 case MC_SEQ_PMG_TIMING >> 2:
3981 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3982 break;
3983 case MC_PMG_CMD_MRS2 >> 2:
3984 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3985 break;
3986 case MC_SEQ_WR_CTL_2 >> 2:
3987 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3988 break;
3989 default:
3990 result = false;
3991 break;
3992 }
3993
3994 return result;
3995 }
3996
ci_set_valid_flag(struct ci_mc_reg_table * table)3997 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
3998 {
3999 u8 i, j;
4000
4001 for (i = 0; i < table->last; i++) {
4002 for (j = 1; j < table->num_entries; j++) {
4003 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4004 table->mc_reg_table_entry[j].mc_data[i]) {
4005 table->valid_flag |= 1 << i;
4006 break;
4007 }
4008 }
4009 }
4010 }
4011
ci_set_s0_mc_reg_index(struct ci_mc_reg_table * table)4012 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4013 {
4014 u32 i;
4015 u16 address;
4016
4017 for (i = 0; i < table->last; i++) {
4018 table->mc_reg_address[i].s0 =
4019 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4020 address : table->mc_reg_address[i].s1;
4021 }
4022 }
4023
ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table * table,struct ci_mc_reg_table * ci_table)4024 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4025 struct ci_mc_reg_table *ci_table)
4026 {
4027 u8 i, j;
4028
4029 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4030 return -EINVAL;
4031 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4032 return -EINVAL;
4033
4034 for (i = 0; i < table->last; i++)
4035 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4036
4037 ci_table->last = table->last;
4038
4039 for (i = 0; i < table->num_entries; i++) {
4040 ci_table->mc_reg_table_entry[i].mclk_max =
4041 table->mc_reg_table_entry[i].mclk_max;
4042 for (j = 0; j < table->last; j++)
4043 ci_table->mc_reg_table_entry[i].mc_data[j] =
4044 table->mc_reg_table_entry[i].mc_data[j];
4045 }
4046 ci_table->num_entries = table->num_entries;
4047
4048 return 0;
4049 }
4050
ci_initialize_mc_reg_table(struct radeon_device * rdev)4051 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4052 {
4053 struct ci_power_info *pi = ci_get_pi(rdev);
4054 struct atom_mc_reg_table *table;
4055 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4056 u8 module_index = rv770_get_memory_module_index(rdev);
4057 int ret;
4058
4059 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4060 if (!table)
4061 return -ENOMEM;
4062
4063 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4064 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4065 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4066 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4067 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4068 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4069 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4070 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4071 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4072 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4073 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4074 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4075 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4076 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4077 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4078 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4079 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4080 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4081 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4082 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4083
4084 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4085 if (ret)
4086 goto init_mc_done;
4087
4088 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4089 if (ret)
4090 goto init_mc_done;
4091
4092 ci_set_s0_mc_reg_index(ci_table);
4093
4094 ret = ci_set_mc_special_registers(rdev, ci_table);
4095 if (ret)
4096 goto init_mc_done;
4097
4098 ci_set_valid_flag(ci_table);
4099
4100 init_mc_done:
4101 kfree(table);
4102
4103 return ret;
4104 }
4105
ci_populate_mc_reg_addresses(struct radeon_device * rdev,SMU7_Discrete_MCRegisters * mc_reg_table)4106 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4107 SMU7_Discrete_MCRegisters *mc_reg_table)
4108 {
4109 struct ci_power_info *pi = ci_get_pi(rdev);
4110 u32 i, j;
4111
4112 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4113 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4114 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4115 return -EINVAL;
4116 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4117 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4118 i++;
4119 }
4120 }
4121
4122 mc_reg_table->last = (u8)i;
4123
4124 return 0;
4125 }
4126
ci_convert_mc_registers(const struct ci_mc_reg_entry * entry,SMU7_Discrete_MCRegisterSet * data,u32 num_entries,u32 valid_flag)4127 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4128 SMU7_Discrete_MCRegisterSet *data,
4129 u32 num_entries, u32 valid_flag)
4130 {
4131 u32 i, j;
4132
4133 for (i = 0, j = 0; j < num_entries; j++) {
4134 if (valid_flag & (1 << j)) {
4135 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4136 i++;
4137 }
4138 }
4139 }
4140
ci_convert_mc_reg_table_entry_to_smc(struct radeon_device * rdev,const u32 memory_clock,SMU7_Discrete_MCRegisterSet * mc_reg_table_data)4141 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4142 const u32 memory_clock,
4143 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4144 {
4145 struct ci_power_info *pi = ci_get_pi(rdev);
4146 u32 i = 0;
4147
4148 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4149 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4150 break;
4151 }
4152
4153 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4154 --i;
4155
4156 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4157 mc_reg_table_data, pi->mc_reg_table.last,
4158 pi->mc_reg_table.valid_flag);
4159 }
4160
ci_convert_mc_reg_table_to_smc(struct radeon_device * rdev,SMU7_Discrete_MCRegisters * mc_reg_table)4161 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4162 SMU7_Discrete_MCRegisters *mc_reg_table)
4163 {
4164 struct ci_power_info *pi = ci_get_pi(rdev);
4165 u32 i;
4166
4167 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4168 ci_convert_mc_reg_table_entry_to_smc(rdev,
4169 pi->dpm_table.mclk_table.dpm_levels[i].value,
4170 &mc_reg_table->data[i]);
4171 }
4172
ci_populate_initial_mc_reg_table(struct radeon_device * rdev)4173 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4174 {
4175 struct ci_power_info *pi = ci_get_pi(rdev);
4176 int ret;
4177
4178 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4179
4180 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4181 if (ret)
4182 return ret;
4183 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4184
4185 return ci_copy_bytes_to_smc(rdev,
4186 pi->mc_reg_table_start,
4187 (u8 *)&pi->smc_mc_reg_table,
4188 sizeof(SMU7_Discrete_MCRegisters),
4189 pi->sram_end);
4190 }
4191
ci_update_and_upload_mc_reg_table(struct radeon_device * rdev)4192 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4193 {
4194 struct ci_power_info *pi = ci_get_pi(rdev);
4195
4196 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4197 return 0;
4198
4199 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4200
4201 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4202
4203 return ci_copy_bytes_to_smc(rdev,
4204 pi->mc_reg_table_start +
4205 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4206 (u8 *)&pi->smc_mc_reg_table.data[0],
4207 sizeof(SMU7_Discrete_MCRegisterSet) *
4208 pi->dpm_table.mclk_table.count,
4209 pi->sram_end);
4210 }
4211
ci_enable_voltage_control(struct radeon_device * rdev)4212 static void ci_enable_voltage_control(struct radeon_device *rdev)
4213 {
4214 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4215
4216 tmp |= VOLT_PWRMGT_EN;
4217 WREG32_SMC(GENERAL_PWRMGT, tmp);
4218 }
4219
ci_get_maximum_link_speed(struct radeon_device * rdev,struct radeon_ps * radeon_state)4220 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4221 struct radeon_ps *radeon_state)
4222 {
4223 struct ci_ps *state = ci_get_ps(radeon_state);
4224 int i;
4225 u16 pcie_speed, max_speed = 0;
4226
4227 for (i = 0; i < state->performance_level_count; i++) {
4228 pcie_speed = state->performance_levels[i].pcie_gen;
4229 if (max_speed < pcie_speed)
4230 max_speed = pcie_speed;
4231 }
4232
4233 return max_speed;
4234 }
4235
ci_get_current_pcie_speed(struct radeon_device * rdev)4236 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4237 {
4238 u32 speed_cntl = 0;
4239
4240 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4241 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4242
4243 return (u16)speed_cntl;
4244 }
4245
ci_get_current_pcie_lane_number(struct radeon_device * rdev)4246 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4247 {
4248 u32 link_width = 0;
4249
4250 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4251 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4252
4253 switch (link_width) {
4254 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4255 return 1;
4256 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4257 return 2;
4258 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4259 return 4;
4260 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4261 return 8;
4262 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4263 /* not actually supported */
4264 return 12;
4265 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4266 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4267 default:
4268 return 16;
4269 }
4270 }
4271
ci_request_link_speed_change_before_state_change(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)4272 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4273 struct radeon_ps *radeon_new_state,
4274 struct radeon_ps *radeon_current_state)
4275 {
4276 struct ci_power_info *pi = ci_get_pi(rdev);
4277 enum radeon_pcie_gen target_link_speed =
4278 ci_get_maximum_link_speed(rdev, radeon_new_state);
4279 enum radeon_pcie_gen current_link_speed;
4280
4281 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4282 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4283 else
4284 current_link_speed = pi->force_pcie_gen;
4285
4286 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4287 pi->pspp_notify_required = false;
4288 if (target_link_speed > current_link_speed) {
4289 switch (target_link_speed) {
4290 #ifdef CONFIG_ACPI
4291 case RADEON_PCIE_GEN3:
4292 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4293 break;
4294 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4295 if (current_link_speed == RADEON_PCIE_GEN2)
4296 break;
4297 case RADEON_PCIE_GEN2:
4298 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4299 break;
4300 #endif
4301 default:
4302 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4303 break;
4304 }
4305 } else {
4306 if (target_link_speed < current_link_speed)
4307 pi->pspp_notify_required = true;
4308 }
4309 }
4310
ci_notify_link_speed_change_after_state_change(struct radeon_device * rdev,struct radeon_ps * radeon_new_state,struct radeon_ps * radeon_current_state)4311 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4312 struct radeon_ps *radeon_new_state,
4313 struct radeon_ps *radeon_current_state)
4314 {
4315 struct ci_power_info *pi = ci_get_pi(rdev);
4316 enum radeon_pcie_gen target_link_speed =
4317 ci_get_maximum_link_speed(rdev, radeon_new_state);
4318 u8 request;
4319
4320 if (pi->pspp_notify_required) {
4321 if (target_link_speed == RADEON_PCIE_GEN3)
4322 request = PCIE_PERF_REQ_PECI_GEN3;
4323 else if (target_link_speed == RADEON_PCIE_GEN2)
4324 request = PCIE_PERF_REQ_PECI_GEN2;
4325 else
4326 request = PCIE_PERF_REQ_PECI_GEN1;
4327
4328 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4329 (ci_get_current_pcie_speed(rdev) > 0))
4330 return;
4331
4332 #ifdef CONFIG_ACPI
4333 radeon_acpi_pcie_performance_request(rdev, request, false);
4334 #endif
4335 }
4336 }
4337
ci_set_private_data_variables_based_on_pptable(struct radeon_device * rdev)4338 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4339 {
4340 struct ci_power_info *pi = ci_get_pi(rdev);
4341 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4342 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4343 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4344 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4345 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4346 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4347
4348 if (allowed_sclk_vddc_table == NULL)
4349 return -EINVAL;
4350 if (allowed_sclk_vddc_table->count < 1)
4351 return -EINVAL;
4352 if (allowed_mclk_vddc_table == NULL)
4353 return -EINVAL;
4354 if (allowed_mclk_vddc_table->count < 1)
4355 return -EINVAL;
4356 if (allowed_mclk_vddci_table == NULL)
4357 return -EINVAL;
4358 if (allowed_mclk_vddci_table->count < 1)
4359 return -EINVAL;
4360
4361 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4362 pi->max_vddc_in_pp_table =
4363 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4364
4365 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4366 pi->max_vddci_in_pp_table =
4367 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4368
4369 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4370 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4371 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4372 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4373 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4374 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4375 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4376 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4377
4378 return 0;
4379 }
4380
ci_patch_with_vddc_leakage(struct radeon_device * rdev,u16 * vddc)4381 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4382 {
4383 struct ci_power_info *pi = ci_get_pi(rdev);
4384 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4385 u32 leakage_index;
4386
4387 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4388 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4389 *vddc = leakage_table->actual_voltage[leakage_index];
4390 break;
4391 }
4392 }
4393 }
4394
ci_patch_with_vddci_leakage(struct radeon_device * rdev,u16 * vddci)4395 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4396 {
4397 struct ci_power_info *pi = ci_get_pi(rdev);
4398 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4399 u32 leakage_index;
4400
4401 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4402 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4403 *vddci = leakage_table->actual_voltage[leakage_index];
4404 break;
4405 }
4406 }
4407 }
4408
ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * table)4409 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4410 struct radeon_clock_voltage_dependency_table *table)
4411 {
4412 u32 i;
4413
4414 if (table) {
4415 for (i = 0; i < table->count; i++)
4416 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4417 }
4418 }
4419
ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device * rdev,struct radeon_clock_voltage_dependency_table * table)4420 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4421 struct radeon_clock_voltage_dependency_table *table)
4422 {
4423 u32 i;
4424
4425 if (table) {
4426 for (i = 0; i < table->count; i++)
4427 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4428 }
4429 }
4430
ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_vce_clock_voltage_dependency_table * table)4431 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4432 struct radeon_vce_clock_voltage_dependency_table *table)
4433 {
4434 u32 i;
4435
4436 if (table) {
4437 for (i = 0; i < table->count; i++)
4438 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4439 }
4440 }
4441
ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_uvd_clock_voltage_dependency_table * table)4442 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4443 struct radeon_uvd_clock_voltage_dependency_table *table)
4444 {
4445 u32 i;
4446
4447 if (table) {
4448 for (i = 0; i < table->count; i++)
4449 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4450 }
4451 }
4452
ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_phase_shedding_limits_table * table)4453 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4454 struct radeon_phase_shedding_limits_table *table)
4455 {
4456 u32 i;
4457
4458 if (table) {
4459 for (i = 0; i < table->count; i++)
4460 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4461 }
4462 }
4463
ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device * rdev,struct radeon_clock_and_voltage_limits * table)4464 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4465 struct radeon_clock_and_voltage_limits *table)
4466 {
4467 if (table) {
4468 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4469 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4470 }
4471 }
4472
ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device * rdev,struct radeon_cac_leakage_table * table)4473 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4474 struct radeon_cac_leakage_table *table)
4475 {
4476 u32 i;
4477
4478 if (table) {
4479 for (i = 0; i < table->count; i++)
4480 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4481 }
4482 }
4483
ci_patch_dependency_tables_with_leakage(struct radeon_device * rdev)4484 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4485 {
4486
4487 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4488 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4489 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4490 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4491 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4492 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4493 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4494 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4495 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4496 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4497 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4498 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4499 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4500 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4501 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4502 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4503 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4504 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4505 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4506 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4507 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4508 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4509 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4510 &rdev->pm.dpm.dyn_state.cac_leakage_table);
4511
4512 }
4513
ci_get_memory_type(struct radeon_device * rdev)4514 static void ci_get_memory_type(struct radeon_device *rdev)
4515 {
4516 struct ci_power_info *pi = ci_get_pi(rdev);
4517 u32 tmp;
4518
4519 tmp = RREG32(MC_SEQ_MISC0);
4520
4521 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4522 MC_SEQ_MISC0_GDDR5_VALUE)
4523 pi->mem_gddr5 = true;
4524 else
4525 pi->mem_gddr5 = false;
4526
4527 }
4528
ci_update_current_ps(struct radeon_device * rdev,struct radeon_ps * rps)4529 static void ci_update_current_ps(struct radeon_device *rdev,
4530 struct radeon_ps *rps)
4531 {
4532 struct ci_ps *new_ps = ci_get_ps(rps);
4533 struct ci_power_info *pi = ci_get_pi(rdev);
4534
4535 pi->current_rps = *rps;
4536 pi->current_ps = *new_ps;
4537 pi->current_rps.ps_priv = &pi->current_ps;
4538 }
4539
ci_update_requested_ps(struct radeon_device * rdev,struct radeon_ps * rps)4540 static void ci_update_requested_ps(struct radeon_device *rdev,
4541 struct radeon_ps *rps)
4542 {
4543 struct ci_ps *new_ps = ci_get_ps(rps);
4544 struct ci_power_info *pi = ci_get_pi(rdev);
4545
4546 pi->requested_rps = *rps;
4547 pi->requested_ps = *new_ps;
4548 pi->requested_rps.ps_priv = &pi->requested_ps;
4549 }
4550
ci_dpm_pre_set_power_state(struct radeon_device * rdev)4551 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4552 {
4553 struct ci_power_info *pi = ci_get_pi(rdev);
4554 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4555 struct radeon_ps *new_ps = &requested_ps;
4556
4557 ci_update_requested_ps(rdev, new_ps);
4558
4559 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4560
4561 return 0;
4562 }
4563
ci_dpm_post_set_power_state(struct radeon_device * rdev)4564 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4565 {
4566 struct ci_power_info *pi = ci_get_pi(rdev);
4567 struct radeon_ps *new_ps = &pi->requested_rps;
4568
4569 ci_update_current_ps(rdev, new_ps);
4570 }
4571
4572
ci_dpm_setup_asic(struct radeon_device * rdev)4573 void ci_dpm_setup_asic(struct radeon_device *rdev)
4574 {
4575 int r;
4576
4577 r = ci_mc_load_microcode(rdev);
4578 if (r)
4579 DRM_ERROR("Failed to load MC firmware!\n");
4580 ci_read_clock_registers(rdev);
4581 ci_get_memory_type(rdev);
4582 ci_enable_acpi_power_management(rdev);
4583 ci_init_sclk_t(rdev);
4584 }
4585
ci_dpm_enable(struct radeon_device * rdev)4586 int ci_dpm_enable(struct radeon_device *rdev)
4587 {
4588 struct ci_power_info *pi = ci_get_pi(rdev);
4589 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4590 int ret;
4591
4592 if (ci_is_smc_running(rdev))
4593 return -EINVAL;
4594 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4595 ci_enable_voltage_control(rdev);
4596 ret = ci_construct_voltage_tables(rdev);
4597 if (ret) {
4598 DRM_ERROR("ci_construct_voltage_tables failed\n");
4599 return ret;
4600 }
4601 }
4602 if (pi->caps_dynamic_ac_timing) {
4603 ret = ci_initialize_mc_reg_table(rdev);
4604 if (ret)
4605 pi->caps_dynamic_ac_timing = false;
4606 }
4607 if (pi->dynamic_ss)
4608 ci_enable_spread_spectrum(rdev, true);
4609 if (pi->thermal_protection)
4610 ci_enable_thermal_protection(rdev, true);
4611 ci_program_sstp(rdev);
4612 ci_enable_display_gap(rdev);
4613 ci_program_vc(rdev);
4614 ret = ci_upload_firmware(rdev);
4615 if (ret) {
4616 DRM_ERROR("ci_upload_firmware failed\n");
4617 return ret;
4618 }
4619 ret = ci_process_firmware_header(rdev);
4620 if (ret) {
4621 DRM_ERROR("ci_process_firmware_header failed\n");
4622 return ret;
4623 }
4624 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4625 if (ret) {
4626 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4627 return ret;
4628 }
4629 ret = ci_init_smc_table(rdev);
4630 if (ret) {
4631 DRM_ERROR("ci_init_smc_table failed\n");
4632 return ret;
4633 }
4634 ret = ci_init_arb_table_index(rdev);
4635 if (ret) {
4636 DRM_ERROR("ci_init_arb_table_index failed\n");
4637 return ret;
4638 }
4639 if (pi->caps_dynamic_ac_timing) {
4640 ret = ci_populate_initial_mc_reg_table(rdev);
4641 if (ret) {
4642 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4643 return ret;
4644 }
4645 }
4646 ret = ci_populate_pm_base(rdev);
4647 if (ret) {
4648 DRM_ERROR("ci_populate_pm_base failed\n");
4649 return ret;
4650 }
4651 ci_dpm_start_smc(rdev);
4652 ci_enable_vr_hot_gpio_interrupt(rdev);
4653 ret = ci_notify_smc_display_change(rdev, false);
4654 if (ret) {
4655 DRM_ERROR("ci_notify_smc_display_change failed\n");
4656 return ret;
4657 }
4658 ci_enable_sclk_control(rdev, true);
4659 ret = ci_enable_ulv(rdev, true);
4660 if (ret) {
4661 DRM_ERROR("ci_enable_ulv failed\n");
4662 return ret;
4663 }
4664 ret = ci_enable_ds_master_switch(rdev, true);
4665 if (ret) {
4666 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4667 return ret;
4668 }
4669 ret = ci_start_dpm(rdev);
4670 if (ret) {
4671 DRM_ERROR("ci_start_dpm failed\n");
4672 return ret;
4673 }
4674 ret = ci_enable_didt(rdev, true);
4675 if (ret) {
4676 DRM_ERROR("ci_enable_didt failed\n");
4677 return ret;
4678 }
4679 ret = ci_enable_smc_cac(rdev, true);
4680 if (ret) {
4681 DRM_ERROR("ci_enable_smc_cac failed\n");
4682 return ret;
4683 }
4684 ret = ci_enable_power_containment(rdev, true);
4685 if (ret) {
4686 DRM_ERROR("ci_enable_power_containment failed\n");
4687 return ret;
4688 }
4689
4690 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4691
4692 ci_update_current_ps(rdev, boot_ps);
4693
4694 return 0;
4695 }
4696
ci_dpm_late_enable(struct radeon_device * rdev)4697 int ci_dpm_late_enable(struct radeon_device *rdev)
4698 {
4699 int ret;
4700
4701 if (rdev->irq.installed &&
4702 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4703 #if 0
4704 PPSMC_Result result;
4705 #endif
4706 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4707 if (ret) {
4708 DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4709 return ret;
4710 }
4711 rdev->irq.dpm_thermal = true;
4712 radeon_irq_set(rdev);
4713 #if 0
4714 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4715
4716 if (result != PPSMC_Result_OK)
4717 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4718 #endif
4719 }
4720
4721 ci_dpm_powergate_uvd(rdev, true);
4722
4723 return 0;
4724 }
4725
ci_dpm_disable(struct radeon_device * rdev)4726 void ci_dpm_disable(struct radeon_device *rdev)
4727 {
4728 struct ci_power_info *pi = ci_get_pi(rdev);
4729 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4730
4731 ci_dpm_powergate_uvd(rdev, false);
4732
4733 if (!ci_is_smc_running(rdev))
4734 return;
4735
4736 if (pi->thermal_protection)
4737 ci_enable_thermal_protection(rdev, false);
4738 ci_enable_power_containment(rdev, false);
4739 ci_enable_smc_cac(rdev, false);
4740 ci_enable_didt(rdev, false);
4741 ci_enable_spread_spectrum(rdev, false);
4742 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4743 ci_stop_dpm(rdev);
4744 ci_enable_ds_master_switch(rdev, false);
4745 ci_enable_ulv(rdev, false);
4746 ci_clear_vc(rdev);
4747 ci_reset_to_default(rdev);
4748 ci_dpm_stop_smc(rdev);
4749 ci_force_switch_to_arb_f0(rdev);
4750
4751 ci_update_current_ps(rdev, boot_ps);
4752 }
4753
ci_dpm_set_power_state(struct radeon_device * rdev)4754 int ci_dpm_set_power_state(struct radeon_device *rdev)
4755 {
4756 struct ci_power_info *pi = ci_get_pi(rdev);
4757 struct radeon_ps *new_ps = &pi->requested_rps;
4758 struct radeon_ps *old_ps = &pi->current_rps;
4759 int ret;
4760
4761 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4762 if (pi->pcie_performance_request)
4763 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4764 ret = ci_freeze_sclk_mclk_dpm(rdev);
4765 if (ret) {
4766 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4767 return ret;
4768 }
4769 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4770 if (ret) {
4771 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4772 return ret;
4773 }
4774 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4775 if (ret) {
4776 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4777 return ret;
4778 }
4779
4780 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4781 if (ret) {
4782 DRM_ERROR("ci_update_vce_dpm failed\n");
4783 return ret;
4784 }
4785
4786 ret = ci_update_sclk_t(rdev);
4787 if (ret) {
4788 DRM_ERROR("ci_update_sclk_t failed\n");
4789 return ret;
4790 }
4791 if (pi->caps_dynamic_ac_timing) {
4792 ret = ci_update_and_upload_mc_reg_table(rdev);
4793 if (ret) {
4794 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4795 return ret;
4796 }
4797 }
4798 ret = ci_program_memory_timing_parameters(rdev);
4799 if (ret) {
4800 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4801 return ret;
4802 }
4803 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4804 if (ret) {
4805 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4806 return ret;
4807 }
4808 ret = ci_upload_dpm_level_enable_mask(rdev);
4809 if (ret) {
4810 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4811 return ret;
4812 }
4813 if (pi->pcie_performance_request)
4814 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4815
4816 return 0;
4817 }
4818
ci_dpm_power_control_set_level(struct radeon_device * rdev)4819 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4820 {
4821 return ci_power_control_set_level(rdev);
4822 }
4823
ci_dpm_reset_asic(struct radeon_device * rdev)4824 void ci_dpm_reset_asic(struct radeon_device *rdev)
4825 {
4826 ci_set_boot_state(rdev);
4827 }
4828
ci_dpm_display_configuration_changed(struct radeon_device * rdev)4829 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4830 {
4831 ci_program_display_gap(rdev);
4832 }
4833
4834 union power_info {
4835 struct _ATOM_POWERPLAY_INFO info;
4836 struct _ATOM_POWERPLAY_INFO_V2 info_2;
4837 struct _ATOM_POWERPLAY_INFO_V3 info_3;
4838 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4839 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4840 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4841 };
4842
4843 union pplib_clock_info {
4844 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4845 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4846 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4847 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4848 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4849 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4850 };
4851
4852 union pplib_power_state {
4853 struct _ATOM_PPLIB_STATE v1;
4854 struct _ATOM_PPLIB_STATE_V2 v2;
4855 };
4856
ci_parse_pplib_non_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,struct _ATOM_PPLIB_NONCLOCK_INFO * non_clock_info,u8 table_rev)4857 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4858 struct radeon_ps *rps,
4859 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4860 u8 table_rev)
4861 {
4862 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4863 rps->class = le16_to_cpu(non_clock_info->usClassification);
4864 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4865
4866 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4867 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4868 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4869 } else {
4870 rps->vclk = 0;
4871 rps->dclk = 0;
4872 }
4873
4874 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4875 rdev->pm.dpm.boot_ps = rps;
4876 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4877 rdev->pm.dpm.uvd_ps = rps;
4878 }
4879
ci_parse_pplib_clock_info(struct radeon_device * rdev,struct radeon_ps * rps,int index,union pplib_clock_info * clock_info)4880 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4881 struct radeon_ps *rps, int index,
4882 union pplib_clock_info *clock_info)
4883 {
4884 struct ci_power_info *pi = ci_get_pi(rdev);
4885 struct ci_ps *ps = ci_get_ps(rps);
4886 struct ci_pl *pl = &ps->performance_levels[index];
4887
4888 ps->performance_level_count = index + 1;
4889
4890 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4891 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4892 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4893 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4894
4895 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4896 pi->sys_pcie_mask,
4897 pi->vbios_boot_state.pcie_gen_bootup_value,
4898 clock_info->ci.ucPCIEGen);
4899 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4900 pi->vbios_boot_state.pcie_lane_bootup_value,
4901 le16_to_cpu(clock_info->ci.usPCIELane));
4902
4903 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4904 pi->acpi_pcie_gen = pl->pcie_gen;
4905 }
4906
4907 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4908 pi->ulv.supported = true;
4909 pi->ulv.pl = *pl;
4910 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4911 }
4912
4913 /* patch up boot state */
4914 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4915 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4916 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4917 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4918 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4919 }
4920
4921 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4922 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4923 pi->use_pcie_powersaving_levels = true;
4924 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4925 pi->pcie_gen_powersaving.max = pl->pcie_gen;
4926 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4927 pi->pcie_gen_powersaving.min = pl->pcie_gen;
4928 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4929 pi->pcie_lane_powersaving.max = pl->pcie_lane;
4930 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4931 pi->pcie_lane_powersaving.min = pl->pcie_lane;
4932 break;
4933 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4934 pi->use_pcie_performance_levels = true;
4935 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4936 pi->pcie_gen_performance.max = pl->pcie_gen;
4937 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4938 pi->pcie_gen_performance.min = pl->pcie_gen;
4939 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4940 pi->pcie_lane_performance.max = pl->pcie_lane;
4941 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4942 pi->pcie_lane_performance.min = pl->pcie_lane;
4943 break;
4944 default:
4945 break;
4946 }
4947 }
4948
ci_parse_power_table(struct radeon_device * rdev)4949 static int ci_parse_power_table(struct radeon_device *rdev)
4950 {
4951 struct radeon_mode_info *mode_info = &rdev->mode_info;
4952 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4953 union pplib_power_state *power_state;
4954 int i, j, k, non_clock_array_index, clock_array_index;
4955 union pplib_clock_info *clock_info;
4956 struct _StateArray *state_array;
4957 struct _ClockInfoArray *clock_info_array;
4958 struct _NonClockInfoArray *non_clock_info_array;
4959 union power_info *power_info;
4960 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4961 u16 data_offset;
4962 u8 frev, crev;
4963 u8 *power_state_offset;
4964 struct ci_ps *ps;
4965
4966 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4967 &frev, &crev, &data_offset))
4968 return -EINVAL;
4969 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4970
4971 state_array = (struct _StateArray *)
4972 (mode_info->atom_context->bios + data_offset +
4973 le16_to_cpu(power_info->pplib.usStateArrayOffset));
4974 clock_info_array = (struct _ClockInfoArray *)
4975 (mode_info->atom_context->bios + data_offset +
4976 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4977 non_clock_info_array = (struct _NonClockInfoArray *)
4978 (mode_info->atom_context->bios + data_offset +
4979 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4980
4981 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4982 state_array->ucNumEntries, GFP_KERNEL);
4983 if (!rdev->pm.dpm.ps)
4984 return -ENOMEM;
4985 power_state_offset = (u8 *)state_array->states;
4986 for (i = 0; i < state_array->ucNumEntries; i++) {
4987 u8 *idx;
4988 power_state = (union pplib_power_state *)power_state_offset;
4989 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4990 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4991 &non_clock_info_array->nonClockInfo[non_clock_array_index];
4992 if (!rdev->pm.power_state[i].clock_info)
4993 return -EINVAL;
4994 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
4995 if (ps == NULL) {
4996 kfree(rdev->pm.dpm.ps);
4997 return -ENOMEM;
4998 }
4999 rdev->pm.dpm.ps[i].ps_priv = ps;
5000 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5001 non_clock_info,
5002 non_clock_info_array->ucEntrySize);
5003 k = 0;
5004 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5005 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5006 clock_array_index = idx[j];
5007 if (clock_array_index >= clock_info_array->ucNumEntries)
5008 continue;
5009 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5010 break;
5011 clock_info = (union pplib_clock_info *)
5012 ((u8 *)&clock_info_array->clockInfo[0] +
5013 (clock_array_index * clock_info_array->ucEntrySize));
5014 ci_parse_pplib_clock_info(rdev,
5015 &rdev->pm.dpm.ps[i], k,
5016 clock_info);
5017 k++;
5018 }
5019 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5020 }
5021 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5022
5023 /* fill in the vce power states */
5024 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5025 u32 sclk, mclk;
5026 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5027 clock_info = (union pplib_clock_info *)
5028 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5029 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5030 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5031 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5032 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5033 rdev->pm.dpm.vce_states[i].sclk = sclk;
5034 rdev->pm.dpm.vce_states[i].mclk = mclk;
5035 }
5036
5037 return 0;
5038 }
5039
ci_get_vbios_boot_values(struct radeon_device * rdev,struct ci_vbios_boot_state * boot_state)5040 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5041 struct ci_vbios_boot_state *boot_state)
5042 {
5043 struct radeon_mode_info *mode_info = &rdev->mode_info;
5044 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5045 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5046 u8 frev, crev;
5047 u16 data_offset;
5048
5049 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5050 &frev, &crev, &data_offset)) {
5051 firmware_info =
5052 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5053 data_offset);
5054 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5055 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5056 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5057 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5058 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5059 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5060 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5061
5062 return 0;
5063 }
5064 return -EINVAL;
5065 }
5066
ci_dpm_fini(struct radeon_device * rdev)5067 void ci_dpm_fini(struct radeon_device *rdev)
5068 {
5069 int i;
5070
5071 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5072 kfree(rdev->pm.dpm.ps[i].ps_priv);
5073 }
5074 kfree(rdev->pm.dpm.ps);
5075 kfree(rdev->pm.dpm.priv);
5076 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5077 r600_free_extended_power_table(rdev);
5078 }
5079
ci_dpm_init(struct radeon_device * rdev)5080 int ci_dpm_init(struct radeon_device *rdev)
5081 {
5082 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5083 u16 data_offset, size;
5084 u8 frev, crev;
5085 struct ci_power_info *pi;
5086 int ret;
5087 u32 mask;
5088
5089 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5090 if (pi == NULL)
5091 return -ENOMEM;
5092 rdev->pm.dpm.priv = pi;
5093
5094 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5095 if (ret)
5096 pi->sys_pcie_mask = 0;
5097 else
5098 pi->sys_pcie_mask = mask;
5099 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5100
5101 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5102 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5103 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5104 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5105
5106 pi->pcie_lane_performance.max = 0;
5107 pi->pcie_lane_performance.min = 16;
5108 pi->pcie_lane_powersaving.max = 0;
5109 pi->pcie_lane_powersaving.min = 16;
5110
5111 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5112 if (ret) {
5113 ci_dpm_fini(rdev);
5114 return ret;
5115 }
5116
5117 ret = r600_get_platform_caps(rdev);
5118 if (ret) {
5119 ci_dpm_fini(rdev);
5120 return ret;
5121 }
5122
5123 ret = r600_parse_extended_power_table(rdev);
5124 if (ret) {
5125 ci_dpm_fini(rdev);
5126 return ret;
5127 }
5128
5129 ret = ci_parse_power_table(rdev);
5130 if (ret) {
5131 ci_dpm_fini(rdev);
5132 return ret;
5133 }
5134
5135 pi->dll_default_on = false;
5136 pi->sram_end = SMC_RAM_END;
5137
5138 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5139 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5140 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5141 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5142 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5143 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5144 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5145 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5146
5147 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5148
5149 pi->sclk_dpm_key_disabled = 0;
5150 pi->mclk_dpm_key_disabled = 0;
5151 pi->pcie_dpm_key_disabled = 0;
5152
5153 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5154 if ((rdev->pdev->device == 0x6658) &&
5155 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5156 pi->mclk_dpm_key_disabled = 1;
5157 }
5158
5159 pi->caps_sclk_ds = true;
5160
5161 pi->mclk_strobe_mode_threshold = 40000;
5162 pi->mclk_stutter_mode_threshold = 40000;
5163 pi->mclk_edc_enable_threshold = 40000;
5164 pi->mclk_edc_wr_enable_threshold = 40000;
5165
5166 ci_initialize_powertune_defaults(rdev);
5167
5168 pi->caps_fps = false;
5169
5170 pi->caps_sclk_throttle_low_notification = false;
5171
5172 pi->caps_uvd_dpm = true;
5173 pi->caps_vce_dpm = true;
5174
5175 ci_get_leakage_voltages(rdev);
5176 ci_patch_dependency_tables_with_leakage(rdev);
5177 ci_set_private_data_variables_based_on_pptable(rdev);
5178
5179 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5180 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5181 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5182 ci_dpm_fini(rdev);
5183 return -ENOMEM;
5184 }
5185 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5186 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5187 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5188 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5189 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5190 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5191 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5192 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5193 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5194
5195 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5196 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5197 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5198
5199 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5200 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5201 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5202 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5203
5204 if (rdev->family == CHIP_HAWAII) {
5205 pi->thermal_temp_setting.temperature_low = 94500;
5206 pi->thermal_temp_setting.temperature_high = 95000;
5207 pi->thermal_temp_setting.temperature_shutdown = 104000;
5208 } else {
5209 pi->thermal_temp_setting.temperature_low = 99500;
5210 pi->thermal_temp_setting.temperature_high = 100000;
5211 pi->thermal_temp_setting.temperature_shutdown = 104000;
5212 }
5213
5214 pi->uvd_enabled = false;
5215
5216 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5217 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5218 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5219 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5220 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5221 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5222 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5223
5224 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5225 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5226 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5227 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5228 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5229 else
5230 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5231 }
5232
5233 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5234 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5235 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5236 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5237 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5238 else
5239 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5240 }
5241
5242 pi->vddc_phase_shed_control = true;
5243
5244 #if defined(CONFIG_ACPI)
5245 pi->pcie_performance_request =
5246 radeon_acpi_is_pcie_performance_request_supported(rdev);
5247 #else
5248 pi->pcie_performance_request = false;
5249 #endif
5250
5251 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5252 &frev, &crev, &data_offset)) {
5253 pi->caps_sclk_ss_support = true;
5254 pi->caps_mclk_ss_support = true;
5255 pi->dynamic_ss = true;
5256 } else {
5257 pi->caps_sclk_ss_support = false;
5258 pi->caps_mclk_ss_support = false;
5259 pi->dynamic_ss = true;
5260 }
5261
5262 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5263 pi->thermal_protection = true;
5264 else
5265 pi->thermal_protection = false;
5266
5267 pi->caps_dynamic_ac_timing = true;
5268
5269 pi->uvd_power_gated = false;
5270
5271 /* make sure dc limits are valid */
5272 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5273 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5274 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5275 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5276
5277 return 0;
5278 }
5279
ci_dpm_debugfs_print_current_performance_level(struct radeon_device * rdev,struct seq_file * m)5280 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5281 struct seq_file *m)
5282 {
5283 struct ci_power_info *pi = ci_get_pi(rdev);
5284 struct radeon_ps *rps = &pi->current_rps;
5285 u32 sclk = ci_get_average_sclk_freq(rdev);
5286 u32 mclk = ci_get_average_mclk_freq(rdev);
5287
5288 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5289 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5290 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5291 sclk, mclk);
5292 }
5293
ci_dpm_print_power_state(struct radeon_device * rdev,struct radeon_ps * rps)5294 void ci_dpm_print_power_state(struct radeon_device *rdev,
5295 struct radeon_ps *rps)
5296 {
5297 struct ci_ps *ps = ci_get_ps(rps);
5298 struct ci_pl *pl;
5299 int i;
5300
5301 r600_dpm_print_class_info(rps->class, rps->class2);
5302 r600_dpm_print_cap_info(rps->caps);
5303 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5304 for (i = 0; i < ps->performance_level_count; i++) {
5305 pl = &ps->performance_levels[i];
5306 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5307 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5308 }
5309 r600_dpm_print_ps_status(rdev, rps);
5310 }
5311
ci_dpm_get_sclk(struct radeon_device * rdev,bool low)5312 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5313 {
5314 struct ci_power_info *pi = ci_get_pi(rdev);
5315 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5316
5317 if (low)
5318 return requested_state->performance_levels[0].sclk;
5319 else
5320 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5321 }
5322
ci_dpm_get_mclk(struct radeon_device * rdev,bool low)5323 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5324 {
5325 struct ci_power_info *pi = ci_get_pi(rdev);
5326 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5327
5328 if (low)
5329 return requested_state->performance_levels[0].mclk;
5330 else
5331 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5332 }
5333