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Searched refs:MI_FLUSH (Results 1 – 7 of 7) sorted by relevance

/drivers/video/fbdev/intelfb/
Dintelfbhw.h474 #define MI_FLUSH (0x04 << 23) macro
Dintelfbhw.c1552 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()
/drivers/gpu/drm/i915/
Dintel_ringbuffer.c90 cmd = MI_FLUSH; in gen2_render_ring_flush()
145 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen4_render_ring_flush()
1363 intel_ring_emit(ring, MI_FLUSH); in bsd_ring_flush()
1579 intel_ring_emit(ring, MI_FLUSH); in i830_dispatch_execbuffer()
Di915_dma.c545 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); in i915_dispatch_batchbuffer()
576 OUT_RING(MI_FLUSH | MI_READ_FLUSH); in i915_dispatch_flip()
Di915_cmd_parser.c145 CMD( MI_FLUSH, SMI, F, 1, S ),
Di915_reg.h223 #define MI_FLUSH MI_INSTR(0x04, 0) macro
Dintel_pm.c4540 intel_ring_emit(ring, MI_FLUSH); in ironlake_enable_rc6()