1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31 #include <linux/async.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_fb_helper.h>
35 #include <drm/drm_legacy.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <linux/pci.h>
41 #include <linux/console.h>
42 #include <linux/vt.h>
43 #include <linux/vgaarb.h>
44 #include <linux/acpi.h>
45 #include <linux/pnp.h>
46 #include <linux/vga_switcheroo.h>
47 #include <linux/slab.h>
48 #include <acpi/video.h>
49 #include <linux/pm.h>
50 #include <linux/pm_runtime.h>
51 #include <linux/oom.h>
52
53 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
54
55 #define BEGIN_LP_RING(n) \
56 intel_ring_begin(LP_RING(dev_priv), (n))
57
58 #define OUT_RING(x) \
59 intel_ring_emit(LP_RING(dev_priv), x)
60
61 #define ADVANCE_LP_RING() \
62 __intel_ring_advance(LP_RING(dev_priv))
63
64 /**
65 * Lock test for when it's just for synchronization of ring access.
66 *
67 * In that case, we don't need to do it when GEM is initialized as nobody else
68 * has access to the ring.
69 */
70 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
71 if (LP_RING(dev->dev_private)->buffer->obj == NULL) \
72 LOCK_TEST_WITH_RETURN(dev, file); \
73 } while (0)
74
75 static inline u32
intel_read_legacy_status_page(struct drm_i915_private * dev_priv,int reg)76 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
77 {
78 if (I915_NEED_GFX_HWS(dev_priv->dev))
79 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
80 else
81 return intel_read_status_page(LP_RING(dev_priv), reg);
82 }
83
84 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
85 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
86 #define I915_BREADCRUMB_INDEX 0x21
87
i915_update_dri1_breadcrumb(struct drm_device * dev)88 void i915_update_dri1_breadcrumb(struct drm_device *dev)
89 {
90 struct drm_i915_private *dev_priv = dev->dev_private;
91 struct drm_i915_master_private *master_priv;
92
93 /*
94 * The dri breadcrumb update races against the drm master disappearing.
95 * Instead of trying to fix this (this is by far not the only ums issue)
96 * just don't do the update in kms mode.
97 */
98 if (drm_core_check_feature(dev, DRIVER_MODESET))
99 return;
100
101 if (dev->primary->master) {
102 master_priv = dev->primary->master->driver_priv;
103 if (master_priv->sarea_priv)
104 master_priv->sarea_priv->last_dispatch =
105 READ_BREADCRUMB(dev_priv);
106 }
107 }
108
i915_write_hws_pga(struct drm_device * dev)109 static void i915_write_hws_pga(struct drm_device *dev)
110 {
111 struct drm_i915_private *dev_priv = dev->dev_private;
112 u32 addr;
113
114 addr = dev_priv->status_page_dmah->busaddr;
115 if (INTEL_INFO(dev)->gen >= 4)
116 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
117 I915_WRITE(HWS_PGA, addr);
118 }
119
120 /**
121 * Frees the hardware status page, whether it's a physical address or a virtual
122 * address set up by the X Server.
123 */
i915_free_hws(struct drm_device * dev)124 static void i915_free_hws(struct drm_device *dev)
125 {
126 struct drm_i915_private *dev_priv = dev->dev_private;
127 struct intel_engine_cs *ring = LP_RING(dev_priv);
128
129 if (dev_priv->status_page_dmah) {
130 drm_pci_free(dev, dev_priv->status_page_dmah);
131 dev_priv->status_page_dmah = NULL;
132 }
133
134 if (ring->status_page.gfx_addr) {
135 ring->status_page.gfx_addr = 0;
136 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
137 }
138
139 /* Need to rewrite hardware status page */
140 I915_WRITE(HWS_PGA, 0x1ffff000);
141 }
142
i915_kernel_lost_context(struct drm_device * dev)143 void i915_kernel_lost_context(struct drm_device *dev)
144 {
145 struct drm_i915_private *dev_priv = dev->dev_private;
146 struct drm_i915_master_private *master_priv;
147 struct intel_engine_cs *ring = LP_RING(dev_priv);
148 struct intel_ringbuffer *ringbuf = ring->buffer;
149
150 /*
151 * We should never lose context on the ring with modesetting
152 * as we don't expose it to userspace
153 */
154 if (drm_core_check_feature(dev, DRIVER_MODESET))
155 return;
156
157 ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
158 ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
159 ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
160 if (ringbuf->space < 0)
161 ringbuf->space += ringbuf->size;
162
163 if (!dev->primary->master)
164 return;
165
166 master_priv = dev->primary->master->driver_priv;
167 if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
168 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
169 }
170
i915_dma_cleanup(struct drm_device * dev)171 static int i915_dma_cleanup(struct drm_device *dev)
172 {
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 int i;
175
176 /* Make sure interrupts are disabled here because the uninstall ioctl
177 * may not have been called from userspace and after dev_private
178 * is freed, it's too late.
179 */
180 if (dev->irq_enabled)
181 drm_irq_uninstall(dev);
182
183 mutex_lock(&dev->struct_mutex);
184 for (i = 0; i < I915_NUM_RINGS; i++)
185 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
186 mutex_unlock(&dev->struct_mutex);
187
188 /* Clear the HWS virtual address at teardown */
189 if (I915_NEED_GFX_HWS(dev))
190 i915_free_hws(dev);
191
192 return 0;
193 }
194
i915_initialize(struct drm_device * dev,drm_i915_init_t * init)195 static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init)
196 {
197 struct drm_i915_private *dev_priv = dev->dev_private;
198 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
199 int ret;
200
201 master_priv->sarea = drm_legacy_getsarea(dev);
202 if (master_priv->sarea) {
203 master_priv->sarea_priv = (drm_i915_sarea_t *)
204 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
205 } else {
206 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
207 }
208
209 if (init->ring_size != 0) {
210 if (LP_RING(dev_priv)->buffer->obj != NULL) {
211 i915_dma_cleanup(dev);
212 DRM_ERROR("Client tried to initialize ringbuffer in "
213 "GEM mode\n");
214 return -EINVAL;
215 }
216
217 ret = intel_render_ring_init_dri(dev,
218 init->ring_start,
219 init->ring_size);
220 if (ret) {
221 i915_dma_cleanup(dev);
222 return ret;
223 }
224 }
225
226 dev_priv->dri1.cpp = init->cpp;
227 dev_priv->dri1.back_offset = init->back_offset;
228 dev_priv->dri1.front_offset = init->front_offset;
229 dev_priv->dri1.current_page = 0;
230 if (master_priv->sarea_priv)
231 master_priv->sarea_priv->pf_current_page = 0;
232
233 /* Allow hardware batchbuffers unless told otherwise.
234 */
235 dev_priv->dri1.allow_batchbuffer = 1;
236
237 return 0;
238 }
239
i915_dma_resume(struct drm_device * dev)240 static int i915_dma_resume(struct drm_device *dev)
241 {
242 struct drm_i915_private *dev_priv = dev->dev_private;
243 struct intel_engine_cs *ring = LP_RING(dev_priv);
244
245 DRM_DEBUG_DRIVER("%s\n", __func__);
246
247 if (ring->buffer->virtual_start == NULL) {
248 DRM_ERROR("can not ioremap virtual address for"
249 " ring buffer\n");
250 return -ENOMEM;
251 }
252
253 /* Program Hardware Status Page */
254 if (!ring->status_page.page_addr) {
255 DRM_ERROR("Can not find hardware status page\n");
256 return -EINVAL;
257 }
258 DRM_DEBUG_DRIVER("hw status page @ %p\n",
259 ring->status_page.page_addr);
260 if (ring->status_page.gfx_addr != 0)
261 intel_ring_setup_status_page(ring);
262 else
263 i915_write_hws_pga(dev);
264
265 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
266
267 return 0;
268 }
269
i915_dma_init(struct drm_device * dev,void * data,struct drm_file * file_priv)270 static int i915_dma_init(struct drm_device *dev, void *data,
271 struct drm_file *file_priv)
272 {
273 drm_i915_init_t *init = data;
274 int retcode = 0;
275
276 if (drm_core_check_feature(dev, DRIVER_MODESET))
277 return -ENODEV;
278
279 switch (init->func) {
280 case I915_INIT_DMA:
281 retcode = i915_initialize(dev, init);
282 break;
283 case I915_CLEANUP_DMA:
284 retcode = i915_dma_cleanup(dev);
285 break;
286 case I915_RESUME_DMA:
287 retcode = i915_dma_resume(dev);
288 break;
289 default:
290 retcode = -EINVAL;
291 break;
292 }
293
294 return retcode;
295 }
296
297 /* Implement basically the same security restrictions as hardware does
298 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
299 *
300 * Most of the calculations below involve calculating the size of a
301 * particular instruction. It's important to get the size right as
302 * that tells us where the next instruction to check is. Any illegal
303 * instruction detected will be given a size of zero, which is a
304 * signal to abort the rest of the buffer.
305 */
validate_cmd(int cmd)306 static int validate_cmd(int cmd)
307 {
308 switch (((cmd >> 29) & 0x7)) {
309 case 0x0:
310 switch ((cmd >> 23) & 0x3f) {
311 case 0x0:
312 return 1; /* MI_NOOP */
313 case 0x4:
314 return 1; /* MI_FLUSH */
315 default:
316 return 0; /* disallow everything else */
317 }
318 break;
319 case 0x1:
320 return 0; /* reserved */
321 case 0x2:
322 return (cmd & 0xff) + 2; /* 2d commands */
323 case 0x3:
324 if (((cmd >> 24) & 0x1f) <= 0x18)
325 return 1;
326
327 switch ((cmd >> 24) & 0x1f) {
328 case 0x1c:
329 return 1;
330 case 0x1d:
331 switch ((cmd >> 16) & 0xff) {
332 case 0x3:
333 return (cmd & 0x1f) + 2;
334 case 0x4:
335 return (cmd & 0xf) + 2;
336 default:
337 return (cmd & 0xffff) + 2;
338 }
339 case 0x1e:
340 if (cmd & (1 << 23))
341 return (cmd & 0xffff) + 1;
342 else
343 return 1;
344 case 0x1f:
345 if ((cmd & (1 << 23)) == 0) /* inline vertices */
346 return (cmd & 0x1ffff) + 2;
347 else if (cmd & (1 << 17)) /* indirect random */
348 if ((cmd & 0xffff) == 0)
349 return 0; /* unknown length, too hard */
350 else
351 return (((cmd & 0xffff) + 1) / 2) + 1;
352 else
353 return 2; /* indirect sequential */
354 default:
355 return 0;
356 }
357 default:
358 return 0;
359 }
360
361 return 0;
362 }
363
i915_emit_cmds(struct drm_device * dev,int * buffer,int dwords)364 static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords)
365 {
366 struct drm_i915_private *dev_priv = dev->dev_private;
367 int i, ret;
368
369 if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
370 return -EINVAL;
371
372 for (i = 0; i < dwords;) {
373 int sz = validate_cmd(buffer[i]);
374
375 if (sz == 0 || i + sz > dwords)
376 return -EINVAL;
377 i += sz;
378 }
379
380 ret = BEGIN_LP_RING((dwords+1)&~1);
381 if (ret)
382 return ret;
383
384 for (i = 0; i < dwords; i++)
385 OUT_RING(buffer[i]);
386 if (dwords & 1)
387 OUT_RING(0);
388
389 ADVANCE_LP_RING();
390
391 return 0;
392 }
393
394 int
i915_emit_box(struct drm_device * dev,struct drm_clip_rect * box,int DR1,int DR4)395 i915_emit_box(struct drm_device *dev,
396 struct drm_clip_rect *box,
397 int DR1, int DR4)
398 {
399 struct drm_i915_private *dev_priv = dev->dev_private;
400 int ret;
401
402 if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
403 box->y2 <= 0 || box->x2 <= 0) {
404 DRM_ERROR("Bad box %d,%d..%d,%d\n",
405 box->x1, box->y1, box->x2, box->y2);
406 return -EINVAL;
407 }
408
409 if (INTEL_INFO(dev)->gen >= 4) {
410 ret = BEGIN_LP_RING(4);
411 if (ret)
412 return ret;
413
414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
415 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
416 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
417 OUT_RING(DR4);
418 } else {
419 ret = BEGIN_LP_RING(6);
420 if (ret)
421 return ret;
422
423 OUT_RING(GFX_OP_DRAWRECT_INFO);
424 OUT_RING(DR1);
425 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
426 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
427 OUT_RING(DR4);
428 OUT_RING(0);
429 }
430 ADVANCE_LP_RING();
431
432 return 0;
433 }
434
435 /* XXX: Emitting the counter should really be moved to part of the IRQ
436 * emit. For now, do it in both places:
437 */
438
i915_emit_breadcrumb(struct drm_device * dev)439 static void i915_emit_breadcrumb(struct drm_device *dev)
440 {
441 struct drm_i915_private *dev_priv = dev->dev_private;
442 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
443
444 dev_priv->dri1.counter++;
445 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
446 dev_priv->dri1.counter = 0;
447 if (master_priv->sarea_priv)
448 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
449
450 if (BEGIN_LP_RING(4) == 0) {
451 OUT_RING(MI_STORE_DWORD_INDEX);
452 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
453 OUT_RING(dev_priv->dri1.counter);
454 OUT_RING(0);
455 ADVANCE_LP_RING();
456 }
457 }
458
i915_dispatch_cmdbuffer(struct drm_device * dev,drm_i915_cmdbuffer_t * cmd,struct drm_clip_rect * cliprects,void * cmdbuf)459 static int i915_dispatch_cmdbuffer(struct drm_device *dev,
460 drm_i915_cmdbuffer_t *cmd,
461 struct drm_clip_rect *cliprects,
462 void *cmdbuf)
463 {
464 int nbox = cmd->num_cliprects;
465 int i = 0, count, ret;
466
467 if (cmd->sz & 0x3) {
468 DRM_ERROR("alignment");
469 return -EINVAL;
470 }
471
472 i915_kernel_lost_context(dev);
473
474 count = nbox ? nbox : 1;
475
476 for (i = 0; i < count; i++) {
477 if (i < nbox) {
478 ret = i915_emit_box(dev, &cliprects[i],
479 cmd->DR1, cmd->DR4);
480 if (ret)
481 return ret;
482 }
483
484 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
485 if (ret)
486 return ret;
487 }
488
489 i915_emit_breadcrumb(dev);
490 return 0;
491 }
492
i915_dispatch_batchbuffer(struct drm_device * dev,drm_i915_batchbuffer_t * batch,struct drm_clip_rect * cliprects)493 static int i915_dispatch_batchbuffer(struct drm_device *dev,
494 drm_i915_batchbuffer_t *batch,
495 struct drm_clip_rect *cliprects)
496 {
497 struct drm_i915_private *dev_priv = dev->dev_private;
498 int nbox = batch->num_cliprects;
499 int i, count, ret;
500
501 if ((batch->start | batch->used) & 0x7) {
502 DRM_ERROR("alignment");
503 return -EINVAL;
504 }
505
506 i915_kernel_lost_context(dev);
507
508 count = nbox ? nbox : 1;
509 for (i = 0; i < count; i++) {
510 if (i < nbox) {
511 ret = i915_emit_box(dev, &cliprects[i],
512 batch->DR1, batch->DR4);
513 if (ret)
514 return ret;
515 }
516
517 if (!IS_I830(dev) && !IS_845G(dev)) {
518 ret = BEGIN_LP_RING(2);
519 if (ret)
520 return ret;
521
522 if (INTEL_INFO(dev)->gen >= 4) {
523 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
524 OUT_RING(batch->start);
525 } else {
526 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
527 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
528 }
529 } else {
530 ret = BEGIN_LP_RING(4);
531 if (ret)
532 return ret;
533
534 OUT_RING(MI_BATCH_BUFFER);
535 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
536 OUT_RING(batch->start + batch->used - 4);
537 OUT_RING(0);
538 }
539 ADVANCE_LP_RING();
540 }
541
542
543 if (IS_G4X(dev) || IS_GEN5(dev)) {
544 if (BEGIN_LP_RING(2) == 0) {
545 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
546 OUT_RING(MI_NOOP);
547 ADVANCE_LP_RING();
548 }
549 }
550
551 i915_emit_breadcrumb(dev);
552 return 0;
553 }
554
i915_dispatch_flip(struct drm_device * dev)555 static int i915_dispatch_flip(struct drm_device *dev)
556 {
557 struct drm_i915_private *dev_priv = dev->dev_private;
558 struct drm_i915_master_private *master_priv =
559 dev->primary->master->driver_priv;
560 int ret;
561
562 if (!master_priv->sarea_priv)
563 return -EINVAL;
564
565 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
566 __func__,
567 dev_priv->dri1.current_page,
568 master_priv->sarea_priv->pf_current_page);
569
570 i915_kernel_lost_context(dev);
571
572 ret = BEGIN_LP_RING(10);
573 if (ret)
574 return ret;
575
576 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
577 OUT_RING(0);
578
579 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
580 OUT_RING(0);
581 if (dev_priv->dri1.current_page == 0) {
582 OUT_RING(dev_priv->dri1.back_offset);
583 dev_priv->dri1.current_page = 1;
584 } else {
585 OUT_RING(dev_priv->dri1.front_offset);
586 dev_priv->dri1.current_page = 0;
587 }
588 OUT_RING(0);
589
590 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
591 OUT_RING(0);
592
593 ADVANCE_LP_RING();
594
595 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
596
597 if (BEGIN_LP_RING(4) == 0) {
598 OUT_RING(MI_STORE_DWORD_INDEX);
599 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
600 OUT_RING(dev_priv->dri1.counter);
601 OUT_RING(0);
602 ADVANCE_LP_RING();
603 }
604
605 master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
606 return 0;
607 }
608
i915_quiescent(struct drm_device * dev)609 static int i915_quiescent(struct drm_device *dev)
610 {
611 i915_kernel_lost_context(dev);
612 return intel_ring_idle(LP_RING(dev->dev_private));
613 }
614
i915_flush_ioctl(struct drm_device * dev,void * data,struct drm_file * file_priv)615 static int i915_flush_ioctl(struct drm_device *dev, void *data,
616 struct drm_file *file_priv)
617 {
618 int ret;
619
620 if (drm_core_check_feature(dev, DRIVER_MODESET))
621 return -ENODEV;
622
623 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
624
625 mutex_lock(&dev->struct_mutex);
626 ret = i915_quiescent(dev);
627 mutex_unlock(&dev->struct_mutex);
628
629 return ret;
630 }
631
i915_batchbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)632 static int i915_batchbuffer(struct drm_device *dev, void *data,
633 struct drm_file *file_priv)
634 {
635 struct drm_i915_private *dev_priv = dev->dev_private;
636 struct drm_i915_master_private *master_priv;
637 drm_i915_sarea_t *sarea_priv;
638 drm_i915_batchbuffer_t *batch = data;
639 int ret;
640 struct drm_clip_rect *cliprects = NULL;
641
642 if (drm_core_check_feature(dev, DRIVER_MODESET))
643 return -ENODEV;
644
645 master_priv = dev->primary->master->driver_priv;
646 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
647
648 if (!dev_priv->dri1.allow_batchbuffer) {
649 DRM_ERROR("Batchbuffer ioctl disabled\n");
650 return -EINVAL;
651 }
652
653 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
654 batch->start, batch->used, batch->num_cliprects);
655
656 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
657
658 if (batch->num_cliprects < 0)
659 return -EINVAL;
660
661 if (batch->num_cliprects) {
662 cliprects = kcalloc(batch->num_cliprects,
663 sizeof(*cliprects),
664 GFP_KERNEL);
665 if (cliprects == NULL)
666 return -ENOMEM;
667
668 ret = copy_from_user(cliprects, batch->cliprects,
669 batch->num_cliprects *
670 sizeof(struct drm_clip_rect));
671 if (ret != 0) {
672 ret = -EFAULT;
673 goto fail_free;
674 }
675 }
676
677 mutex_lock(&dev->struct_mutex);
678 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
679 mutex_unlock(&dev->struct_mutex);
680
681 if (sarea_priv)
682 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
683
684 fail_free:
685 kfree(cliprects);
686
687 return ret;
688 }
689
i915_cmdbuffer(struct drm_device * dev,void * data,struct drm_file * file_priv)690 static int i915_cmdbuffer(struct drm_device *dev, void *data,
691 struct drm_file *file_priv)
692 {
693 struct drm_i915_private *dev_priv = dev->dev_private;
694 struct drm_i915_master_private *master_priv;
695 drm_i915_sarea_t *sarea_priv;
696 drm_i915_cmdbuffer_t *cmdbuf = data;
697 struct drm_clip_rect *cliprects = NULL;
698 void *batch_data;
699 int ret;
700
701 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
702 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
703
704 if (drm_core_check_feature(dev, DRIVER_MODESET))
705 return -ENODEV;
706
707 master_priv = dev->primary->master->driver_priv;
708 sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
709
710 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
711
712 if (cmdbuf->num_cliprects < 0)
713 return -EINVAL;
714
715 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
716 if (batch_data == NULL)
717 return -ENOMEM;
718
719 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
720 if (ret != 0) {
721 ret = -EFAULT;
722 goto fail_batch_free;
723 }
724
725 if (cmdbuf->num_cliprects) {
726 cliprects = kcalloc(cmdbuf->num_cliprects,
727 sizeof(*cliprects), GFP_KERNEL);
728 if (cliprects == NULL) {
729 ret = -ENOMEM;
730 goto fail_batch_free;
731 }
732
733 ret = copy_from_user(cliprects, cmdbuf->cliprects,
734 cmdbuf->num_cliprects *
735 sizeof(struct drm_clip_rect));
736 if (ret != 0) {
737 ret = -EFAULT;
738 goto fail_clip_free;
739 }
740 }
741
742 mutex_lock(&dev->struct_mutex);
743 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
744 mutex_unlock(&dev->struct_mutex);
745 if (ret) {
746 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
747 goto fail_clip_free;
748 }
749
750 if (sarea_priv)
751 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
752
753 fail_clip_free:
754 kfree(cliprects);
755 fail_batch_free:
756 kfree(batch_data);
757
758 return ret;
759 }
760
i915_emit_irq(struct drm_device * dev)761 static int i915_emit_irq(struct drm_device *dev)
762 {
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
765
766 i915_kernel_lost_context(dev);
767
768 DRM_DEBUG_DRIVER("\n");
769
770 dev_priv->dri1.counter++;
771 if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
772 dev_priv->dri1.counter = 1;
773 if (master_priv->sarea_priv)
774 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
775
776 if (BEGIN_LP_RING(4) == 0) {
777 OUT_RING(MI_STORE_DWORD_INDEX);
778 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
779 OUT_RING(dev_priv->dri1.counter);
780 OUT_RING(MI_USER_INTERRUPT);
781 ADVANCE_LP_RING();
782 }
783
784 return dev_priv->dri1.counter;
785 }
786
i915_wait_irq(struct drm_device * dev,int irq_nr)787 static int i915_wait_irq(struct drm_device *dev, int irq_nr)
788 {
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
791 int ret = 0;
792 struct intel_engine_cs *ring = LP_RING(dev_priv);
793
794 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
795 READ_BREADCRUMB(dev_priv));
796
797 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
798 if (master_priv->sarea_priv)
799 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
800 return 0;
801 }
802
803 if (master_priv->sarea_priv)
804 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
805
806 if (ring->irq_get(ring)) {
807 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
808 READ_BREADCRUMB(dev_priv) >= irq_nr);
809 ring->irq_put(ring);
810 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
811 ret = -EBUSY;
812
813 if (ret == -EBUSY) {
814 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
815 READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
816 }
817
818 return ret;
819 }
820
821 /* Needs the lock as it touches the ring.
822 */
i915_irq_emit(struct drm_device * dev,void * data,struct drm_file * file_priv)823 static int i915_irq_emit(struct drm_device *dev, void *data,
824 struct drm_file *file_priv)
825 {
826 struct drm_i915_private *dev_priv = dev->dev_private;
827 drm_i915_irq_emit_t *emit = data;
828 int result;
829
830 if (drm_core_check_feature(dev, DRIVER_MODESET))
831 return -ENODEV;
832
833 if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
834 DRM_ERROR("called with no initialization\n");
835 return -EINVAL;
836 }
837
838 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
839
840 mutex_lock(&dev->struct_mutex);
841 result = i915_emit_irq(dev);
842 mutex_unlock(&dev->struct_mutex);
843
844 if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
845 DRM_ERROR("copy_to_user\n");
846 return -EFAULT;
847 }
848
849 return 0;
850 }
851
852 /* Doesn't need the hardware lock.
853 */
i915_irq_wait(struct drm_device * dev,void * data,struct drm_file * file_priv)854 static int i915_irq_wait(struct drm_device *dev, void *data,
855 struct drm_file *file_priv)
856 {
857 struct drm_i915_private *dev_priv = dev->dev_private;
858 drm_i915_irq_wait_t *irqwait = data;
859
860 if (drm_core_check_feature(dev, DRIVER_MODESET))
861 return -ENODEV;
862
863 if (!dev_priv) {
864 DRM_ERROR("called with no initialization\n");
865 return -EINVAL;
866 }
867
868 return i915_wait_irq(dev, irqwait->irq_seq);
869 }
870
i915_vblank_pipe_get(struct drm_device * dev,void * data,struct drm_file * file_priv)871 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
872 struct drm_file *file_priv)
873 {
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 drm_i915_vblank_pipe_t *pipe = data;
876
877 if (drm_core_check_feature(dev, DRIVER_MODESET))
878 return -ENODEV;
879
880 if (!dev_priv) {
881 DRM_ERROR("called with no initialization\n");
882 return -EINVAL;
883 }
884
885 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
886
887 return 0;
888 }
889
890 /**
891 * Schedule buffer swap at given vertical blank.
892 */
i915_vblank_swap(struct drm_device * dev,void * data,struct drm_file * file_priv)893 static int i915_vblank_swap(struct drm_device *dev, void *data,
894 struct drm_file *file_priv)
895 {
896 /* The delayed swap mechanism was fundamentally racy, and has been
897 * removed. The model was that the client requested a delayed flip/swap
898 * from the kernel, then waited for vblank before continuing to perform
899 * rendering. The problem was that the kernel might wake the client
900 * up before it dispatched the vblank swap (since the lock has to be
901 * held while touching the ringbuffer), in which case the client would
902 * clear and start the next frame before the swap occurred, and
903 * flicker would occur in addition to likely missing the vblank.
904 *
905 * In the absence of this ioctl, userland falls back to a correct path
906 * of waiting for a vblank, then dispatching the swap on its own.
907 * Context switching to userland and back is plenty fast enough for
908 * meeting the requirements of vblank swapping.
909 */
910 return -EINVAL;
911 }
912
i915_flip_bufs(struct drm_device * dev,void * data,struct drm_file * file_priv)913 static int i915_flip_bufs(struct drm_device *dev, void *data,
914 struct drm_file *file_priv)
915 {
916 int ret;
917
918 if (drm_core_check_feature(dev, DRIVER_MODESET))
919 return -ENODEV;
920
921 DRM_DEBUG_DRIVER("%s\n", __func__);
922
923 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
924
925 mutex_lock(&dev->struct_mutex);
926 ret = i915_dispatch_flip(dev);
927 mutex_unlock(&dev->struct_mutex);
928
929 return ret;
930 }
931
i915_getparam(struct drm_device * dev,void * data,struct drm_file * file_priv)932 static int i915_getparam(struct drm_device *dev, void *data,
933 struct drm_file *file_priv)
934 {
935 struct drm_i915_private *dev_priv = dev->dev_private;
936 drm_i915_getparam_t *param = data;
937 int value;
938
939 if (!dev_priv) {
940 DRM_ERROR("called with no initialization\n");
941 return -EINVAL;
942 }
943
944 switch (param->param) {
945 case I915_PARAM_IRQ_ACTIVE:
946 value = dev->pdev->irq ? 1 : 0;
947 break;
948 case I915_PARAM_ALLOW_BATCHBUFFER:
949 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
950 break;
951 case I915_PARAM_LAST_DISPATCH:
952 value = READ_BREADCRUMB(dev_priv);
953 break;
954 case I915_PARAM_CHIPSET_ID:
955 value = dev->pdev->device;
956 break;
957 case I915_PARAM_HAS_GEM:
958 value = 1;
959 break;
960 case I915_PARAM_NUM_FENCES_AVAIL:
961 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
962 break;
963 case I915_PARAM_HAS_OVERLAY:
964 value = dev_priv->overlay ? 1 : 0;
965 break;
966 case I915_PARAM_HAS_PAGEFLIPPING:
967 value = 1;
968 break;
969 case I915_PARAM_HAS_EXECBUF2:
970 /* depends on GEM */
971 value = 1;
972 break;
973 case I915_PARAM_HAS_BSD:
974 value = intel_ring_initialized(&dev_priv->ring[VCS]);
975 break;
976 case I915_PARAM_HAS_BLT:
977 value = intel_ring_initialized(&dev_priv->ring[BCS]);
978 break;
979 case I915_PARAM_HAS_VEBOX:
980 value = intel_ring_initialized(&dev_priv->ring[VECS]);
981 break;
982 case I915_PARAM_HAS_RELAXED_FENCING:
983 value = 1;
984 break;
985 case I915_PARAM_HAS_COHERENT_RINGS:
986 value = 1;
987 break;
988 case I915_PARAM_HAS_EXEC_CONSTANTS:
989 value = INTEL_INFO(dev)->gen >= 4;
990 break;
991 case I915_PARAM_HAS_RELAXED_DELTA:
992 value = 1;
993 break;
994 case I915_PARAM_HAS_GEN7_SOL_RESET:
995 value = 1;
996 break;
997 case I915_PARAM_HAS_LLC:
998 value = HAS_LLC(dev);
999 break;
1000 case I915_PARAM_HAS_WT:
1001 value = HAS_WT(dev);
1002 break;
1003 case I915_PARAM_HAS_ALIASING_PPGTT:
1004 value = USES_PPGTT(dev);
1005 break;
1006 case I915_PARAM_HAS_WAIT_TIMEOUT:
1007 value = 1;
1008 break;
1009 case I915_PARAM_HAS_SEMAPHORES:
1010 value = i915_semaphore_is_enabled(dev);
1011 break;
1012 case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1013 value = 1;
1014 break;
1015 case I915_PARAM_HAS_SECURE_BATCHES:
1016 value = capable(CAP_SYS_ADMIN);
1017 break;
1018 case I915_PARAM_HAS_PINNED_BATCHES:
1019 value = 1;
1020 break;
1021 case I915_PARAM_HAS_EXEC_NO_RELOC:
1022 value = 1;
1023 break;
1024 case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1025 value = 1;
1026 break;
1027 case I915_PARAM_CMD_PARSER_VERSION:
1028 value = i915_cmd_parser_get_version();
1029 break;
1030 default:
1031 DRM_DEBUG("Unknown parameter %d\n", param->param);
1032 return -EINVAL;
1033 }
1034
1035 if (copy_to_user(param->value, &value, sizeof(int))) {
1036 DRM_ERROR("copy_to_user failed\n");
1037 return -EFAULT;
1038 }
1039
1040 return 0;
1041 }
1042
i915_setparam(struct drm_device * dev,void * data,struct drm_file * file_priv)1043 static int i915_setparam(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv)
1045 {
1046 struct drm_i915_private *dev_priv = dev->dev_private;
1047 drm_i915_setparam_t *param = data;
1048
1049 if (!dev_priv) {
1050 DRM_ERROR("called with no initialization\n");
1051 return -EINVAL;
1052 }
1053
1054 switch (param->param) {
1055 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1056 break;
1057 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1058 break;
1059 case I915_SETPARAM_ALLOW_BATCHBUFFER:
1060 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1061 break;
1062 case I915_SETPARAM_NUM_USED_FENCES:
1063 if (param->value > dev_priv->num_fence_regs ||
1064 param->value < 0)
1065 return -EINVAL;
1066 /* Userspace can use first N regs */
1067 dev_priv->fence_reg_start = param->value;
1068 break;
1069 default:
1070 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1071 param->param);
1072 return -EINVAL;
1073 }
1074
1075 return 0;
1076 }
1077
i915_set_status_page(struct drm_device * dev,void * data,struct drm_file * file_priv)1078 static int i915_set_status_page(struct drm_device *dev, void *data,
1079 struct drm_file *file_priv)
1080 {
1081 struct drm_i915_private *dev_priv = dev->dev_private;
1082 drm_i915_hws_addr_t *hws = data;
1083 struct intel_engine_cs *ring;
1084
1085 if (drm_core_check_feature(dev, DRIVER_MODESET))
1086 return -ENODEV;
1087
1088 if (!I915_NEED_GFX_HWS(dev))
1089 return -EINVAL;
1090
1091 if (!dev_priv) {
1092 DRM_ERROR("called with no initialization\n");
1093 return -EINVAL;
1094 }
1095
1096 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1097 WARN(1, "tried to set status page when mode setting active\n");
1098 return 0;
1099 }
1100
1101 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1102
1103 ring = LP_RING(dev_priv);
1104 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1105
1106 dev_priv->dri1.gfx_hws_cpu_addr =
1107 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1108 if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1109 i915_dma_cleanup(dev);
1110 ring->status_page.gfx_addr = 0;
1111 DRM_ERROR("can not ioremap virtual address for"
1112 " G33 hw status page\n");
1113 return -ENOMEM;
1114 }
1115
1116 memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1117 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1118
1119 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1120 ring->status_page.gfx_addr);
1121 DRM_DEBUG_DRIVER("load hws at %p\n",
1122 ring->status_page.page_addr);
1123 return 0;
1124 }
1125
i915_get_bridge_dev(struct drm_device * dev)1126 static int i915_get_bridge_dev(struct drm_device *dev)
1127 {
1128 struct drm_i915_private *dev_priv = dev->dev_private;
1129
1130 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1131 if (!dev_priv->bridge_dev) {
1132 DRM_ERROR("bridge device not found\n");
1133 return -1;
1134 }
1135 return 0;
1136 }
1137
1138 #define MCHBAR_I915 0x44
1139 #define MCHBAR_I965 0x48
1140 #define MCHBAR_SIZE (4*4096)
1141
1142 #define DEVEN_REG 0x54
1143 #define DEVEN_MCHBAR_EN (1 << 28)
1144
1145 /* Allocate space for the MCH regs if needed, return nonzero on error */
1146 static int
intel_alloc_mchbar_resource(struct drm_device * dev)1147 intel_alloc_mchbar_resource(struct drm_device *dev)
1148 {
1149 struct drm_i915_private *dev_priv = dev->dev_private;
1150 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1151 u32 temp_lo, temp_hi = 0;
1152 u64 mchbar_addr;
1153 int ret;
1154
1155 if (INTEL_INFO(dev)->gen >= 4)
1156 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1157 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1158 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1159
1160 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1161 #ifdef CONFIG_PNP
1162 if (mchbar_addr &&
1163 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1164 return 0;
1165 #endif
1166
1167 /* Get some space for it */
1168 dev_priv->mch_res.name = "i915 MCHBAR";
1169 dev_priv->mch_res.flags = IORESOURCE_MEM;
1170 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1171 &dev_priv->mch_res,
1172 MCHBAR_SIZE, MCHBAR_SIZE,
1173 PCIBIOS_MIN_MEM,
1174 0, pcibios_align_resource,
1175 dev_priv->bridge_dev);
1176 if (ret) {
1177 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1178 dev_priv->mch_res.start = 0;
1179 return ret;
1180 }
1181
1182 if (INTEL_INFO(dev)->gen >= 4)
1183 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1184 upper_32_bits(dev_priv->mch_res.start));
1185
1186 pci_write_config_dword(dev_priv->bridge_dev, reg,
1187 lower_32_bits(dev_priv->mch_res.start));
1188 return 0;
1189 }
1190
1191 /* Setup MCHBAR if possible, return true if we should disable it again */
1192 static void
intel_setup_mchbar(struct drm_device * dev)1193 intel_setup_mchbar(struct drm_device *dev)
1194 {
1195 struct drm_i915_private *dev_priv = dev->dev_private;
1196 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1197 u32 temp;
1198 bool enabled;
1199
1200 if (IS_VALLEYVIEW(dev))
1201 return;
1202
1203 dev_priv->mchbar_need_disable = false;
1204
1205 if (IS_I915G(dev) || IS_I915GM(dev)) {
1206 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1207 enabled = !!(temp & DEVEN_MCHBAR_EN);
1208 } else {
1209 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1210 enabled = temp & 1;
1211 }
1212
1213 /* If it's already enabled, don't have to do anything */
1214 if (enabled)
1215 return;
1216
1217 if (intel_alloc_mchbar_resource(dev))
1218 return;
1219
1220 dev_priv->mchbar_need_disable = true;
1221
1222 /* Space is allocated or reserved, so enable it. */
1223 if (IS_I915G(dev) || IS_I915GM(dev)) {
1224 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1225 temp | DEVEN_MCHBAR_EN);
1226 } else {
1227 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1228 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1229 }
1230 }
1231
1232 static void
intel_teardown_mchbar(struct drm_device * dev)1233 intel_teardown_mchbar(struct drm_device *dev)
1234 {
1235 struct drm_i915_private *dev_priv = dev->dev_private;
1236 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1237 u32 temp;
1238
1239 if (dev_priv->mchbar_need_disable) {
1240 if (IS_I915G(dev) || IS_I915GM(dev)) {
1241 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1242 temp &= ~DEVEN_MCHBAR_EN;
1243 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1244 } else {
1245 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1246 temp &= ~1;
1247 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1248 }
1249 }
1250
1251 if (dev_priv->mch_res.start)
1252 release_resource(&dev_priv->mch_res);
1253 }
1254
1255 /* true = enable decode, false = disable decoder */
i915_vga_set_decode(void * cookie,bool state)1256 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1257 {
1258 struct drm_device *dev = cookie;
1259
1260 intel_modeset_vga_set_state(dev, state);
1261 if (state)
1262 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1263 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1264 else
1265 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1266 }
1267
i915_switcheroo_set_state(struct pci_dev * pdev,enum vga_switcheroo_state state)1268 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1269 {
1270 struct drm_device *dev = pci_get_drvdata(pdev);
1271 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1272
1273 if (state == VGA_SWITCHEROO_ON) {
1274 pr_info("switched on\n");
1275 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1276 /* i915 resume handler doesn't set to D0 */
1277 pci_set_power_state(dev->pdev, PCI_D0);
1278 i915_resume(dev);
1279 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1280 } else {
1281 pr_err("switched off\n");
1282 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1283 i915_suspend(dev, pmm);
1284 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1285 }
1286 }
1287
i915_switcheroo_can_switch(struct pci_dev * pdev)1288 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1289 {
1290 struct drm_device *dev = pci_get_drvdata(pdev);
1291
1292 /*
1293 * FIXME: open_count is protected by drm_global_mutex but that would lead to
1294 * locking inversion with the driver load path. And the access here is
1295 * completely racy anyway. So don't bother with locking for now.
1296 */
1297 return dev->open_count == 0;
1298 }
1299
1300 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1301 .set_gpu_state = i915_switcheroo_set_state,
1302 .reprobe = NULL,
1303 .can_switch = i915_switcheroo_can_switch,
1304 };
1305
i915_load_modeset_init(struct drm_device * dev)1306 static int i915_load_modeset_init(struct drm_device *dev)
1307 {
1308 struct drm_i915_private *dev_priv = dev->dev_private;
1309 int ret;
1310
1311 ret = intel_parse_bios(dev);
1312 if (ret)
1313 DRM_INFO("failed to find VBIOS tables\n");
1314
1315 /* If we have > 1 VGA cards, then we need to arbitrate access
1316 * to the common VGA resources.
1317 *
1318 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1319 * then we do not take part in VGA arbitration and the
1320 * vga_client_register() fails with -ENODEV.
1321 */
1322 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1323 if (ret && ret != -ENODEV)
1324 goto out;
1325
1326 intel_register_dsm_handler();
1327
1328 ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1329 if (ret)
1330 goto cleanup_vga_client;
1331
1332 /* Initialise stolen first so that we may reserve preallocated
1333 * objects for the BIOS to KMS transition.
1334 */
1335 ret = i915_gem_init_stolen(dev);
1336 if (ret)
1337 goto cleanup_vga_switcheroo;
1338
1339 intel_power_domains_init_hw(dev_priv);
1340
1341 /*
1342 * We enable some interrupt sources in our postinstall hooks, so mark
1343 * interrupts as enabled _before_ actually enabling them to avoid
1344 * special cases in our ordering checks.
1345 */
1346 dev_priv->pm._irqs_disabled = false;
1347
1348 ret = drm_irq_install(dev, dev->pdev->irq);
1349 if (ret)
1350 goto cleanup_gem_stolen;
1351
1352 /* Important: The output setup functions called by modeset_init need
1353 * working irqs for e.g. gmbus and dp aux transfers. */
1354 intel_modeset_init(dev);
1355
1356 ret = i915_gem_init(dev);
1357 if (ret)
1358 goto cleanup_irq;
1359
1360 intel_modeset_gem_init(dev);
1361
1362 /* Always safe in the mode setting case. */
1363 /* FIXME: do pre/post-mode set stuff in core KMS code */
1364 dev->vblank_disable_allowed = true;
1365 if (INTEL_INFO(dev)->num_pipes == 0)
1366 return 0;
1367
1368 ret = intel_fbdev_init(dev);
1369 if (ret)
1370 goto cleanup_gem;
1371
1372 /* Only enable hotplug handling once the fbdev is fully set up. */
1373 intel_hpd_init(dev);
1374
1375 /*
1376 * Some ports require correctly set-up hpd registers for detection to
1377 * work properly (leading to ghost connected connector status), e.g. VGA
1378 * on gm45. Hence we can only set up the initial fbdev config after hpd
1379 * irqs are fully enabled. Now we should scan for the initial config
1380 * only once hotplug handling is enabled, but due to screwed-up locking
1381 * around kms/fbdev init we can't protect the fdbev initial config
1382 * scanning against hotplug events. Hence do this first and ignore the
1383 * tiny window where we will loose hotplug notifactions.
1384 */
1385 async_schedule(intel_fbdev_initial_config, dev_priv);
1386
1387 drm_kms_helper_poll_init(dev);
1388
1389 return 0;
1390
1391 cleanup_gem:
1392 mutex_lock(&dev->struct_mutex);
1393 i915_gem_cleanup_ringbuffer(dev);
1394 i915_gem_context_fini(dev);
1395 mutex_unlock(&dev->struct_mutex);
1396 cleanup_irq:
1397 drm_irq_uninstall(dev);
1398 cleanup_gem_stolen:
1399 i915_gem_cleanup_stolen(dev);
1400 cleanup_vga_switcheroo:
1401 vga_switcheroo_unregister_client(dev->pdev);
1402 cleanup_vga_client:
1403 vga_client_register(dev->pdev, NULL, NULL, NULL);
1404 out:
1405 return ret;
1406 }
1407
i915_master_create(struct drm_device * dev,struct drm_master * master)1408 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1409 {
1410 struct drm_i915_master_private *master_priv;
1411
1412 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1413 if (!master_priv)
1414 return -ENOMEM;
1415
1416 master->driver_priv = master_priv;
1417 return 0;
1418 }
1419
i915_master_destroy(struct drm_device * dev,struct drm_master * master)1420 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1421 {
1422 struct drm_i915_master_private *master_priv = master->driver_priv;
1423
1424 if (!master_priv)
1425 return;
1426
1427 kfree(master_priv);
1428
1429 master->driver_priv = NULL;
1430 }
1431
1432 #if IS_ENABLED(CONFIG_FB)
i915_kick_out_firmware_fb(struct drm_i915_private * dev_priv)1433 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1434 {
1435 struct apertures_struct *ap;
1436 struct pci_dev *pdev = dev_priv->dev->pdev;
1437 bool primary;
1438 int ret;
1439
1440 ap = alloc_apertures(1);
1441 if (!ap)
1442 return -ENOMEM;
1443
1444 ap->ranges[0].base = dev_priv->gtt.mappable_base;
1445 ap->ranges[0].size = dev_priv->gtt.mappable_end;
1446
1447 primary =
1448 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1449
1450 ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1451
1452 kfree(ap);
1453
1454 return ret;
1455 }
1456 #else
i915_kick_out_firmware_fb(struct drm_i915_private * dev_priv)1457 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1458 {
1459 return 0;
1460 }
1461 #endif
1462
1463 #if !defined(CONFIG_VGA_CONSOLE)
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)1464 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1465 {
1466 return 0;
1467 }
1468 #elif !defined(CONFIG_DUMMY_CONSOLE)
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)1469 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1470 {
1471 return -ENODEV;
1472 }
1473 #else
i915_kick_out_vgacon(struct drm_i915_private * dev_priv)1474 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1475 {
1476 int ret = 0;
1477
1478 DRM_INFO("Replacing VGA console driver\n");
1479
1480 console_lock();
1481 if (con_is_bound(&vga_con))
1482 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1483 if (ret == 0) {
1484 ret = do_unregister_con_driver(&vga_con);
1485
1486 /* Ignore "already unregistered". */
1487 if (ret == -ENODEV)
1488 ret = 0;
1489 }
1490 console_unlock();
1491
1492 return ret;
1493 }
1494 #endif
1495
i915_dump_device_info(struct drm_i915_private * dev_priv)1496 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1497 {
1498 const struct intel_device_info *info = &dev_priv->info;
1499
1500 #define PRINT_S(name) "%s"
1501 #define SEP_EMPTY
1502 #define PRINT_FLAG(name) info->name ? #name "," : ""
1503 #define SEP_COMMA ,
1504 DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
1505 DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1506 info->gen,
1507 dev_priv->dev->pdev->device,
1508 dev_priv->dev->pdev->revision,
1509 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1510 #undef PRINT_S
1511 #undef SEP_EMPTY
1512 #undef PRINT_FLAG
1513 #undef SEP_COMMA
1514 }
1515
1516 /*
1517 * Determine various intel_device_info fields at runtime.
1518 *
1519 * Use it when either:
1520 * - it's judged too laborious to fill n static structures with the limit
1521 * when a simple if statement does the job,
1522 * - run-time checks (eg read fuse/strap registers) are needed.
1523 *
1524 * This function needs to be called:
1525 * - after the MMIO has been setup as we are reading registers,
1526 * - after the PCH has been detected,
1527 * - before the first usage of the fields it can tweak.
1528 */
intel_device_info_runtime_init(struct drm_device * dev)1529 static void intel_device_info_runtime_init(struct drm_device *dev)
1530 {
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 struct intel_device_info *info;
1533 enum pipe pipe;
1534
1535 info = (struct intel_device_info *)&dev_priv->info;
1536
1537 if (IS_VALLEYVIEW(dev))
1538 for_each_pipe(dev_priv, pipe)
1539 info->num_sprites[pipe] = 2;
1540 else
1541 for_each_pipe(dev_priv, pipe)
1542 info->num_sprites[pipe] = 1;
1543
1544 if (i915.disable_display) {
1545 DRM_INFO("Display disabled (module parameter)\n");
1546 info->num_pipes = 0;
1547 } else if (info->num_pipes > 0 &&
1548 (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1549 !IS_VALLEYVIEW(dev)) {
1550 u32 fuse_strap = I915_READ(FUSE_STRAP);
1551 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1552
1553 /*
1554 * SFUSE_STRAP is supposed to have a bit signalling the display
1555 * is fused off. Unfortunately it seems that, at least in
1556 * certain cases, fused off display means that PCH display
1557 * reads don't land anywhere. In that case, we read 0s.
1558 *
1559 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1560 * should be set when taking over after the firmware.
1561 */
1562 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1563 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1564 (dev_priv->pch_type == PCH_CPT &&
1565 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1566 DRM_INFO("Display fused off, disabling\n");
1567 info->num_pipes = 0;
1568 }
1569 }
1570 }
1571
1572 /**
1573 * i915_driver_load - setup chip and create an initial config
1574 * @dev: DRM device
1575 * @flags: startup flags
1576 *
1577 * The driver load routine has to do several things:
1578 * - drive output discovery via intel_modeset_init()
1579 * - initialize the memory manager
1580 * - allocate initial config memory
1581 * - setup the DRM framebuffer with the allocated memory
1582 */
i915_driver_load(struct drm_device * dev,unsigned long flags)1583 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1584 {
1585 struct drm_i915_private *dev_priv;
1586 struct intel_device_info *info, *device_info;
1587 int ret = 0, mmio_bar, mmio_size;
1588 uint32_t aperture_size;
1589
1590 info = (struct intel_device_info *) flags;
1591
1592 /* Refuse to load on gen6+ without kms enabled. */
1593 if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1594 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1595 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1596 return -ENODEV;
1597 }
1598
1599 /* UMS needs agp support. */
1600 if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1601 return -EINVAL;
1602
1603 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1604 if (dev_priv == NULL)
1605 return -ENOMEM;
1606
1607 dev->dev_private = dev_priv;
1608 dev_priv->dev = dev;
1609
1610 /* Setup the write-once "constant" device info */
1611 device_info = (struct intel_device_info *)&dev_priv->info;
1612 memcpy(device_info, info, sizeof(dev_priv->info));
1613 device_info->device_id = dev->pdev->device;
1614
1615 spin_lock_init(&dev_priv->irq_lock);
1616 spin_lock_init(&dev_priv->gpu_error.lock);
1617 spin_lock_init(&dev_priv->backlight_lock);
1618 spin_lock_init(&dev_priv->uncore.lock);
1619 spin_lock_init(&dev_priv->mm.object_stat_lock);
1620 spin_lock_init(&dev_priv->mmio_flip_lock);
1621 mutex_init(&dev_priv->dpio_lock);
1622 mutex_init(&dev_priv->modeset_restore_lock);
1623
1624 intel_pm_setup(dev);
1625
1626 intel_display_crc_init(dev);
1627
1628 i915_dump_device_info(dev_priv);
1629
1630 /* Not all pre-production machines fall into this category, only the
1631 * very first ones. Almost everything should work, except for maybe
1632 * suspend/resume. And we don't implement workarounds that affect only
1633 * pre-production machines. */
1634 if (IS_HSW_EARLY_SDV(dev))
1635 DRM_INFO("This is an early pre-production Haswell machine. "
1636 "It may not be fully functional.\n");
1637
1638 if (i915_get_bridge_dev(dev)) {
1639 ret = -EIO;
1640 goto free_priv;
1641 }
1642
1643 mmio_bar = IS_GEN2(dev) ? 1 : 0;
1644 /* Before gen4, the registers and the GTT are behind different BARs.
1645 * However, from gen4 onwards, the registers and the GTT are shared
1646 * in the same BAR, so we want to restrict this ioremap from
1647 * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1648 * the register BAR remains the same size for all the earlier
1649 * generations up to Ironlake.
1650 */
1651 if (info->gen < 5)
1652 mmio_size = 512*1024;
1653 else
1654 mmio_size = 2*1024*1024;
1655
1656 dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1657 if (!dev_priv->regs) {
1658 DRM_ERROR("failed to map registers\n");
1659 ret = -EIO;
1660 goto put_bridge;
1661 }
1662
1663 /* This must be called before any calls to HAS_PCH_* */
1664 intel_detect_pch(dev);
1665
1666 intel_uncore_init(dev);
1667
1668 ret = i915_gem_gtt_init(dev);
1669 if (ret)
1670 goto out_regs;
1671
1672 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1673 /* WARNING: Apparently we must kick fbdev drivers before vgacon,
1674 * otherwise the vga fbdev driver falls over. */
1675 ret = i915_kick_out_firmware_fb(dev_priv);
1676 if (ret) {
1677 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1678 goto out_gtt;
1679 }
1680
1681 ret = i915_kick_out_vgacon(dev_priv);
1682 if (ret) {
1683 DRM_ERROR("failed to remove conflicting VGA console\n");
1684 goto out_gtt;
1685 }
1686 }
1687
1688 pci_set_master(dev->pdev);
1689
1690 /* overlay on gen2 is broken and can't address above 1G */
1691 if (IS_GEN2(dev))
1692 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1693
1694 /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1695 * using 32bit addressing, overwriting memory if HWS is located
1696 * above 4GB.
1697 *
1698 * The documentation also mentions an issue with undefined
1699 * behaviour if any general state is accessed within a page above 4GB,
1700 * which also needs to be handled carefully.
1701 */
1702 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1703 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1704
1705 aperture_size = dev_priv->gtt.mappable_end;
1706
1707 dev_priv->gtt.mappable =
1708 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1709 aperture_size);
1710 if (dev_priv->gtt.mappable == NULL) {
1711 ret = -EIO;
1712 goto out_gtt;
1713 }
1714
1715 dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1716 aperture_size);
1717
1718 /* The i915 workqueue is primarily used for batched retirement of
1719 * requests (and thus managing bo) once the task has been completed
1720 * by the GPU. i915_gem_retire_requests() is called directly when we
1721 * need high-priority retirement, such as waiting for an explicit
1722 * bo.
1723 *
1724 * It is also used for periodic low-priority events, such as
1725 * idle-timers and recording error state.
1726 *
1727 * All tasks on the workqueue are expected to acquire the dev mutex
1728 * so there is no point in running more than one instance of the
1729 * workqueue at any time. Use an ordered one.
1730 */
1731 dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1732 if (dev_priv->wq == NULL) {
1733 DRM_ERROR("Failed to create our workqueue.\n");
1734 ret = -ENOMEM;
1735 goto out_mtrrfree;
1736 }
1737
1738 dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1739 if (dev_priv->dp_wq == NULL) {
1740 DRM_ERROR("Failed to create our dp workqueue.\n");
1741 ret = -ENOMEM;
1742 goto out_freewq;
1743 }
1744
1745 intel_irq_init(dev);
1746 intel_uncore_sanitize(dev);
1747
1748 /* Try to make sure MCHBAR is enabled before poking at it */
1749 intel_setup_mchbar(dev);
1750 intel_setup_gmbus(dev);
1751 intel_opregion_setup(dev);
1752
1753 intel_setup_bios(dev);
1754
1755 i915_gem_load(dev);
1756
1757 /* On the 945G/GM, the chipset reports the MSI capability on the
1758 * integrated graphics even though the support isn't actually there
1759 * according to the published specs. It doesn't appear to function
1760 * correctly in testing on 945G.
1761 * This may be a side effect of MSI having been made available for PEG
1762 * and the registers being closely associated.
1763 *
1764 * According to chipset errata, on the 965GM, MSI interrupts may
1765 * be lost or delayed, but we use them anyways to avoid
1766 * stuck interrupts on some machines.
1767 */
1768 if (!IS_I945G(dev) && !IS_I945GM(dev))
1769 pci_enable_msi(dev->pdev);
1770
1771 intel_device_info_runtime_init(dev);
1772
1773 if (INTEL_INFO(dev)->num_pipes) {
1774 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1775 if (ret)
1776 goto out_gem_unload;
1777 }
1778
1779 intel_power_domains_init(dev_priv);
1780
1781 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1782 ret = i915_load_modeset_init(dev);
1783 if (ret < 0) {
1784 DRM_ERROR("failed to init modeset\n");
1785 goto out_power_well;
1786 }
1787 } else {
1788 /* Start out suspended in ums mode. */
1789 dev_priv->ums.mm_suspended = 1;
1790 }
1791
1792 i915_setup_sysfs(dev);
1793
1794 if (INTEL_INFO(dev)->num_pipes) {
1795 /* Must be done after probing outputs */
1796 intel_opregion_init(dev);
1797 acpi_video_register();
1798 }
1799
1800 if (IS_GEN5(dev))
1801 intel_gpu_ips_init(dev_priv);
1802
1803 intel_init_runtime_pm(dev_priv);
1804
1805 return 0;
1806
1807 out_power_well:
1808 intel_power_domains_remove(dev_priv);
1809 drm_vblank_cleanup(dev);
1810 out_gem_unload:
1811 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1812 unregister_shrinker(&dev_priv->mm.shrinker);
1813
1814 if (dev->pdev->msi_enabled)
1815 pci_disable_msi(dev->pdev);
1816
1817 intel_teardown_gmbus(dev);
1818 intel_teardown_mchbar(dev);
1819 pm_qos_remove_request(&dev_priv->pm_qos);
1820 destroy_workqueue(dev_priv->dp_wq);
1821 out_freewq:
1822 destroy_workqueue(dev_priv->wq);
1823 out_mtrrfree:
1824 arch_phys_wc_del(dev_priv->gtt.mtrr);
1825 io_mapping_free(dev_priv->gtt.mappable);
1826 out_gtt:
1827 i915_global_gtt_cleanup(dev);
1828 out_regs:
1829 intel_uncore_fini(dev);
1830 pci_iounmap(dev->pdev, dev_priv->regs);
1831 put_bridge:
1832 pci_dev_put(dev_priv->bridge_dev);
1833 free_priv:
1834 if (dev_priv->slab)
1835 kmem_cache_destroy(dev_priv->slab);
1836 kfree(dev_priv);
1837 return ret;
1838 }
1839
i915_driver_unload(struct drm_device * dev)1840 int i915_driver_unload(struct drm_device *dev)
1841 {
1842 struct drm_i915_private *dev_priv = dev->dev_private;
1843 int ret;
1844
1845 ret = i915_gem_suspend(dev);
1846 if (ret) {
1847 DRM_ERROR("failed to idle hardware: %d\n", ret);
1848 return ret;
1849 }
1850
1851 intel_fini_runtime_pm(dev_priv);
1852
1853 intel_gpu_ips_teardown();
1854
1855 /* The i915.ko module is still not prepared to be loaded when
1856 * the power well is not enabled, so just enable it in case
1857 * we're going to unload/reload. */
1858 intel_display_set_init_power(dev_priv, true);
1859 intel_power_domains_remove(dev_priv);
1860
1861 i915_teardown_sysfs(dev);
1862
1863 WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1864 unregister_shrinker(&dev_priv->mm.shrinker);
1865
1866 io_mapping_free(dev_priv->gtt.mappable);
1867 arch_phys_wc_del(dev_priv->gtt.mtrr);
1868
1869 acpi_video_unregister();
1870
1871 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1872 intel_fbdev_fini(dev);
1873 intel_modeset_cleanup(dev);
1874
1875 /*
1876 * free the memory space allocated for the child device
1877 * config parsed from VBT
1878 */
1879 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1880 kfree(dev_priv->vbt.child_dev);
1881 dev_priv->vbt.child_dev = NULL;
1882 dev_priv->vbt.child_dev_num = 0;
1883 }
1884
1885 vga_switcheroo_unregister_client(dev->pdev);
1886 vga_client_register(dev->pdev, NULL, NULL, NULL);
1887 }
1888
1889 /* Free error state after interrupts are fully disabled. */
1890 del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1891 cancel_work_sync(&dev_priv->gpu_error.work);
1892 i915_destroy_error_state(dev);
1893
1894 if (dev->pdev->msi_enabled)
1895 pci_disable_msi(dev->pdev);
1896
1897 intel_opregion_fini(dev);
1898
1899 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1900 /* Flush any outstanding unpin_work. */
1901 flush_workqueue(dev_priv->wq);
1902
1903 mutex_lock(&dev->struct_mutex);
1904 i915_gem_cleanup_ringbuffer(dev);
1905 i915_gem_context_fini(dev);
1906 mutex_unlock(&dev->struct_mutex);
1907 i915_gem_cleanup_stolen(dev);
1908
1909 if (!I915_NEED_GFX_HWS(dev))
1910 i915_free_hws(dev);
1911 }
1912
1913 drm_vblank_cleanup(dev);
1914
1915 intel_teardown_gmbus(dev);
1916 intel_teardown_mchbar(dev);
1917
1918 destroy_workqueue(dev_priv->dp_wq);
1919 destroy_workqueue(dev_priv->wq);
1920 pm_qos_remove_request(&dev_priv->pm_qos);
1921
1922 i915_global_gtt_cleanup(dev);
1923
1924 intel_uncore_fini(dev);
1925 if (dev_priv->regs != NULL)
1926 pci_iounmap(dev->pdev, dev_priv->regs);
1927
1928 if (dev_priv->slab)
1929 kmem_cache_destroy(dev_priv->slab);
1930
1931 pci_dev_put(dev_priv->bridge_dev);
1932 kfree(dev_priv);
1933
1934 return 0;
1935 }
1936
i915_driver_open(struct drm_device * dev,struct drm_file * file)1937 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1938 {
1939 int ret;
1940
1941 ret = i915_gem_open(dev, file);
1942 if (ret)
1943 return ret;
1944
1945 return 0;
1946 }
1947
1948 /**
1949 * i915_driver_lastclose - clean up after all DRM clients have exited
1950 * @dev: DRM device
1951 *
1952 * Take care of cleaning up after all DRM clients have exited. In the
1953 * mode setting case, we want to restore the kernel's initial mode (just
1954 * in case the last client left us in a bad state).
1955 *
1956 * Additionally, in the non-mode setting case, we'll tear down the GTT
1957 * and DMA structures, since the kernel won't be using them, and clea
1958 * up any GEM state.
1959 */
i915_driver_lastclose(struct drm_device * dev)1960 void i915_driver_lastclose(struct drm_device *dev)
1961 {
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963
1964 /* On gen6+ we refuse to init without kms enabled, but then the drm core
1965 * goes right around and calls lastclose. Check for this and don't clean
1966 * up anything. */
1967 if (!dev_priv)
1968 return;
1969
1970 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1971 intel_fbdev_restore_mode(dev);
1972 vga_switcheroo_process_delayed_switch();
1973 return;
1974 }
1975
1976 i915_gem_lastclose(dev);
1977
1978 i915_dma_cleanup(dev);
1979 }
1980
i915_driver_preclose(struct drm_device * dev,struct drm_file * file)1981 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1982 {
1983 mutex_lock(&dev->struct_mutex);
1984 i915_gem_context_close(dev, file);
1985 i915_gem_release(dev, file);
1986 mutex_unlock(&dev->struct_mutex);
1987
1988 if (drm_core_check_feature(dev, DRIVER_MODESET))
1989 intel_modeset_preclose(dev, file);
1990 }
1991
i915_driver_postclose(struct drm_device * dev,struct drm_file * file)1992 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1993 {
1994 struct drm_i915_file_private *file_priv = file->driver_priv;
1995
1996 if (file_priv && file_priv->bsd_ring)
1997 file_priv->bsd_ring = NULL;
1998 kfree(file_priv);
1999 }
2000
2001 const struct drm_ioctl_desc i915_ioctls[] = {
2002 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2003 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2004 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2005 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2006 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2007 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2008 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2009 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2010 DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2011 DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2012 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2013 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2014 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2015 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2016 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2017 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2018 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2019 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2020 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2021 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2022 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2023 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2024 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2025 DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2026 DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2027 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2028 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2029 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2030 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2031 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2032 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2033 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2034 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2035 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2036 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2037 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2038 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2039 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2040 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2041 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2042 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2043 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2044 DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2045 DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2046 DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2047 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2048 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2049 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2050 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2051 DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2052 };
2053
2054 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2055
2056 /*
2057 * This is really ugly: Because old userspace abused the linux agp interface to
2058 * manage the gtt, we need to claim that all intel devices are agp. For
2059 * otherwise the drm core refuses to initialize the agp support code.
2060 */
i915_driver_device_is_agp(struct drm_device * dev)2061 int i915_driver_device_is_agp(struct drm_device *dev)
2062 {
2063 return 1;
2064 }
2065