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Searched refs:MPLL_SS1 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h110 #define MPLL_SS1 0x85c macro
Drv740_dpm.c311 pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1); in rv740_read_clock_registers()
Dnid.h676 #define MPLL_SS1 0x85c macro
Dsid.h588 #define MPLL_SS1 0x2bcc macro
Dcikd.h713 #define MPLL_SS1 0x2bcc macro
Devergreend.h225 #define MPLL_SS1 0x85c macro
Dni_dpm.c1195 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ni_read_clock_registers()
Dci_dpm.c1455 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
Dsi_dpm.c3564 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in si_read_clock_registers()