| /drivers/tty/serial/ |
| D | pmac_zilog.c | 186 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
187 write_zsreg(uap, R0, RES_EXT_INT); in pmz_load_zsregs()
254 write_zsreg(uap, R0, ERR_RES); in pmz_receive_chars()
328 ch = read_zsreg(uap, R0); in pmz_receive_chars()
344 status = read_zsreg(uap, R0); in pmz_status_handle()
345 write_zsreg(uap, R0, RES_EXT_INT); in pmz_status_handle()
378 unsigned char status = read_zsreg(uap, R0); in pmz_transmit_chars()
447 write_zsreg(uap, R0, RES_Tx_P); in pmz_transmit_chars()
477 write_zsreg(uap_a, R0, RES_H_IUS); in pmz_interrupt()
502 write_zsreg(uap_b, R0, RES_H_IUS); in pmz_interrupt()
[all …]
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| D | zs.c | 235 while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops) in zs_receive_drain()
245 while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) { in zs_transmit_drain()
327 status_a = read_zsreg(zport_a, R0); in zs_raw_get_ab_mctrl()
328 status_b = read_zsreg(zport_b, R0); in zs_raw_get_ab_mctrl()
424 write_zsreg(zport, R0, RES_Tx_P); in zs_raw_stop_tx()
501 write_zsreg(zport_a, R0, RES_EXT_INT); in zs_enable_ms()
550 avail = read_zsreg(zport, R0) & Rx_CH_AV; in zs_receive_chars()
575 write_zsreg(zport, R0, ERR_RES); in zs_receive_chars()
659 status = read_zsreg(zport, R0); in zs_status_handle()
696 write_zsreg(zport, R0, RES_EXT_INT); in zs_status_handle()
[all …]
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| D | zs.h | 59 #define R0 0 /* Register selects */ macro
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| D | sunzilog.h | 30 #define R0 0 /* Register selects */ macro
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| D | ip22zilog.h | 38 #define R0 0 /* Register selects */ macro
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| D | pmac_zilog.h | 126 #define R0 0 /* Register selects */ macro
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| D | ip22zilog.c | 219 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
220 write_zsreg(channel, R0, RES_EXT_INT); in __load_zsregs()
703 (void) read_zsreg(channel, R0); in __ip22zilog_reset()
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| D | sunzilog.c | 252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */ in __load_zsregs()
253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */ in __load_zsregs()
1337 (void) read_zsreg(channel, R0); in sunzilog_init_hw()
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| /drivers/net/hamradio/ |
| D | dmascc.c | 504 if (read_scc(priv, R0) & Tx_BUF_EMP) { in setup_adapter()
526 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
545 write_scc(priv, R0, RES_EXT_INT); in setup_adapter()
851 priv->rr0 = read_scc(priv, R0); in scc_open()
1011 write_scc(priv, R0, RES_EOM_L); in tx_on()
1020 while (read_scc(priv, R0) & Rx_CH_AV) in rx_on()
1048 write_scc(priv, R0, ERR_RES); in rx_on()
1109 write_scc(&info->priv[0], R0, RES_H_IUS); in z8530_isr()
1164 write_scc(priv, R0, ERR_RES); in rx_isr()
1169 while (read_scc(priv, R0) & Rx_CH_AV) { in rx_isr()
[all …]
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| D | scc.c | 399 OutReg(scc->ctrl, R0, RES_Tx_CRC); in scc_txint()
436 status = InReg(scc->ctrl,R0); in scc_exint()
652 OutReg(scc->ctrl,R0,RES_H_IUS); /* Reset Highest IUS */ in scc_isr()
701 OutReg(scc->ctrl,R0,RES_H_IUS); in scc_isr()
863 if(scc->kiss.softdcd || (InReg(scc->ctrl,R0) & DCD)) in init_channel()
878 scc->status = InReg(scc->ctrl,R0); /* read initial status */ in init_channel()
1251 OutReg(scc->ctrl, R0, RES_Tx_P); in t_maxkeyup()
2062 seq_printf(seq, "\tR %2.2x %2.2x XX ", InReg(scc->ctrl,R0), InReg(scc->ctrl,R1)); in scc_net_seq_show()
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| D | z8530.h | 6 #define R0 0 /* Register selects */ macro
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| /drivers/net/wan/ |
| D | z85230.c | 342 if(!(read_zsreg(c, R0)&1)) in z8530_rx()
413 if(!(read_zsreg(c, R0)&4)) in z8530_tx()
454 status = read_zsreg(chan, R0); in z8530_status()
566 status=read_zsreg(chan, R0); in z8530_dma_status()
674 u8 status=read_zsreg(chan, R0); in z8530_status_clear()
838 chk=read_zsreg(c,R0); in z8530_sync_close()
1031 chk=read_zsreg(c,R0); in z8530_sync_dma_close()
1195 chk=read_zsreg(c,R0); in z8530_sync_txdma_close()
1283 if(read_zsreg(&dev->chanA, R0)&Tx_BUF_EMP) in do_z8530_init()
1406 c->status=read_zsreg(c, R0); in z8530_channel_load()
[all …]
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| D | z85230.h | 25 #define R0 0 /* Register selects */ macro
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| /drivers/media/i2c/ |
| D | wm8739.c | 48 R0 = 0, R1, enumerator
127 wm8739_write(sd, R0, (vol_l & 0x1f) | mute); in wm8739_s_ctrl()
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| /drivers/media/dvb-frontends/ |
| D | drxk_hard.c | 189 u32 R0 = 0; in Frac28a() local
191 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
199 Q1 = (Q1 << 4) | (R0 / c); in Frac28a()
200 R0 = (R0 % c) << 4; in Frac28a()
203 if ((R0 >> 3) >= c) in Frac28a()
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| /drivers/media/dvb-frontends/drx39xyj/ |
| D | drxj.c | 1071 u32 R0 = 0; in frac28() local
1073 R0 = (N % D) << 4; /* 32-28 == 4 shifts possible at max */ in frac28()
1079 Q1 = (Q1 << 4) | R0 / D; in frac28()
1080 R0 = (R0 % D) << 4; in frac28()
1083 if ((R0 >> 3) >= D) in frac28()
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