1 /* sunzilog.c: Zilog serial driver for Sparc systems.
2 *
3 * Driver for Zilog serial chips found on Sun workstations and
4 * servers. This driver could actually be made more generic.
5 *
6 * This is based on the old drivers/sbus/char/zs.c code. A lot
7 * of code has been simply moved over directly from there but
8 * much has been rewritten. Credits therefore go out to Eddie
9 * C. Dost, Pete Zaitcev, Ted Ts'o and Alex Buell for their
10 * work there.
11 *
12 * Copyright (C) 2002, 2006, 2007 David S. Miller (davem@davemloft.net)
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
21 #include <linux/major.h>
22 #include <linux/string.h>
23 #include <linux/ptrace.h>
24 #include <linux/ioport.h>
25 #include <linux/slab.h>
26 #include <linux/circ_buf.h>
27 #include <linux/serial.h>
28 #include <linux/sysrq.h>
29 #include <linux/console.h>
30 #include <linux/spinlock.h>
31 #ifdef CONFIG_SERIO
32 #include <linux/serio.h>
33 #endif
34 #include <linux/init.h>
35 #include <linux/of_device.h>
36
37 #include <asm/io.h>
38 #include <asm/irq.h>
39 #include <asm/prom.h>
40 #include <asm/setup.h>
41
42 #if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43 #define SUPPORT_SYSRQ
44 #endif
45
46 #include <linux/serial_core.h>
47 #include <linux/sunserialcore.h>
48
49 #include "sunzilog.h"
50
51 /* On 32-bit sparcs we need to delay after register accesses
52 * to accommodate sun4 systems, but we do not need to flush writes.
53 * On 64-bit sparc we only need to flush single writes to ensure
54 * completion.
55 */
56 #ifndef CONFIG_SPARC64
57 #define ZSDELAY() udelay(5)
58 #define ZSDELAY_LONG() udelay(20)
59 #define ZS_WSYNC(channel) do { } while (0)
60 #else
61 #define ZSDELAY()
62 #define ZSDELAY_LONG()
63 #define ZS_WSYNC(__channel) \
64 readb(&((__channel)->control))
65 #endif
66
67 #define ZS_CLOCK 4915200 /* Zilog input clock rate. */
68 #define ZS_CLOCK_DIVISOR 16 /* Divisor this driver uses. */
69
70 /*
71 * We wrap our port structure around the generic uart_port.
72 */
73 struct uart_sunzilog_port {
74 struct uart_port port;
75
76 /* IRQ servicing chain. */
77 struct uart_sunzilog_port *next;
78
79 /* Current values of Zilog write registers. */
80 unsigned char curregs[NUM_ZSREGS];
81
82 unsigned int flags;
83 #define SUNZILOG_FLAG_CONS_KEYB 0x00000001
84 #define SUNZILOG_FLAG_CONS_MOUSE 0x00000002
85 #define SUNZILOG_FLAG_IS_CONS 0x00000004
86 #define SUNZILOG_FLAG_IS_KGDB 0x00000008
87 #define SUNZILOG_FLAG_MODEM_STATUS 0x00000010
88 #define SUNZILOG_FLAG_IS_CHANNEL_A 0x00000020
89 #define SUNZILOG_FLAG_REGS_HELD 0x00000040
90 #define SUNZILOG_FLAG_TX_STOPPED 0x00000080
91 #define SUNZILOG_FLAG_TX_ACTIVE 0x00000100
92 #define SUNZILOG_FLAG_ESCC 0x00000200
93 #define SUNZILOG_FLAG_ISR_HANDLER 0x00000400
94
95 unsigned int cflag;
96
97 unsigned char parity_mask;
98 unsigned char prev_status;
99
100 #ifdef CONFIG_SERIO
101 struct serio serio;
102 int serio_open;
103 #endif
104 };
105
106 static void sunzilog_putchar(struct uart_port *port, int ch);
107
108 #define ZILOG_CHANNEL_FROM_PORT(PORT) ((struct zilog_channel __iomem *)((PORT)->membase))
109 #define UART_ZILOG(PORT) ((struct uart_sunzilog_port *)(PORT))
110
111 #define ZS_IS_KEYB(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_KEYB)
112 #define ZS_IS_MOUSE(UP) ((UP)->flags & SUNZILOG_FLAG_CONS_MOUSE)
113 #define ZS_IS_CONS(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CONS)
114 #define ZS_IS_KGDB(UP) ((UP)->flags & SUNZILOG_FLAG_IS_KGDB)
115 #define ZS_WANTS_MODEM_STATUS(UP) ((UP)->flags & SUNZILOG_FLAG_MODEM_STATUS)
116 #define ZS_IS_CHANNEL_A(UP) ((UP)->flags & SUNZILOG_FLAG_IS_CHANNEL_A)
117 #define ZS_REGS_HELD(UP) ((UP)->flags & SUNZILOG_FLAG_REGS_HELD)
118 #define ZS_TX_STOPPED(UP) ((UP)->flags & SUNZILOG_FLAG_TX_STOPPED)
119 #define ZS_TX_ACTIVE(UP) ((UP)->flags & SUNZILOG_FLAG_TX_ACTIVE)
120
121 /* Reading and writing Zilog8530 registers. The delays are to make this
122 * driver work on the Sun4 which needs a settling delay after each chip
123 * register access, other machines handle this in hardware via auxiliary
124 * flip-flops which implement the settle time we do in software.
125 *
126 * The port lock must be held and local IRQs must be disabled
127 * when {read,write}_zsreg is invoked.
128 */
read_zsreg(struct zilog_channel __iomem * channel,unsigned char reg)129 static unsigned char read_zsreg(struct zilog_channel __iomem *channel,
130 unsigned char reg)
131 {
132 unsigned char retval;
133
134 writeb(reg, &channel->control);
135 ZSDELAY();
136 retval = readb(&channel->control);
137 ZSDELAY();
138
139 return retval;
140 }
141
write_zsreg(struct zilog_channel __iomem * channel,unsigned char reg,unsigned char value)142 static void write_zsreg(struct zilog_channel __iomem *channel,
143 unsigned char reg, unsigned char value)
144 {
145 writeb(reg, &channel->control);
146 ZSDELAY();
147 writeb(value, &channel->control);
148 ZSDELAY();
149 }
150
sunzilog_clear_fifo(struct zilog_channel __iomem * channel)151 static void sunzilog_clear_fifo(struct zilog_channel __iomem *channel)
152 {
153 int i;
154
155 for (i = 0; i < 32; i++) {
156 unsigned char regval;
157
158 regval = readb(&channel->control);
159 ZSDELAY();
160 if (regval & Rx_CH_AV)
161 break;
162
163 regval = read_zsreg(channel, R1);
164 readb(&channel->data);
165 ZSDELAY();
166
167 if (regval & (PAR_ERR | Rx_OVR | CRC_ERR)) {
168 writeb(ERR_RES, &channel->control);
169 ZSDELAY();
170 ZS_WSYNC(channel);
171 }
172 }
173 }
174
175 /* This function must only be called when the TX is not busy. The UART
176 * port lock must be held and local interrupts disabled.
177 */
__load_zsregs(struct zilog_channel __iomem * channel,unsigned char * regs)178 static int __load_zsregs(struct zilog_channel __iomem *channel, unsigned char *regs)
179 {
180 int i;
181 int escc;
182 unsigned char r15;
183
184 /* Let pending transmits finish. */
185 for (i = 0; i < 1000; i++) {
186 unsigned char stat = read_zsreg(channel, R1);
187 if (stat & ALL_SNT)
188 break;
189 udelay(100);
190 }
191
192 writeb(ERR_RES, &channel->control);
193 ZSDELAY();
194 ZS_WSYNC(channel);
195
196 sunzilog_clear_fifo(channel);
197
198 /* Disable all interrupts. */
199 write_zsreg(channel, R1,
200 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB));
201
202 /* Set parity, sync config, stop bits, and clock divisor. */
203 write_zsreg(channel, R4, regs[R4]);
204
205 /* Set misc. TX/RX control bits. */
206 write_zsreg(channel, R10, regs[R10]);
207
208 /* Set TX/RX controls sans the enable bits. */
209 write_zsreg(channel, R3, regs[R3] & ~RxENAB);
210 write_zsreg(channel, R5, regs[R5] & ~TxENAB);
211
212 /* Synchronous mode config. */
213 write_zsreg(channel, R6, regs[R6]);
214 write_zsreg(channel, R7, regs[R7]);
215
216 /* Don't mess with the interrupt vector (R2, unused by us) and
217 * master interrupt control (R9). We make sure this is setup
218 * properly at probe time then never touch it again.
219 */
220
221 /* Disable baud generator. */
222 write_zsreg(channel, R14, regs[R14] & ~BRENAB);
223
224 /* Clock mode control. */
225 write_zsreg(channel, R11, regs[R11]);
226
227 /* Lower and upper byte of baud rate generator divisor. */
228 write_zsreg(channel, R12, regs[R12]);
229 write_zsreg(channel, R13, regs[R13]);
230
231 /* Now rewrite R14, with BRENAB (if set). */
232 write_zsreg(channel, R14, regs[R14]);
233
234 /* External status interrupt control. */
235 write_zsreg(channel, R15, (regs[R15] | WR7pEN) & ~FIFOEN);
236
237 /* ESCC Extension Register */
238 r15 = read_zsreg(channel, R15);
239 if (r15 & 0x01) {
240 write_zsreg(channel, R7, regs[R7p]);
241
242 /* External status interrupt and FIFO control. */
243 write_zsreg(channel, R15, regs[R15] & ~WR7pEN);
244 escc = 1;
245 } else {
246 /* Clear FIFO bit case it is an issue */
247 regs[R15] &= ~FIFOEN;
248 escc = 0;
249 }
250
251 /* Reset external status interrupts. */
252 write_zsreg(channel, R0, RES_EXT_INT); /* First Latch */
253 write_zsreg(channel, R0, RES_EXT_INT); /* Second Latch */
254
255 /* Rewrite R3/R5, this time without enables masked. */
256 write_zsreg(channel, R3, regs[R3]);
257 write_zsreg(channel, R5, regs[R5]);
258
259 /* Rewrite R1, this time without IRQ enabled masked. */
260 write_zsreg(channel, R1, regs[R1]);
261
262 return escc;
263 }
264
265 /* Reprogram the Zilog channel HW registers with the copies found in the
266 * software state struct. If the transmitter is busy, we defer this update
267 * until the next TX complete interrupt. Else, we do it right now.
268 *
269 * The UART port lock must be held and local interrupts disabled.
270 */
sunzilog_maybe_update_regs(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)271 static void sunzilog_maybe_update_regs(struct uart_sunzilog_port *up,
272 struct zilog_channel __iomem *channel)
273 {
274 if (!ZS_REGS_HELD(up)) {
275 if (ZS_TX_ACTIVE(up)) {
276 up->flags |= SUNZILOG_FLAG_REGS_HELD;
277 } else {
278 __load_zsregs(channel, up->curregs);
279 }
280 }
281 }
282
sunzilog_change_mouse_baud(struct uart_sunzilog_port * up)283 static void sunzilog_change_mouse_baud(struct uart_sunzilog_port *up)
284 {
285 unsigned int cur_cflag = up->cflag;
286 int brg, new_baud;
287
288 up->cflag &= ~CBAUD;
289 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
290
291 brg = BPS_TO_BRG(new_baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
292 up->curregs[R12] = (brg & 0xff);
293 up->curregs[R13] = (brg >> 8) & 0xff;
294 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(&up->port));
295 }
296
sunzilog_kbdms_receive_chars(struct uart_sunzilog_port * up,unsigned char ch,int is_break)297 static void sunzilog_kbdms_receive_chars(struct uart_sunzilog_port *up,
298 unsigned char ch, int is_break)
299 {
300 if (ZS_IS_KEYB(up)) {
301 /* Stop-A is handled by drivers/char/keyboard.c now. */
302 #ifdef CONFIG_SERIO
303 if (up->serio_open)
304 serio_interrupt(&up->serio, ch, 0);
305 #endif
306 } else if (ZS_IS_MOUSE(up)) {
307 int ret = suncore_mouse_baud_detection(ch, is_break);
308
309 switch (ret) {
310 case 2:
311 sunzilog_change_mouse_baud(up);
312 /* fallthru */
313 case 1:
314 break;
315
316 case 0:
317 #ifdef CONFIG_SERIO
318 if (up->serio_open)
319 serio_interrupt(&up->serio, ch, 0);
320 #endif
321 break;
322 }
323 }
324 }
325
326 static struct tty_port *
sunzilog_receive_chars(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)327 sunzilog_receive_chars(struct uart_sunzilog_port *up,
328 struct zilog_channel __iomem *channel)
329 {
330 struct tty_port *port = NULL;
331 unsigned char ch, r1, flag;
332
333 if (up->port.state != NULL) /* Unopened serial console */
334 port = &up->port.state->port;
335
336 for (;;) {
337
338 r1 = read_zsreg(channel, R1);
339 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
340 writeb(ERR_RES, &channel->control);
341 ZSDELAY();
342 ZS_WSYNC(channel);
343 }
344
345 ch = readb(&channel->control);
346 ZSDELAY();
347
348 /* This funny hack depends upon BRK_ABRT not interfering
349 * with the other bits we care about in R1.
350 */
351 if (ch & BRK_ABRT)
352 r1 |= BRK_ABRT;
353
354 if (!(ch & Rx_CH_AV))
355 break;
356
357 ch = readb(&channel->data);
358 ZSDELAY();
359
360 ch &= up->parity_mask;
361
362 if (unlikely(ZS_IS_KEYB(up)) || unlikely(ZS_IS_MOUSE(up))) {
363 sunzilog_kbdms_receive_chars(up, ch, 0);
364 continue;
365 }
366
367 /* A real serial line, record the character and status. */
368 flag = TTY_NORMAL;
369 up->port.icount.rx++;
370 if (r1 & (BRK_ABRT | PAR_ERR | Rx_OVR | CRC_ERR)) {
371 if (r1 & BRK_ABRT) {
372 r1 &= ~(PAR_ERR | CRC_ERR);
373 up->port.icount.brk++;
374 if (uart_handle_break(&up->port))
375 continue;
376 }
377 else if (r1 & PAR_ERR)
378 up->port.icount.parity++;
379 else if (r1 & CRC_ERR)
380 up->port.icount.frame++;
381 if (r1 & Rx_OVR)
382 up->port.icount.overrun++;
383 r1 &= up->port.read_status_mask;
384 if (r1 & BRK_ABRT)
385 flag = TTY_BREAK;
386 else if (r1 & PAR_ERR)
387 flag = TTY_PARITY;
388 else if (r1 & CRC_ERR)
389 flag = TTY_FRAME;
390 }
391 if (uart_handle_sysrq_char(&up->port, ch) || !port)
392 continue;
393
394 if (up->port.ignore_status_mask == 0xff ||
395 (r1 & up->port.ignore_status_mask) == 0) {
396 tty_insert_flip_char(port, ch, flag);
397 }
398 if (r1 & Rx_OVR)
399 tty_insert_flip_char(port, 0, TTY_OVERRUN);
400 }
401
402 return port;
403 }
404
sunzilog_status_handle(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)405 static void sunzilog_status_handle(struct uart_sunzilog_port *up,
406 struct zilog_channel __iomem *channel)
407 {
408 unsigned char status;
409
410 status = readb(&channel->control);
411 ZSDELAY();
412
413 writeb(RES_EXT_INT, &channel->control);
414 ZSDELAY();
415 ZS_WSYNC(channel);
416
417 if (status & BRK_ABRT) {
418 if (ZS_IS_MOUSE(up))
419 sunzilog_kbdms_receive_chars(up, 0, 1);
420 if (ZS_IS_CONS(up)) {
421 /* Wait for BREAK to deassert to avoid potentially
422 * confusing the PROM.
423 */
424 while (1) {
425 status = readb(&channel->control);
426 ZSDELAY();
427 if (!(status & BRK_ABRT))
428 break;
429 }
430 sun_do_break();
431 return;
432 }
433 }
434
435 if (ZS_WANTS_MODEM_STATUS(up)) {
436 if (status & SYNC)
437 up->port.icount.dsr++;
438
439 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change.
440 * But it does not tell us which bit has changed, we have to keep
441 * track of this ourselves.
442 */
443 if ((status ^ up->prev_status) ^ DCD)
444 uart_handle_dcd_change(&up->port,
445 (status & DCD));
446 if ((status ^ up->prev_status) ^ CTS)
447 uart_handle_cts_change(&up->port,
448 (status & CTS));
449
450 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
451 }
452
453 up->prev_status = status;
454 }
455
sunzilog_transmit_chars(struct uart_sunzilog_port * up,struct zilog_channel __iomem * channel)456 static void sunzilog_transmit_chars(struct uart_sunzilog_port *up,
457 struct zilog_channel __iomem *channel)
458 {
459 struct circ_buf *xmit;
460
461 if (ZS_IS_CONS(up)) {
462 unsigned char status = readb(&channel->control);
463 ZSDELAY();
464
465 /* TX still busy? Just wait for the next TX done interrupt.
466 *
467 * It can occur because of how we do serial console writes. It would
468 * be nice to transmit console writes just like we normally would for
469 * a TTY line. (ie. buffered and TX interrupt driven). That is not
470 * easy because console writes cannot sleep. One solution might be
471 * to poll on enough port->xmit space becoming free. -DaveM
472 */
473 if (!(status & Tx_BUF_EMP))
474 return;
475 }
476
477 up->flags &= ~SUNZILOG_FLAG_TX_ACTIVE;
478
479 if (ZS_REGS_HELD(up)) {
480 __load_zsregs(channel, up->curregs);
481 up->flags &= ~SUNZILOG_FLAG_REGS_HELD;
482 }
483
484 if (ZS_TX_STOPPED(up)) {
485 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
486 goto ack_tx_int;
487 }
488
489 if (up->port.x_char) {
490 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
491 writeb(up->port.x_char, &channel->data);
492 ZSDELAY();
493 ZS_WSYNC(channel);
494
495 up->port.icount.tx++;
496 up->port.x_char = 0;
497 return;
498 }
499
500 if (up->port.state == NULL)
501 goto ack_tx_int;
502 xmit = &up->port.state->xmit;
503 if (uart_circ_empty(xmit))
504 goto ack_tx_int;
505
506 if (uart_tx_stopped(&up->port))
507 goto ack_tx_int;
508
509 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
510 writeb(xmit->buf[xmit->tail], &channel->data);
511 ZSDELAY();
512 ZS_WSYNC(channel);
513
514 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
515 up->port.icount.tx++;
516
517 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
518 uart_write_wakeup(&up->port);
519
520 return;
521
522 ack_tx_int:
523 writeb(RES_Tx_P, &channel->control);
524 ZSDELAY();
525 ZS_WSYNC(channel);
526 }
527
sunzilog_interrupt(int irq,void * dev_id)528 static irqreturn_t sunzilog_interrupt(int irq, void *dev_id)
529 {
530 struct uart_sunzilog_port *up = dev_id;
531
532 while (up) {
533 struct zilog_channel __iomem *channel
534 = ZILOG_CHANNEL_FROM_PORT(&up->port);
535 struct tty_port *port;
536 unsigned char r3;
537
538 spin_lock(&up->port.lock);
539 r3 = read_zsreg(channel, R3);
540
541 /* Channel A */
542 port = NULL;
543 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) {
544 writeb(RES_H_IUS, &channel->control);
545 ZSDELAY();
546 ZS_WSYNC(channel);
547
548 if (r3 & CHARxIP)
549 port = sunzilog_receive_chars(up, channel);
550 if (r3 & CHAEXT)
551 sunzilog_status_handle(up, channel);
552 if (r3 & CHATxIP)
553 sunzilog_transmit_chars(up, channel);
554 }
555 spin_unlock(&up->port.lock);
556
557 if (port)
558 tty_flip_buffer_push(port);
559
560 /* Channel B */
561 up = up->next;
562 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
563
564 spin_lock(&up->port.lock);
565 port = NULL;
566 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) {
567 writeb(RES_H_IUS, &channel->control);
568 ZSDELAY();
569 ZS_WSYNC(channel);
570
571 if (r3 & CHBRxIP)
572 port = sunzilog_receive_chars(up, channel);
573 if (r3 & CHBEXT)
574 sunzilog_status_handle(up, channel);
575 if (r3 & CHBTxIP)
576 sunzilog_transmit_chars(up, channel);
577 }
578 spin_unlock(&up->port.lock);
579
580 if (port)
581 tty_flip_buffer_push(port);
582
583 up = up->next;
584 }
585
586 return IRQ_HANDLED;
587 }
588
589 /* A convenient way to quickly get R0 status. The caller must _not_ hold the
590 * port lock, it is acquired here.
591 */
sunzilog_read_channel_status(struct uart_port * port)592 static __inline__ unsigned char sunzilog_read_channel_status(struct uart_port *port)
593 {
594 struct zilog_channel __iomem *channel;
595 unsigned char status;
596
597 channel = ZILOG_CHANNEL_FROM_PORT(port);
598 status = readb(&channel->control);
599 ZSDELAY();
600
601 return status;
602 }
603
604 /* The port lock is not held. */
sunzilog_tx_empty(struct uart_port * port)605 static unsigned int sunzilog_tx_empty(struct uart_port *port)
606 {
607 unsigned long flags;
608 unsigned char status;
609 unsigned int ret;
610
611 spin_lock_irqsave(&port->lock, flags);
612
613 status = sunzilog_read_channel_status(port);
614
615 spin_unlock_irqrestore(&port->lock, flags);
616
617 if (status & Tx_BUF_EMP)
618 ret = TIOCSER_TEMT;
619 else
620 ret = 0;
621
622 return ret;
623 }
624
625 /* The port lock is held and interrupts are disabled. */
sunzilog_get_mctrl(struct uart_port * port)626 static unsigned int sunzilog_get_mctrl(struct uart_port *port)
627 {
628 unsigned char status;
629 unsigned int ret;
630
631 status = sunzilog_read_channel_status(port);
632
633 ret = 0;
634 if (status & DCD)
635 ret |= TIOCM_CAR;
636 if (status & SYNC)
637 ret |= TIOCM_DSR;
638 if (status & CTS)
639 ret |= TIOCM_CTS;
640
641 return ret;
642 }
643
644 /* The port lock is held and interrupts are disabled. */
sunzilog_set_mctrl(struct uart_port * port,unsigned int mctrl)645 static void sunzilog_set_mctrl(struct uart_port *port, unsigned int mctrl)
646 {
647 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
648 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
649 unsigned char set_bits, clear_bits;
650
651 set_bits = clear_bits = 0;
652
653 if (mctrl & TIOCM_RTS)
654 set_bits |= RTS;
655 else
656 clear_bits |= RTS;
657 if (mctrl & TIOCM_DTR)
658 set_bits |= DTR;
659 else
660 clear_bits |= DTR;
661
662 /* NOTE: Not subject to 'transmitter active' rule. */
663 up->curregs[R5] |= set_bits;
664 up->curregs[R5] &= ~clear_bits;
665 write_zsreg(channel, R5, up->curregs[R5]);
666 }
667
668 /* The port lock is held and interrupts are disabled. */
sunzilog_stop_tx(struct uart_port * port)669 static void sunzilog_stop_tx(struct uart_port *port)
670 {
671 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
672
673 up->flags |= SUNZILOG_FLAG_TX_STOPPED;
674 }
675
676 /* The port lock is held and interrupts are disabled. */
sunzilog_start_tx(struct uart_port * port)677 static void sunzilog_start_tx(struct uart_port *port)
678 {
679 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
680 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
681 unsigned char status;
682
683 up->flags |= SUNZILOG_FLAG_TX_ACTIVE;
684 up->flags &= ~SUNZILOG_FLAG_TX_STOPPED;
685
686 status = readb(&channel->control);
687 ZSDELAY();
688
689 /* TX busy? Just wait for the TX done interrupt. */
690 if (!(status & Tx_BUF_EMP))
691 return;
692
693 /* Send the first character to jump-start the TX done
694 * IRQ sending engine.
695 */
696 if (port->x_char) {
697 writeb(port->x_char, &channel->data);
698 ZSDELAY();
699 ZS_WSYNC(channel);
700
701 port->icount.tx++;
702 port->x_char = 0;
703 } else {
704 struct circ_buf *xmit = &port->state->xmit;
705
706 if (uart_circ_empty(xmit))
707 return;
708 writeb(xmit->buf[xmit->tail], &channel->data);
709 ZSDELAY();
710 ZS_WSYNC(channel);
711
712 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
713 port->icount.tx++;
714
715 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
716 uart_write_wakeup(&up->port);
717 }
718 }
719
720 /* The port lock is held. */
sunzilog_stop_rx(struct uart_port * port)721 static void sunzilog_stop_rx(struct uart_port *port)
722 {
723 struct uart_sunzilog_port *up = UART_ZILOG(port);
724 struct zilog_channel __iomem *channel;
725
726 if (ZS_IS_CONS(up))
727 return;
728
729 channel = ZILOG_CHANNEL_FROM_PORT(port);
730
731 /* Disable all RX interrupts. */
732 up->curregs[R1] &= ~RxINT_MASK;
733 sunzilog_maybe_update_regs(up, channel);
734 }
735
736 /* The port lock is held. */
sunzilog_enable_ms(struct uart_port * port)737 static void sunzilog_enable_ms(struct uart_port *port)
738 {
739 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
740 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
741 unsigned char new_reg;
742
743 new_reg = up->curregs[R15] | (DCDIE | SYNCIE | CTSIE);
744 if (new_reg != up->curregs[R15]) {
745 up->curregs[R15] = new_reg;
746
747 /* NOTE: Not subject to 'transmitter active' rule. */
748 write_zsreg(channel, R15, up->curregs[R15] & ~WR7pEN);
749 }
750 }
751
752 /* The port lock is not held. */
sunzilog_break_ctl(struct uart_port * port,int break_state)753 static void sunzilog_break_ctl(struct uart_port *port, int break_state)
754 {
755 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
756 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
757 unsigned char set_bits, clear_bits, new_reg;
758 unsigned long flags;
759
760 set_bits = clear_bits = 0;
761
762 if (break_state)
763 set_bits |= SND_BRK;
764 else
765 clear_bits |= SND_BRK;
766
767 spin_lock_irqsave(&port->lock, flags);
768
769 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits;
770 if (new_reg != up->curregs[R5]) {
771 up->curregs[R5] = new_reg;
772
773 /* NOTE: Not subject to 'transmitter active' rule. */
774 write_zsreg(channel, R5, up->curregs[R5]);
775 }
776
777 spin_unlock_irqrestore(&port->lock, flags);
778 }
779
__sunzilog_startup(struct uart_sunzilog_port * up)780 static void __sunzilog_startup(struct uart_sunzilog_port *up)
781 {
782 struct zilog_channel __iomem *channel;
783
784 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
785 up->prev_status = readb(&channel->control);
786
787 /* Enable receiver and transmitter. */
788 up->curregs[R3] |= RxENAB;
789 up->curregs[R5] |= TxENAB;
790
791 up->curregs[R1] |= EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
792 sunzilog_maybe_update_regs(up, channel);
793 }
794
sunzilog_startup(struct uart_port * port)795 static int sunzilog_startup(struct uart_port *port)
796 {
797 struct uart_sunzilog_port *up = UART_ZILOG(port);
798 unsigned long flags;
799
800 if (ZS_IS_CONS(up))
801 return 0;
802
803 spin_lock_irqsave(&port->lock, flags);
804 __sunzilog_startup(up);
805 spin_unlock_irqrestore(&port->lock, flags);
806 return 0;
807 }
808
809 /*
810 * The test for ZS_IS_CONS is explained by the following e-mail:
811 *****
812 * From: Russell King <rmk@arm.linux.org.uk>
813 * Date: Sun, 8 Dec 2002 10:18:38 +0000
814 *
815 * On Sun, Dec 08, 2002 at 02:43:36AM -0500, Pete Zaitcev wrote:
816 * > I boot my 2.5 boxes using "console=ttyS0,9600" argument,
817 * > and I noticed that something is not right with reference
818 * > counting in this case. It seems that when the console
819 * > is open by kernel initially, this is not accounted
820 * > as an open, and uart_startup is not called.
821 *
822 * That is correct. We are unable to call uart_startup when the serial
823 * console is initialised because it may need to allocate memory (as
824 * request_irq does) and the memory allocators may not have been
825 * initialised.
826 *
827 * 1. initialise the port into a state where it can send characters in the
828 * console write method.
829 *
830 * 2. don't do the actual hardware shutdown in your shutdown() method (but
831 * do the normal software shutdown - ie, free irqs etc)
832 *****
833 */
sunzilog_shutdown(struct uart_port * port)834 static void sunzilog_shutdown(struct uart_port *port)
835 {
836 struct uart_sunzilog_port *up = UART_ZILOG(port);
837 struct zilog_channel __iomem *channel;
838 unsigned long flags;
839
840 if (ZS_IS_CONS(up))
841 return;
842
843 spin_lock_irqsave(&port->lock, flags);
844
845 channel = ZILOG_CHANNEL_FROM_PORT(port);
846
847 /* Disable receiver and transmitter. */
848 up->curregs[R3] &= ~RxENAB;
849 up->curregs[R5] &= ~TxENAB;
850
851 /* Disable all interrupts and BRK assertion. */
852 up->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK);
853 up->curregs[R5] &= ~SND_BRK;
854 sunzilog_maybe_update_regs(up, channel);
855
856 spin_unlock_irqrestore(&port->lock, flags);
857 }
858
859 /* Shared by TTY driver and serial console setup. The port lock is held
860 * and local interrupts are disabled.
861 */
862 static void
sunzilog_convert_to_zs(struct uart_sunzilog_port * up,unsigned int cflag,unsigned int iflag,int brg)863 sunzilog_convert_to_zs(struct uart_sunzilog_port *up, unsigned int cflag,
864 unsigned int iflag, int brg)
865 {
866
867 up->curregs[R10] = NRZ;
868 up->curregs[R11] = TCBR | RCBR;
869
870 /* Program BAUD and clock source. */
871 up->curregs[R4] &= ~XCLK_MASK;
872 up->curregs[R4] |= X16CLK;
873 up->curregs[R12] = brg & 0xff;
874 up->curregs[R13] = (brg >> 8) & 0xff;
875 up->curregs[R14] = BRSRC | BRENAB;
876
877 /* Character size, stop bits, and parity. */
878 up->curregs[R3] &= ~RxN_MASK;
879 up->curregs[R5] &= ~TxN_MASK;
880 switch (cflag & CSIZE) {
881 case CS5:
882 up->curregs[R3] |= Rx5;
883 up->curregs[R5] |= Tx5;
884 up->parity_mask = 0x1f;
885 break;
886 case CS6:
887 up->curregs[R3] |= Rx6;
888 up->curregs[R5] |= Tx6;
889 up->parity_mask = 0x3f;
890 break;
891 case CS7:
892 up->curregs[R3] |= Rx7;
893 up->curregs[R5] |= Tx7;
894 up->parity_mask = 0x7f;
895 break;
896 case CS8:
897 default:
898 up->curregs[R3] |= Rx8;
899 up->curregs[R5] |= Tx8;
900 up->parity_mask = 0xff;
901 break;
902 }
903 up->curregs[R4] &= ~0x0c;
904 if (cflag & CSTOPB)
905 up->curregs[R4] |= SB2;
906 else
907 up->curregs[R4] |= SB1;
908 if (cflag & PARENB)
909 up->curregs[R4] |= PAR_ENAB;
910 else
911 up->curregs[R4] &= ~PAR_ENAB;
912 if (!(cflag & PARODD))
913 up->curregs[R4] |= PAR_EVEN;
914 else
915 up->curregs[R4] &= ~PAR_EVEN;
916
917 up->port.read_status_mask = Rx_OVR;
918 if (iflag & INPCK)
919 up->port.read_status_mask |= CRC_ERR | PAR_ERR;
920 if (iflag & (IGNBRK | BRKINT | PARMRK))
921 up->port.read_status_mask |= BRK_ABRT;
922
923 up->port.ignore_status_mask = 0;
924 if (iflag & IGNPAR)
925 up->port.ignore_status_mask |= CRC_ERR | PAR_ERR;
926 if (iflag & IGNBRK) {
927 up->port.ignore_status_mask |= BRK_ABRT;
928 if (iflag & IGNPAR)
929 up->port.ignore_status_mask |= Rx_OVR;
930 }
931
932 if ((cflag & CREAD) == 0)
933 up->port.ignore_status_mask = 0xff;
934 }
935
936 /* The port lock is not held. */
937 static void
sunzilog_set_termios(struct uart_port * port,struct ktermios * termios,struct ktermios * old)938 sunzilog_set_termios(struct uart_port *port, struct ktermios *termios,
939 struct ktermios *old)
940 {
941 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
942 unsigned long flags;
943 int baud, brg;
944
945 baud = uart_get_baud_rate(port, termios, old, 1200, 76800);
946
947 spin_lock_irqsave(&up->port.lock, flags);
948
949 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
950
951 sunzilog_convert_to_zs(up, termios->c_cflag, termios->c_iflag, brg);
952
953 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
954 up->flags |= SUNZILOG_FLAG_MODEM_STATUS;
955 else
956 up->flags &= ~SUNZILOG_FLAG_MODEM_STATUS;
957
958 up->cflag = termios->c_cflag;
959
960 sunzilog_maybe_update_regs(up, ZILOG_CHANNEL_FROM_PORT(port));
961
962 uart_update_timeout(port, termios->c_cflag, baud);
963
964 spin_unlock_irqrestore(&up->port.lock, flags);
965 }
966
sunzilog_type(struct uart_port * port)967 static const char *sunzilog_type(struct uart_port *port)
968 {
969 struct uart_sunzilog_port *up = UART_ZILOG(port);
970
971 return (up->flags & SUNZILOG_FLAG_ESCC) ? "zs (ESCC)" : "zs";
972 }
973
974 /* We do not request/release mappings of the registers here, this
975 * happens at early serial probe time.
976 */
sunzilog_release_port(struct uart_port * port)977 static void sunzilog_release_port(struct uart_port *port)
978 {
979 }
980
sunzilog_request_port(struct uart_port * port)981 static int sunzilog_request_port(struct uart_port *port)
982 {
983 return 0;
984 }
985
986 /* These do not need to do anything interesting either. */
sunzilog_config_port(struct uart_port * port,int flags)987 static void sunzilog_config_port(struct uart_port *port, int flags)
988 {
989 }
990
991 /* We do not support letting the user mess with the divisor, IRQ, etc. */
sunzilog_verify_port(struct uart_port * port,struct serial_struct * ser)992 static int sunzilog_verify_port(struct uart_port *port, struct serial_struct *ser)
993 {
994 return -EINVAL;
995 }
996
997 #ifdef CONFIG_CONSOLE_POLL
sunzilog_get_poll_char(struct uart_port * port)998 static int sunzilog_get_poll_char(struct uart_port *port)
999 {
1000 unsigned char ch, r1;
1001 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *) port;
1002 struct zilog_channel __iomem *channel
1003 = ZILOG_CHANNEL_FROM_PORT(&up->port);
1004
1005
1006 r1 = read_zsreg(channel, R1);
1007 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) {
1008 writeb(ERR_RES, &channel->control);
1009 ZSDELAY();
1010 ZS_WSYNC(channel);
1011 }
1012
1013 ch = readb(&channel->control);
1014 ZSDELAY();
1015
1016 /* This funny hack depends upon BRK_ABRT not interfering
1017 * with the other bits we care about in R1.
1018 */
1019 if (ch & BRK_ABRT)
1020 r1 |= BRK_ABRT;
1021
1022 if (!(ch & Rx_CH_AV))
1023 return NO_POLL_CHAR;
1024
1025 ch = readb(&channel->data);
1026 ZSDELAY();
1027
1028 ch &= up->parity_mask;
1029 return ch;
1030 }
1031
sunzilog_put_poll_char(struct uart_port * port,unsigned char ch)1032 static void sunzilog_put_poll_char(struct uart_port *port,
1033 unsigned char ch)
1034 {
1035 struct uart_sunzilog_port *up = (struct uart_sunzilog_port *)port;
1036
1037 sunzilog_putchar(&up->port, ch);
1038 }
1039 #endif /* CONFIG_CONSOLE_POLL */
1040
1041 static struct uart_ops sunzilog_pops = {
1042 .tx_empty = sunzilog_tx_empty,
1043 .set_mctrl = sunzilog_set_mctrl,
1044 .get_mctrl = sunzilog_get_mctrl,
1045 .stop_tx = sunzilog_stop_tx,
1046 .start_tx = sunzilog_start_tx,
1047 .stop_rx = sunzilog_stop_rx,
1048 .enable_ms = sunzilog_enable_ms,
1049 .break_ctl = sunzilog_break_ctl,
1050 .startup = sunzilog_startup,
1051 .shutdown = sunzilog_shutdown,
1052 .set_termios = sunzilog_set_termios,
1053 .type = sunzilog_type,
1054 .release_port = sunzilog_release_port,
1055 .request_port = sunzilog_request_port,
1056 .config_port = sunzilog_config_port,
1057 .verify_port = sunzilog_verify_port,
1058 #ifdef CONFIG_CONSOLE_POLL
1059 .poll_get_char = sunzilog_get_poll_char,
1060 .poll_put_char = sunzilog_put_poll_char,
1061 #endif
1062 };
1063
1064 static int uart_chip_count;
1065 static struct uart_sunzilog_port *sunzilog_port_table;
1066 static struct zilog_layout __iomem **sunzilog_chip_regs;
1067
1068 static struct uart_sunzilog_port *sunzilog_irq_chain;
1069
1070 static struct uart_driver sunzilog_reg = {
1071 .owner = THIS_MODULE,
1072 .driver_name = "sunzilog",
1073 .dev_name = "ttyS",
1074 .major = TTY_MAJOR,
1075 };
1076
sunzilog_alloc_tables(int num_sunzilog)1077 static int __init sunzilog_alloc_tables(int num_sunzilog)
1078 {
1079 struct uart_sunzilog_port *up;
1080 unsigned long size;
1081 int num_channels = num_sunzilog * 2;
1082 int i;
1083
1084 size = num_channels * sizeof(struct uart_sunzilog_port);
1085 sunzilog_port_table = kzalloc(size, GFP_KERNEL);
1086 if (!sunzilog_port_table)
1087 return -ENOMEM;
1088
1089 for (i = 0; i < num_channels; i++) {
1090 up = &sunzilog_port_table[i];
1091
1092 spin_lock_init(&up->port.lock);
1093
1094 if (i == 0)
1095 sunzilog_irq_chain = up;
1096
1097 if (i < num_channels - 1)
1098 up->next = up + 1;
1099 else
1100 up->next = NULL;
1101 }
1102
1103 size = num_sunzilog * sizeof(struct zilog_layout __iomem *);
1104 sunzilog_chip_regs = kzalloc(size, GFP_KERNEL);
1105 if (!sunzilog_chip_regs) {
1106 kfree(sunzilog_port_table);
1107 sunzilog_irq_chain = NULL;
1108 return -ENOMEM;
1109 }
1110
1111 return 0;
1112 }
1113
sunzilog_free_tables(void)1114 static void sunzilog_free_tables(void)
1115 {
1116 kfree(sunzilog_port_table);
1117 sunzilog_irq_chain = NULL;
1118 kfree(sunzilog_chip_regs);
1119 }
1120
1121 #define ZS_PUT_CHAR_MAX_DELAY 2000 /* 10 ms */
1122
sunzilog_putchar(struct uart_port * port,int ch)1123 static void sunzilog_putchar(struct uart_port *port, int ch)
1124 {
1125 struct zilog_channel __iomem *channel = ZILOG_CHANNEL_FROM_PORT(port);
1126 int loops = ZS_PUT_CHAR_MAX_DELAY;
1127
1128 /* This is a timed polling loop so do not switch the explicit
1129 * udelay with ZSDELAY as that is a NOP on some platforms. -DaveM
1130 */
1131 do {
1132 unsigned char val = readb(&channel->control);
1133 if (val & Tx_BUF_EMP) {
1134 ZSDELAY();
1135 break;
1136 }
1137 udelay(5);
1138 } while (--loops);
1139
1140 writeb(ch, &channel->data);
1141 ZSDELAY();
1142 ZS_WSYNC(channel);
1143 }
1144
1145 #ifdef CONFIG_SERIO
1146
1147 static DEFINE_SPINLOCK(sunzilog_serio_lock);
1148
sunzilog_serio_write(struct serio * serio,unsigned char ch)1149 static int sunzilog_serio_write(struct serio *serio, unsigned char ch)
1150 {
1151 struct uart_sunzilog_port *up = serio->port_data;
1152 unsigned long flags;
1153
1154 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1155
1156 sunzilog_putchar(&up->port, ch);
1157
1158 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1159
1160 return 0;
1161 }
1162
sunzilog_serio_open(struct serio * serio)1163 static int sunzilog_serio_open(struct serio *serio)
1164 {
1165 struct uart_sunzilog_port *up = serio->port_data;
1166 unsigned long flags;
1167 int ret;
1168
1169 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1170 if (!up->serio_open) {
1171 up->serio_open = 1;
1172 ret = 0;
1173 } else
1174 ret = -EBUSY;
1175 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1176
1177 return ret;
1178 }
1179
sunzilog_serio_close(struct serio * serio)1180 static void sunzilog_serio_close(struct serio *serio)
1181 {
1182 struct uart_sunzilog_port *up = serio->port_data;
1183 unsigned long flags;
1184
1185 spin_lock_irqsave(&sunzilog_serio_lock, flags);
1186 up->serio_open = 0;
1187 spin_unlock_irqrestore(&sunzilog_serio_lock, flags);
1188 }
1189
1190 #endif /* CONFIG_SERIO */
1191
1192 #ifdef CONFIG_SERIAL_SUNZILOG_CONSOLE
1193 static void
sunzilog_console_write(struct console * con,const char * s,unsigned int count)1194 sunzilog_console_write(struct console *con, const char *s, unsigned int count)
1195 {
1196 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1197 unsigned long flags;
1198 int locked = 1;
1199
1200 if (up->port.sysrq || oops_in_progress)
1201 locked = spin_trylock_irqsave(&up->port.lock, flags);
1202 else
1203 spin_lock_irqsave(&up->port.lock, flags);
1204
1205 uart_console_write(&up->port, s, count, sunzilog_putchar);
1206 udelay(2);
1207
1208 if (locked)
1209 spin_unlock_irqrestore(&up->port.lock, flags);
1210 }
1211
sunzilog_console_setup(struct console * con,char * options)1212 static int __init sunzilog_console_setup(struct console *con, char *options)
1213 {
1214 struct uart_sunzilog_port *up = &sunzilog_port_table[con->index];
1215 unsigned long flags;
1216 int baud, brg;
1217
1218 if (up->port.type != PORT_SUNZILOG)
1219 return -1;
1220
1221 printk(KERN_INFO "Console: ttyS%d (SunZilog zs%d)\n",
1222 (sunzilog_reg.minor - 64) + con->index, con->index);
1223
1224 /* Get firmware console settings. */
1225 sunserial_console_termios(con, up->port.dev->of_node);
1226
1227 /* Firmware console speed is limited to 150-->38400 baud so
1228 * this hackish cflag thing is OK.
1229 */
1230 switch (con->cflag & CBAUD) {
1231 case B150: baud = 150; break;
1232 case B300: baud = 300; break;
1233 case B600: baud = 600; break;
1234 case B1200: baud = 1200; break;
1235 case B2400: baud = 2400; break;
1236 case B4800: baud = 4800; break;
1237 default: case B9600: baud = 9600; break;
1238 case B19200: baud = 19200; break;
1239 case B38400: baud = 38400; break;
1240 }
1241
1242 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1243
1244 spin_lock_irqsave(&up->port.lock, flags);
1245
1246 up->curregs[R15] |= BRKIE;
1247 sunzilog_convert_to_zs(up, con->cflag, 0, brg);
1248
1249 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1250 __sunzilog_startup(up);
1251
1252 spin_unlock_irqrestore(&up->port.lock, flags);
1253
1254 return 0;
1255 }
1256
1257 static struct console sunzilog_console_ops = {
1258 .name = "ttyS",
1259 .write = sunzilog_console_write,
1260 .device = uart_console_device,
1261 .setup = sunzilog_console_setup,
1262 .flags = CON_PRINTBUFFER,
1263 .index = -1,
1264 .data = &sunzilog_reg,
1265 };
1266
SUNZILOG_CONSOLE(void)1267 static inline struct console *SUNZILOG_CONSOLE(void)
1268 {
1269 return &sunzilog_console_ops;
1270 }
1271
1272 #else
1273 #define SUNZILOG_CONSOLE() (NULL)
1274 #endif
1275
sunzilog_init_kbdms(struct uart_sunzilog_port * up)1276 static void sunzilog_init_kbdms(struct uart_sunzilog_port *up)
1277 {
1278 int baud, brg;
1279
1280 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1281 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
1282 baud = 1200;
1283 } else {
1284 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
1285 baud = 4800;
1286 }
1287
1288 up->curregs[R15] |= BRKIE;
1289 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1290 sunzilog_convert_to_zs(up, up->cflag, 0, brg);
1291 sunzilog_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
1292 __sunzilog_startup(up);
1293 }
1294
1295 #ifdef CONFIG_SERIO
sunzilog_register_serio(struct uart_sunzilog_port * up)1296 static void sunzilog_register_serio(struct uart_sunzilog_port *up)
1297 {
1298 struct serio *serio = &up->serio;
1299
1300 serio->port_data = up;
1301
1302 serio->id.type = SERIO_RS232;
1303 if (up->flags & SUNZILOG_FLAG_CONS_KEYB) {
1304 serio->id.proto = SERIO_SUNKBD;
1305 strlcpy(serio->name, "zskbd", sizeof(serio->name));
1306 } else {
1307 serio->id.proto = SERIO_SUN;
1308 serio->id.extra = 1;
1309 strlcpy(serio->name, "zsms", sizeof(serio->name));
1310 }
1311 strlcpy(serio->phys,
1312 ((up->flags & SUNZILOG_FLAG_CONS_KEYB) ?
1313 "zs/serio0" : "zs/serio1"),
1314 sizeof(serio->phys));
1315
1316 serio->write = sunzilog_serio_write;
1317 serio->open = sunzilog_serio_open;
1318 serio->close = sunzilog_serio_close;
1319 serio->dev.parent = up->port.dev;
1320
1321 serio_register_port(serio);
1322 }
1323 #endif
1324
sunzilog_init_hw(struct uart_sunzilog_port * up)1325 static void sunzilog_init_hw(struct uart_sunzilog_port *up)
1326 {
1327 struct zilog_channel __iomem *channel;
1328 unsigned long flags;
1329 int baud, brg;
1330
1331 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1332
1333 spin_lock_irqsave(&up->port.lock, flags);
1334 if (ZS_IS_CHANNEL_A(up)) {
1335 write_zsreg(channel, R9, FHWRES);
1336 ZSDELAY_LONG();
1337 (void) read_zsreg(channel, R0);
1338 }
1339
1340 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1341 SUNZILOG_FLAG_CONS_MOUSE)) {
1342 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1343 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1344 up->curregs[R3] = RxENAB | Rx8;
1345 up->curregs[R5] = TxENAB | Tx8;
1346 up->curregs[R6] = 0x00; /* SDLC Address */
1347 up->curregs[R7] = 0x7E; /* SDLC Flag */
1348 up->curregs[R9] = NV;
1349 up->curregs[R7p] = 0x00;
1350 sunzilog_init_kbdms(up);
1351 /* Only enable interrupts if an ISR handler available */
1352 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1353 up->curregs[R9] |= MIE;
1354 write_zsreg(channel, R9, up->curregs[R9]);
1355 } else {
1356 /* Normal serial TTY. */
1357 up->parity_mask = 0xff;
1358 up->curregs[R1] = EXT_INT_ENAB | INT_ALL_Rx | TxINT_ENAB;
1359 up->curregs[R4] = PAR_EVEN | X16CLK | SB1;
1360 up->curregs[R3] = RxENAB | Rx8;
1361 up->curregs[R5] = TxENAB | Tx8;
1362 up->curregs[R6] = 0x00; /* SDLC Address */
1363 up->curregs[R7] = 0x7E; /* SDLC Flag */
1364 up->curregs[R9] = NV;
1365 up->curregs[R10] = NRZ;
1366 up->curregs[R11] = TCBR | RCBR;
1367 baud = 9600;
1368 brg = BPS_TO_BRG(baud, ZS_CLOCK / ZS_CLOCK_DIVISOR);
1369 up->curregs[R12] = (brg & 0xff);
1370 up->curregs[R13] = (brg >> 8) & 0xff;
1371 up->curregs[R14] = BRSRC | BRENAB;
1372 up->curregs[R15] = FIFOEN; /* Use FIFO if on ESCC */
1373 up->curregs[R7p] = TxFIFO_LVL | RxFIFO_LVL;
1374 if (__load_zsregs(channel, up->curregs)) {
1375 up->flags |= SUNZILOG_FLAG_ESCC;
1376 }
1377 /* Only enable interrupts if an ISR handler available */
1378 if (up->flags & SUNZILOG_FLAG_ISR_HANDLER)
1379 up->curregs[R9] |= MIE;
1380 write_zsreg(channel, R9, up->curregs[R9]);
1381 }
1382
1383 spin_unlock_irqrestore(&up->port.lock, flags);
1384
1385 #ifdef CONFIG_SERIO
1386 if (up->flags & (SUNZILOG_FLAG_CONS_KEYB |
1387 SUNZILOG_FLAG_CONS_MOUSE))
1388 sunzilog_register_serio(up);
1389 #endif
1390 }
1391
1392 static int zilog_irq;
1393
zs_probe(struct platform_device * op)1394 static int zs_probe(struct platform_device *op)
1395 {
1396 static int kbm_inst, uart_inst;
1397 int inst;
1398 struct uart_sunzilog_port *up;
1399 struct zilog_layout __iomem *rp;
1400 int keyboard_mouse = 0;
1401 int err;
1402
1403 if (of_find_property(op->dev.of_node, "keyboard", NULL))
1404 keyboard_mouse = 1;
1405
1406 /* uarts must come before keyboards/mice */
1407 if (keyboard_mouse)
1408 inst = uart_chip_count + kbm_inst;
1409 else
1410 inst = uart_inst;
1411
1412 sunzilog_chip_regs[inst] = of_ioremap(&op->resource[0], 0,
1413 sizeof(struct zilog_layout),
1414 "zs");
1415 if (!sunzilog_chip_regs[inst])
1416 return -ENOMEM;
1417
1418 rp = sunzilog_chip_regs[inst];
1419
1420 if (!zilog_irq)
1421 zilog_irq = op->archdata.irqs[0];
1422
1423 up = &sunzilog_port_table[inst * 2];
1424
1425 /* Channel A */
1426 up[0].port.mapbase = op->resource[0].start + 0x00;
1427 up[0].port.membase = (void __iomem *) &rp->channelA;
1428 up[0].port.iotype = UPIO_MEM;
1429 up[0].port.irq = op->archdata.irqs[0];
1430 up[0].port.uartclk = ZS_CLOCK;
1431 up[0].port.fifosize = 1;
1432 up[0].port.ops = &sunzilog_pops;
1433 up[0].port.type = PORT_SUNZILOG;
1434 up[0].port.flags = 0;
1435 up[0].port.line = (inst * 2) + 0;
1436 up[0].port.dev = &op->dev;
1437 up[0].flags |= SUNZILOG_FLAG_IS_CHANNEL_A;
1438 if (keyboard_mouse)
1439 up[0].flags |= SUNZILOG_FLAG_CONS_KEYB;
1440 sunzilog_init_hw(&up[0]);
1441
1442 /* Channel B */
1443 up[1].port.mapbase = op->resource[0].start + 0x04;
1444 up[1].port.membase = (void __iomem *) &rp->channelB;
1445 up[1].port.iotype = UPIO_MEM;
1446 up[1].port.irq = op->archdata.irqs[0];
1447 up[1].port.uartclk = ZS_CLOCK;
1448 up[1].port.fifosize = 1;
1449 up[1].port.ops = &sunzilog_pops;
1450 up[1].port.type = PORT_SUNZILOG;
1451 up[1].port.flags = 0;
1452 up[1].port.line = (inst * 2) + 1;
1453 up[1].port.dev = &op->dev;
1454 up[1].flags |= 0;
1455 if (keyboard_mouse)
1456 up[1].flags |= SUNZILOG_FLAG_CONS_MOUSE;
1457 sunzilog_init_hw(&up[1]);
1458
1459 if (!keyboard_mouse) {
1460 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1461 &sunzilog_reg, up[0].port.line,
1462 false))
1463 up->flags |= SUNZILOG_FLAG_IS_CONS;
1464 err = uart_add_one_port(&sunzilog_reg, &up[0].port);
1465 if (err) {
1466 of_iounmap(&op->resource[0],
1467 rp, sizeof(struct zilog_layout));
1468 return err;
1469 }
1470 if (sunserial_console_match(SUNZILOG_CONSOLE(), op->dev.of_node,
1471 &sunzilog_reg, up[1].port.line,
1472 false))
1473 up->flags |= SUNZILOG_FLAG_IS_CONS;
1474 err = uart_add_one_port(&sunzilog_reg, &up[1].port);
1475 if (err) {
1476 uart_remove_one_port(&sunzilog_reg, &up[0].port);
1477 of_iounmap(&op->resource[0],
1478 rp, sizeof(struct zilog_layout));
1479 return err;
1480 }
1481 uart_inst++;
1482 } else {
1483 printk(KERN_INFO "%s: Keyboard at MMIO 0x%llx (irq = %d) "
1484 "is a %s\n",
1485 dev_name(&op->dev),
1486 (unsigned long long) up[0].port.mapbase,
1487 op->archdata.irqs[0], sunzilog_type(&up[0].port));
1488 printk(KERN_INFO "%s: Mouse at MMIO 0x%llx (irq = %d) "
1489 "is a %s\n",
1490 dev_name(&op->dev),
1491 (unsigned long long) up[1].port.mapbase,
1492 op->archdata.irqs[0], sunzilog_type(&up[1].port));
1493 kbm_inst++;
1494 }
1495
1496 platform_set_drvdata(op, &up[0]);
1497
1498 return 0;
1499 }
1500
zs_remove_one(struct uart_sunzilog_port * up)1501 static void zs_remove_one(struct uart_sunzilog_port *up)
1502 {
1503 if (ZS_IS_KEYB(up) || ZS_IS_MOUSE(up)) {
1504 #ifdef CONFIG_SERIO
1505 serio_unregister_port(&up->serio);
1506 #endif
1507 } else
1508 uart_remove_one_port(&sunzilog_reg, &up->port);
1509 }
1510
zs_remove(struct platform_device * op)1511 static int zs_remove(struct platform_device *op)
1512 {
1513 struct uart_sunzilog_port *up = platform_get_drvdata(op);
1514 struct zilog_layout __iomem *regs;
1515
1516 zs_remove_one(&up[0]);
1517 zs_remove_one(&up[1]);
1518
1519 regs = sunzilog_chip_regs[up[0].port.line / 2];
1520 of_iounmap(&op->resource[0], regs, sizeof(struct zilog_layout));
1521
1522 return 0;
1523 }
1524
1525 static const struct of_device_id zs_match[] = {
1526 {
1527 .name = "zs",
1528 },
1529 {},
1530 };
1531 MODULE_DEVICE_TABLE(of, zs_match);
1532
1533 static struct platform_driver zs_driver = {
1534 .driver = {
1535 .name = "zs",
1536 .owner = THIS_MODULE,
1537 .of_match_table = zs_match,
1538 },
1539 .probe = zs_probe,
1540 .remove = zs_remove,
1541 };
1542
sunzilog_init(void)1543 static int __init sunzilog_init(void)
1544 {
1545 struct device_node *dp;
1546 int err;
1547 int num_keybms = 0;
1548 int num_sunzilog = 0;
1549
1550 for_each_node_by_name(dp, "zs") {
1551 num_sunzilog++;
1552 if (of_find_property(dp, "keyboard", NULL))
1553 num_keybms++;
1554 }
1555
1556 if (num_sunzilog) {
1557 err = sunzilog_alloc_tables(num_sunzilog);
1558 if (err)
1559 goto out;
1560
1561 uart_chip_count = num_sunzilog - num_keybms;
1562
1563 err = sunserial_register_minors(&sunzilog_reg,
1564 uart_chip_count * 2);
1565 if (err)
1566 goto out_free_tables;
1567 }
1568
1569 err = platform_driver_register(&zs_driver);
1570 if (err)
1571 goto out_unregister_uart;
1572
1573 if (zilog_irq) {
1574 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1575 err = request_irq(zilog_irq, sunzilog_interrupt, IRQF_SHARED,
1576 "zs", sunzilog_irq_chain);
1577 if (err)
1578 goto out_unregister_driver;
1579
1580 /* Enable Interrupts */
1581 while (up) {
1582 struct zilog_channel __iomem *channel;
1583
1584 /* printk (KERN_INFO "Enable IRQ for ZILOG Hardware %p\n", up); */
1585 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1586 up->flags |= SUNZILOG_FLAG_ISR_HANDLER;
1587 up->curregs[R9] |= MIE;
1588 write_zsreg(channel, R9, up->curregs[R9]);
1589 up = up->next;
1590 }
1591 }
1592
1593 out:
1594 return err;
1595
1596 out_unregister_driver:
1597 platform_driver_unregister(&zs_driver);
1598
1599 out_unregister_uart:
1600 if (num_sunzilog) {
1601 sunserial_unregister_minors(&sunzilog_reg, num_sunzilog);
1602 sunzilog_reg.cons = NULL;
1603 }
1604
1605 out_free_tables:
1606 sunzilog_free_tables();
1607 goto out;
1608 }
1609
sunzilog_exit(void)1610 static void __exit sunzilog_exit(void)
1611 {
1612 platform_driver_unregister(&zs_driver);
1613
1614 if (zilog_irq) {
1615 struct uart_sunzilog_port *up = sunzilog_irq_chain;
1616
1617 /* Disable Interrupts */
1618 while (up) {
1619 struct zilog_channel __iomem *channel;
1620
1621 /* printk (KERN_INFO "Disable IRQ for ZILOG Hardware %p\n", up); */
1622 channel = ZILOG_CHANNEL_FROM_PORT(&up->port);
1623 up->flags &= ~SUNZILOG_FLAG_ISR_HANDLER;
1624 up->curregs[R9] &= ~MIE;
1625 write_zsreg(channel, R9, up->curregs[R9]);
1626 up = up->next;
1627 }
1628
1629 free_irq(zilog_irq, sunzilog_irq_chain);
1630 zilog_irq = 0;
1631 }
1632
1633 if (sunzilog_reg.nr) {
1634 sunserial_unregister_minors(&sunzilog_reg, sunzilog_reg.nr);
1635 sunzilog_free_tables();
1636 }
1637 }
1638
1639 module_init(sunzilog_init);
1640 module_exit(sunzilog_exit);
1641
1642 MODULE_AUTHOR("David S. Miller");
1643 MODULE_DESCRIPTION("Sun Zilog serial port driver");
1644 MODULE_VERSION("2.0");
1645 MODULE_LICENSE("GPL");
1646