Home
last modified time | relevance | path

Searched refs:bypass (Results 1 – 25 of 29) sorted by relevance

12

/drivers/regulator/
Danatop-regulator.c54 bool bypass; member
89 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel; in anatop_regmap_enable()
109 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) { in anatop_regmap_core_set_voltage_sel()
124 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) in anatop_regmap_core_get_voltage_sel()
137 WARN_ON(!anatop_reg->bypass); in anatop_regmap_get_bypass()
139 WARN_ON(anatop_reg->bypass); in anatop_regmap_get_bypass()
141 *enable = anatop_reg->bypass; in anatop_regmap_get_bypass()
150 if (enable == anatop_reg->bypass) in anatop_regmap_set_bypass()
154 anatop_reg->bypass = enable; in anatop_regmap_set_bypass()
284 sreg->bypass = true; in anatop_regulator_probe()
Dinternal.h28 unsigned int bypass:1; member
Dcore.c623 bool bypass; in regulator_bypass_show() local
626 ret = rdev->desc->ops->get_bypass(rdev, &bypass); in regulator_bypass_show()
630 else if (bypass) in regulator_bypass_show()
637 static DEVICE_ATTR(bypass, 0444,
3120 if (enable && !regulator->bypass) { in regulator_allow_bypass()
3129 } else if (!enable && regulator->bypass) { in regulator_allow_bypass()
3140 regulator->bypass = enable; in regulator_allow_bypass()
/drivers/md/bcache/
Dstats.c184 bool hit, bool bypass) in mark_cache_stats() argument
186 if (!bypass) in mark_cache_stats()
199 bool hit, bool bypass) in bch_mark_cache_accounting() argument
202 mark_cache_stats(&dc->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
203 mark_cache_stats(&c->accounting.collector, hit, bypass); in bch_mark_cache_accounting()
Drequest.c201 if (op->bypass) in bch_data_insert_start()
274 op->bypass = true; in bch_data_insert_start()
315 op->writeback, op->bypass); in bch_data_insert()
779 !s->cache_missed, s->iop.bypass); in cached_dev_read_done_bh()
780 trace_bcache_read(s->orig_bio, !s->cache_miss, s->iop.bypass); in cached_dev_read_done_bh()
800 if (s->cache_miss || s->iop.bypass) { in cached_dev_cache_miss()
898 s->iop.bypass = false; in cached_dev_write()
910 s->iop.bypass = true; in cached_dev_write()
914 s->iop.bypass)) { in cached_dev_write()
915 s->iop.bypass = false; in cached_dev_write()
[all …]
Drequest.h19 unsigned bypass:1; member
/drivers/clk/socfpga/
Dclk-pll.c55 unsigned long bypass; in clk_pll_recalc_rate() local
58 bypass = readl(clk_mgr_base_addr + CLKMGR_BYPASS); in clk_pll_recalc_rate()
59 if (bypass & MAINPLL_BYPASS) in clk_pll_recalc_rate()
/drivers/clk/at91/
Dclk-slow.c126 bool bypass) in at91_clk_register_slow_osc() argument
149 if (bypass) in at91_clk_register_slow_osc()
167 bool bypass; in of_at91sam9x5_clk_slow_osc_setup() local
172 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_at91sam9x5_clk_slow_osc_setup()
175 bypass); in of_at91sam9x5_clk_slow_osc_setup()
Dclk-main.c146 bool bypass) in at91_clk_register_main_osc() argument
177 if (bypass) in at91_clk_register_main_osc()
199 bool bypass; in of_at91rm9200_clk_main_osc_setup() local
202 bypass = of_property_read_bool(np, "atmel,osc-bypass"); in of_at91rm9200_clk_main_osc_setup()
209 clk = at91_clk_register_main_osc(pmc, irq, name, parent_name, bypass); in of_at91rm9200_clk_main_osc_setup()
/drivers/base/regmap/
Dregcache.c299 unsigned int bypass; in regcache_sync() local
305 bypass = map->cache_bypass; in regcache_sync()
339 map->cache_bypass = bypass; in regcache_sync()
367 unsigned int bypass; in regcache_sync_region() local
374 bypass = map->cache_bypass; in regcache_sync_region()
393 map->cache_bypass = bypass; in regcache_sync_region()
Dregmap.c1968 bool bypass; in regmap_multi_reg_write_bypassed() local
1972 bypass = map->cache_bypass; in regmap_multi_reg_write_bypassed()
1977 map->cache_bypass = bypass; in regmap_multi_reg_write_bypassed()
2559 bool bypass; in regmap_register_patch() local
2578 bypass = map->cache_bypass; in regmap_register_patch()
2589 map->cache_bypass = bypass; in regmap_register_patch()
/drivers/gpu/drm/nouveau/core/subdev/clock/
Dnva3.c347 u32 bypass; in prog_pll() local
351 bypass = nv_rd32(priv, ctrl) & 0x00000008; in prog_pll()
352 if (!bypass) { in prog_pll()
/drivers/irqchip/
Dirq-gic.c366 u32 bypass = 0; in gic_cpu_if_up() local
371 bypass = readl(cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
372 bypass &= GICC_DIS_BYPASS_MASK; in gic_cpu_if_up()
374 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); in gic_cpu_if_up()
/drivers/media/usb/dvb-usb/
Dvp702x.c155 static int vp702x_set_pld_mode(struct dvb_usb_adapter *adap, u8 bypass) in vp702x_set_pld_mode() argument
166 ret = vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e, in vp702x_set_pld_mode()
/drivers/crypto/amcc/
Dcrypto4xx_core.h130 u32 bypass; member
Dcrypto4xx_reg_def.h266 u32 bypass:8; member
/drivers/staging/media/davinci_vpfe/
Ddm365_resizer.c106 resizer_configure_passthru(struct vpfe_resizer_device *resizer, int bypass) in resizer_configure_passthru() argument
125 if (bypass) { in resizer_configure_passthru()
534 param->rsz_common.passthrough = cont_config->bypass; in resizer_configure_in_continious_mode()
535 if (cont_config->bypass) in resizer_configure_in_continious_mode()
795 param->rsz_common.passthrough = config->bypass; in resizer_configure_in_single_shot_mode()
796 if (config->bypass) in resizer_configure_in_single_shot_mode()
Ddavinci_vpfe_user.h1282 unsigned char bypass; member
/drivers/media/platform/exynos4-is/
Dfimc-is-param.c467 drc->control.bypass = val; in __is_set_drc_control()
689 isp->control.bypass = CONTROL_BYPASS_DISABLE; in fimc_is_set_initial_params()
861 fd->control.bypass = CONTROL_BYPASS_DISABLE; in fimc_is_set_initial_params()
Dfimc-is-param.h454 u32 bypass; member
/drivers/gpu/drm/exynos/
Dexynos_drm_fimc.c111 bool bypass; member
132 u32 bypass; member
1025 sc->range, sc->bypass, sc->up_h, sc->up_v); in fimc_set_scaler()
1040 if (sc->bypass) in fimc_set_scaler()
/drivers/mfd/
Darizona-core.c920 !arizona->pdata.micbias[i].bypass) in arizona_dev_init()
940 if (arizona->pdata.micbias[i].bypass) in arizona_dev_init()
/drivers/net/ethernet/chelsio/cxgb4/
Dcxgb4.h309 unsigned char bypass; member
905 return adap->params.bypass; in is_bypass()
/drivers/cpufreq/
DKconfig.x86285 option lets the probing code bypass some of those checks if the
/drivers/infiniband/hw/cxgb3/
Dcxio_wr.h402 struct t3_bypass_wr bypass; member

12