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Searched refs:cacheline_size (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_pm.c932 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
939 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
946 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
953 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
960 .cacheline_size = G4X_FIFO_LINE_SIZE,
967 .cacheline_size = G4X_FIFO_LINE_SIZE,
974 .cacheline_size = G4X_FIFO_LINE_SIZE,
981 .cacheline_size = G4X_FIFO_LINE_SIZE,
988 .cacheline_size = I915_FIFO_LINE_SIZE,
995 .cacheline_size = I915_FIFO_LINE_SIZE,
[all …]
Dintel_drv.h495 unsigned long cacheline_size; member
/drivers/pci/
Dpci.c2840 u8 cacheline_size; in pci_set_cacheline_size() local
2847 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
2848 if (cacheline_size >= pci_cache_line_size && in pci_set_cacheline_size()
2849 (cacheline_size % pci_cache_line_size) == 0) in pci_set_cacheline_size()
2855 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); in pci_set_cacheline_size()
2856 if (cacheline_size == pci_cache_line_size) in pci_set_cacheline_size()
/drivers/net/ethernet/broadcom/
Dtg3.c17004 int cacheline_size; in tg3_calc_dma_bndry() local
17010 cacheline_size = 1024; in tg3_calc_dma_bndry()
17012 cacheline_size = (int) byte * 4; in tg3_calc_dma_bndry()
17052 switch (cacheline_size) { in tg3_calc_dma_bndry()
17077 switch (cacheline_size) { in tg3_calc_dma_bndry()
17094 switch (cacheline_size) { in tg3_calc_dma_bndry()