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Searched refs:caps (Results 1 – 25 of 431) sorted by relevance

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/drivers/net/ethernet/mellanox/mlx4/
Dmain.c173 for (i = 0; i < dev->caps.num_ports - 1; i++) { in mlx4_check_port_params()
175 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { in mlx4_check_port_params()
182 for (i = 0; i < dev->caps.num_ports; i++) { in mlx4_check_port_params()
183 if (!(port_type[i] & dev->caps.supported_type[i+1])) { in mlx4_check_port_params()
196 for (i = 1; i <= dev->caps.num_ports; ++i) in mlx4_set_port_mask()
197 dev->caps.port_mask[i] = dev->caps.port_type[i]; in mlx4_set_port_mask()
202 struct mlx4_caps *dev_cap = &dev->caps; in mlx4_enable_cqe_eqe_stride()
263 dev->caps.num_ports = dev_cap->num_ports; in mlx4_dev_cap()
265 for (i = 1; i <= dev->caps.num_ports; ++i) { in mlx4_dev_cap()
266 dev->caps.vl_cap[i] = dev_cap->max_vl[i]; in mlx4_dev_cap()
[all …]
Dqp.c375 (dev->caps.num_qps - 1), qp); in mlx4_qp_alloc()
441 radix_tree_delete(&dev->qp_table_tree, qp->qpn & (dev->caps.num_qps - 1)); in mlx4_qp_remove()
483 ALIGN(dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], 8); in mlx4_init_qp_table()
488 int last_base = dev->caps.num_qps; in mlx4_init_qp_table()
495 if (dev->caps.reserved_qps_cnt[sort[j]] > in mlx4_init_qp_table()
496 dev->caps.reserved_qps_cnt[sort[j - 1]]) { in mlx4_init_qp_table()
505 last_base -= dev->caps.reserved_qps_cnt[sort[i]]; in mlx4_init_qp_table()
506 dev->caps.reserved_qps_base[sort[i]] = last_base; in mlx4_init_qp_table()
508 dev->caps.reserved_qps_cnt[sort[i]]; in mlx4_init_qp_table()
524 err = mlx4_bitmap_init(&qp_table->bitmap, dev->caps.num_qps, in mlx4_init_qp_table()
[all …]
Deq.c89 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV) in get_async_ev_mask()
155 if (i != dev->caps.function && in mlx4_gen_slave_eqe()
278 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_get_slave_port_state()
295 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in mlx4_set_slave_port_state()
341 if (slave >= dev->num_slaves || port > dev->caps.num_ports || in set_and_calc_slave_port_state()
465 int eqe_size = dev->caps.eqe_size; in mlx4_eq_int()
467 while ((eqe = next_eqe_sw(eq, dev->caps.eqe_factor, eqe_size))) { in mlx4_eq_int()
502 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
534 if (!ret && slave != dev->caps.function) { in mlx4_eq_int()
566 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) { in mlx4_eq_int()
[all …]
Dpd.c122 return mlx4_bitmap_init(&priv->pd_bitmap, dev->caps.num_pds, in mlx4_init_pd_table()
124 dev->caps.reserved_pds, 0); in mlx4_init_pd_table()
137 (1 << 16) - 1, dev->caps.reserved_xrcds + 1, 0); in mlx4_init_xrcd_table()
155 dev->caps.uar_page_size); in mlx4_uar_alloc()
220 bf->buf_size = dev->caps.bf_reg_size / 2; in mlx4_bf_alloc()
221 bf->reg = uar->bf_map + idx * dev->caps.bf_reg_size; in mlx4_bf_alloc()
222 if (uar->free_bf_bmap == (1 << dev->caps.bf_regs_per_page) - 1) in mlx4_bf_alloc()
252 idx = (bf->reg - bf->uar->bf_map) / dev->caps.bf_reg_size; in mlx4_bf_free()
271 if (dev->caps.num_uars <= 128) { in mlx4_init_uar_table()
273 dev->caps.num_uars); in mlx4_init_uar_table()
[all …]
Dprofile.c188 dev->caps.num_qps = profile[i].num; in mlx4_make_profile()
197 dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift; in mlx4_make_profile()
209 dev->caps.num_srqs = profile[i].num; in mlx4_make_profile()
214 dev->caps.num_cqs = profile[i].num; in mlx4_make_profile()
219 dev->caps.num_eqs = roundup_pow_of_two(min_t(unsigned, dev_cap->max_eqs, in mlx4_make_profile()
222 init_hca->log_num_eqs = ilog2(dev->caps.num_eqs); in mlx4_make_profile()
225 dev->caps.num_mpts = profile[i].num; in mlx4_make_profile()
234 dev->caps.num_mtts = profile[i].num; in mlx4_make_profile()
243 if (dev->caps.steering_mode == in mlx4_make_profile()
245 dev->caps.num_mgms = profile[i].num; in mlx4_make_profile()
[all …]
Dfw.c244 find_first_bit(actv_ports.ports, dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
272 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], in mlx4_QUERY_FUNC_CAP_wrapper()
284 bitmap_weight(actv_ports.ports, dev->caps.num_ports), in mlx4_QUERY_FUNC_CAP_wrapper()
285 dev->caps.num_ports); in mlx4_QUERY_FUNC_CAP_wrapper()
288 size = dev->caps.function_caps; /* set PF behaviours */ in mlx4_QUERY_FUNC_CAP_wrapper()
296 size = dev->caps.num_qps; in mlx4_QUERY_FUNC_CAP_wrapper()
301 size = dev->caps.num_srqs; in mlx4_QUERY_FUNC_CAP_wrapper()
306 size = dev->caps.num_cqs; in mlx4_QUERY_FUNC_CAP_wrapper()
309 size = dev->caps.num_eqs; in mlx4_QUERY_FUNC_CAP_wrapper()
312 size = dev->caps.reserved_eqs; in mlx4_QUERY_FUNC_CAP_wrapper()
[all …]
Dsense.c72 for (i = 1; i <= dev->caps.num_ports; i++) { in mlx4_do_sense_ports()
75 dev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { in mlx4_do_sense_ports()
86 for (i = 0; i < dev->caps.num_ports; i++) in mlx4_do_sense_ports()
101 mlx4_do_sense_ports(dev, stype, &dev->caps.port_type[1]); in mlx4_sense_port()
120 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) in mlx4_start_sense()
139 for (port = 1; port <= dev->caps.num_ports; port++) in mlx4_sense_init()
Dport.c61 table->max = 1 << dev->caps.log_num_macs; in mlx4_init_mac_table()
74 table->max = (1 << dev->caps.log_num_vlans) - MLX4_VLAN_REGULAR; in mlx4_init_vlan_table()
243 return dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + in mlx4_get_base_qpn()
244 (port - 1) * (1 << dev->caps.log_num_macs); in mlx4_get_base_qpn()
254 if (port < 1 || port > dev->caps.num_ports) { in __mlx4_unregister_mac()
492 int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps) in mlx4_get_port_ib_caps() argument
521 *caps = *(__be32 *) (outbuf + 84); in mlx4_get_port_ib_caps()
543 max_port_p_one = find_first_bit(actv_ports.ports, dev->caps.num_ports) + in mlx4_get_slave_num_gids()
544 bitmap_weight(actv_ports.ports, dev->caps.num_ports) + 1; in mlx4_get_slave_num_gids()
549 bitmap_zero(exclusive_ports.ports, dev->caps.num_ports); in mlx4_get_slave_num_gids()
[all …]
/drivers/net/wireless/ath/ath5k/
Dcaps.c35 struct ath5k_capabilities *caps = &ah->ah_capabilities; in ath5k_hw_set_capabilities() local
39 ee_header = caps->cap_eeprom.ee_header; in ath5k_hw_set_capabilities()
46 caps->cap_range.range_5ghz_min = 5120; in ath5k_hw_set_capabilities()
47 caps->cap_range.range_5ghz_max = 5430; in ath5k_hw_set_capabilities()
48 caps->cap_range.range_2ghz_min = 0; in ath5k_hw_set_capabilities()
49 caps->cap_range.range_2ghz_max = 0; in ath5k_hw_set_capabilities()
52 __set_bit(AR5K_MODE_11A, caps->cap_mode); in ath5k_hw_set_capabilities()
69 if (ath_is_49ghz_allowed(caps->cap_eeprom.ee_regdomain)) in ath5k_hw_set_capabilities()
70 caps->cap_range.range_5ghz_min = 4920; in ath5k_hw_set_capabilities()
72 caps->cap_range.range_5ghz_min = 5005; in ath5k_hw_set_capabilities()
[all …]
/drivers/video/fbdev/
Damba-clcd.c132 u32 caps; in clcdfb_set_bitfields() local
135 if (fb->panel->caps && fb->board->caps) in clcdfb_set_bitfields()
136 caps = fb->panel->caps & fb->board->caps; in clcdfb_set_bitfields()
139 caps = fb->panel->cntl & CNTL_BGR ? in clcdfb_set_bitfields()
142 caps &= ~CLCD_CAP_444; in clcdfb_set_bitfields()
147 caps &= ~CLCD_CAP_888; in clcdfb_set_bitfields()
161 caps &= CLCD_CAP_5551; in clcdfb_set_bitfields()
162 if (!caps) { in clcdfb_set_bitfields()
177 if (!(caps & (CLCD_CAP_444 | CLCD_CAP_5551 | CLCD_CAP_565))) { in clcdfb_set_bitfields()
186 if (var->green.length == 4 && caps & CLCD_CAP_444) in clcdfb_set_bitfields()
[all …]
/drivers/infiniband/hw/mlx4/
Dmain.c103 int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED; in check_flow_steering_support()
112 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) && in check_flow_steering_support()
114 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)); in check_flow_steering_support()
160 props->fw_ver = dev->dev->caps.fw_ver; in mlx4_ib_query_device()
166 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR) in mlx4_ib_query_device()
168 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR) in mlx4_ib_query_device()
170 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports) in mlx4_ib_query_device()
172 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT) in mlx4_ib_query_device()
174 if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) in mlx4_ib_query_device()
176 if (dev->dev->caps.max_gso_sz && in mlx4_ib_query_device()
[all …]
/drivers/mmc/core/
Dhost.c329 host->caps |= MMC_CAP_8_BIT_DATA; in mmc_of_parse()
332 host->caps |= MMC_CAP_4_BIT_DATA; in mmc_of_parse()
359 host->caps |= MMC_CAP_NONREMOVABLE; in mmc_of_parse()
364 host->caps |= MMC_CAP_NEEDS_POLL; in mmc_of_parse()
414 host->caps |= MMC_CAP_SD_HIGHSPEED; in mmc_of_parse()
416 host->caps |= MMC_CAP_MMC_HIGHSPEED; in mmc_of_parse()
418 host->caps |= MMC_CAP_UHS_SDR12; in mmc_of_parse()
420 host->caps |= MMC_CAP_UHS_SDR25; in mmc_of_parse()
422 host->caps |= MMC_CAP_UHS_SDR50; in mmc_of_parse()
424 host->caps |= MMC_CAP_UHS_SDR104; in mmc_of_parse()
[all …]
Dsdio_irq.c57 !(host->caps & MMC_CAP_SDIO_IRQ)) { in process_sdio_pending_irqs()
117 period = (host->caps & MMC_CAP_SDIO_IRQ) ? in sdio_irq_thread()
160 if (!(host->caps & MMC_CAP_SDIO_IRQ)) { in sdio_irq_thread()
171 if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_irq_thread()
181 if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_irq_thread()
210 } else if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_card_irq_get()
231 } else if (host->caps & MMC_CAP_SDIO_IRQ) { in sdio_card_irq_put()
248 if ((card->host->caps & MMC_CAP_SDIO_IRQ) && in sdio_single_irq_set()
Dsdio.c213 if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) in sdio_enable_wide()
270 if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) in sdio_disable_wide()
303 if ((card->host->caps & MMC_CAP_4_BIT_DATA) && in sdio_enable_4bit_bus()
327 if (!(card->host->caps & MMC_CAP_SD_HIGHSPEED)) in mmc_sdio_switch_hs()
418 if (!(card->host->caps & in sdio_select_driver_type()
427 if (card->host->caps & MMC_CAP_DRIVER_TYPE_A) in sdio_select_driver_type()
430 if (card->host->caps & MMC_CAP_DRIVER_TYPE_C) in sdio_select_driver_type()
433 if (card->host->caps & MMC_CAP_DRIVER_TYPE_D) in sdio_select_driver_type()
488 if ((card->host->caps & MMC_CAP_UHS_SDR104) && in sdio_set_bus_speed_mode()
494 } else if ((card->host->caps & MMC_CAP_UHS_DDR50) && in sdio_set_bus_speed_mode()
[all …]
/drivers/ptp/
Dptp_chardev.c120 struct ptp_clock_caps caps; in ptp_ioctl() local
134 memset(&caps, 0, sizeof(caps)); in ptp_ioctl()
135 caps.max_adj = ptp->info->max_adj; in ptp_ioctl()
136 caps.n_alarm = ptp->info->n_alarm; in ptp_ioctl()
137 caps.n_ext_ts = ptp->info->n_ext_ts; in ptp_ioctl()
138 caps.n_per_out = ptp->info->n_per_out; in ptp_ioctl()
139 caps.pps = ptp->info->pps; in ptp_ioctl()
140 caps.n_pins = ptp->info->n_pins; in ptp_ioctl()
141 if (copy_to_user((void __user *)arg, &caps, sizeof(caps))) in ptp_ioctl()
Dptp_ixp46x.c43 struct ptp_clock_info caps; member
141 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_adjfreq()
164 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_adjtime()
183 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_gettime()
202 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_settime()
220 struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps); in ptp_ixp_enable()
307 ixp_clock.caps = ptp_ixp_caps; in ptp_ixp_init()
309 ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps, NULL); in ptp_ixp_init()
/drivers/mmc/host/
Datmel-mci.c219 struct atmel_mci_caps caps; member
408 if (host->caps.has_odd_clk_div) in atmci_regs_show()
422 if (host->caps.has_cstor_reg) in atmci_regs_show()
430 if (host->caps.has_dma_conf_reg) { in atmci_regs_show()
440 if (host->caps.has_cfg_reg) { in atmci_regs_show()
749 if (!host->caps.has_rwproof) { in atmci_pdc_set_single_buf()
814 if ((!host->caps.has_rwproof) in atmci_pdc_complete()
816 if (host->caps.has_bad_data_ordering) in atmci_pdc_complete()
851 if (host->caps.has_dma_conf_reg) in atmci_dma_complete()
969 if ((!host->caps.has_rwproof) in atmci_prepare_data_pdc()
[all …]
Dsdhci-acpi.c57 unsigned long caps; member
66 unsigned long caps; member
182 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
194 .caps = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD |
206 .caps = MMC_CAP_WAIT_WHILE_BUSY,
336 host->mmc->caps |= c->slot->chip->caps; in sdhci_acpi_probe()
342 host->mmc->caps |= c->slot->caps; in sdhci_acpi_probe()
/drivers/hwmon/
Dacpi_power_meter.c93 struct acpi_power_meter_capabilities caps; member
169 if (temp > resource->caps.max_avg_interval || in set_avg_interval()
170 temp < resource->caps.min_avg_interval) in set_avg_interval()
241 if (temp > resource->caps.max_cap || temp < resource->caps.min_cap) in set_cap()
331 msecs_to_jiffies(resource->caps.sampling_time)) && in update_meter()
403 val = resource->caps.min_avg_interval; in show_val()
406 val = resource->caps.max_avg_interval; in show_val()
409 val = resource->caps.min_cap * 1000; in show_val()
412 val = resource->caps.max_cap * 1000; in show_val()
415 if (resource->caps.hysteresis == UNKNOWN_HYSTERESIS) in show_val()
[all …]
/drivers/clk/at91/
Dpmc.c115 const struct at91_pmc_caps *caps = pmc->caps; in pmc_irq_domain_xlate() local
122 if (!(caps->available_irqs & (1 << *out_hwirq))) in pmc_irq_domain_xlate()
194 const struct at91_pmc_caps *caps) in at91_pmc_init() argument
198 if (!regbase || !virq || !caps) in at91_pmc_init()
210 pmc->caps = caps; in at91_pmc_init()
350 const struct at91_pmc_caps *caps) in of_at91_pmc_setup() argument
366 pmc = at91_pmc_init(np, regbase, virq, caps); in of_at91_pmc_setup()
/drivers/acpi/
Dvideo_detect.c197 long caps = 0; in acpi_video_get_capabilities() local
208 &caps, NULL); in acpi_video_get_capabilities()
210 acpi_video_support |= caps; in acpi_video_get_capabilities()
230 &caps, NULL); in acpi_video_get_capabilities()
233 graphics_handle ? caps : acpi_video_support, in acpi_video_get_capabilities()
236 return caps; in acpi_video_get_capabilities()
/drivers/net/wireless/ath/ath9k/
Dcommon-init.c134 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) { in ath9k_cmn_init_channels_rates()
151 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) { in ath9k_cmn_init_channels_rates()
185 if (ah->caps.hw_caps & ATH9K_HW_CAP_LDPC) in ath9k_cmn_setup_ht_cap()
188 if (ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) in ath9k_cmn_setup_ht_cap()
234 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_HT)) in ath9k_cmn_reload_chainmask()
237 if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ) in ath9k_cmn_reload_chainmask()
240 if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ) in ath9k_cmn_reload_chainmask()
/drivers/memory/
Datmel-sdramc.c56 const struct at91_ramc_caps *caps; in atmel_ramc_probe() local
60 caps = match->data; in atmel_ramc_probe()
62 if (caps->has_ddrck) { in atmel_ramc_probe()
69 if (caps->has_mpddr_clk) { in atmel_ramc_probe()
/drivers/media/usb/tm6000/
Dtm6000-cards.c75 struct tm6000_capabilities caps; member
93 .caps = {
120 .caps = {
146 .caps = {
174 .caps = {
213 .caps = {
239 .caps = {
264 .caps = {
291 .caps = {
321 .caps = {
[all …]
/drivers/net/phy/
Ddp83640.c143 struct ptp_clock_info caps; member
379 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_adjfreq()
412 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_adjtime()
433 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_gettime()
458 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_settime()
475 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_enable()
519 container_of(ptp, struct dp83640_clock, caps); in ptp_dp83640_verify()
521 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC && in ptp_dp83640_verify()
985 kfree(clock->caps.pin_config); in dp83640_free_clocks()
999 clock->caps.owner = THIS_MODULE; in dp83640_clock_init()
[all …]

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